Patent Application
20120000421
1. Field of the Invention
Embodiments of the invention relate to the field of plasma processing systems. More particularly, the present invention relates to an apparatus and method for improving and regulating voltage coupling for insulating target substrates used in plasma immersion ion implantation.
2. Discussion of Related Art
Plasmas are used in a variety of ways in semiconductor processing to implant wafers or substrates with various dopants, to deposit or to etch thin films. Such processes involve the directional deposition or doping of ions on or beneath the surface of a target substrate. Other processes include plasma etching, where the directionality of the etching species determines the quality of the trenches to be etched.
Generally, plasma immersion ion implantation (PIII), also referred to as plasma doping (PLAD), implants dopants into a substrate. The plasma is generated by supplying energy to a neutral gas introduced into a chamber to form charged carriers which are implanted into the target substrate. PLAD systems are typically used when shallow junctions are required in the manufacture of semiconductor devices where lower ion implant energies confine the dopant ions near the surface of the target substrate or wafer. In these situations, the depth of implantation is related to the voltage applied between the wafer and an anode within a plasma processing chamber of a PLAD system or tool. In particular, a wafer is positioned on a platen, which functions as a cathode, within the chamber. An ionizable gas containing the desired dopant materials is introduced into the plasma chamber. The gas is ionized by any of several methods of plasma generation, including, but not limited to DC glow discharge, capacitively coupled RF, inductively coupled RF, etc.
Once the plasma is generated, there exists a plasma sheath between the plasma and all surrounding surfaces, including the target substrate. The sheath is essentially a layer in the plasma which has a greater density of positive ions (i.e. excess positive charge), as compared to an opposite negative charge on the surface of the target substrate. The platen and substrate are then biased with a negative voltage in order to cause the ions from the plasma to cross the plasma sheath and be implanted into or deposited on the wafer at a depth proportional to the applied bias voltage.
Implantation using a PLAD tool is typically limited to conducting substrates or a semiconductive (e.g., Si) workpiece due to the ability to bias a conductive substrate to attract ions across the plasma sheath for implantation therein. To fabricate certain types of devices, there is a need to implant particular dopants in insulating or insulator substrates such as glass, quartz, etc. However, it is difficult to couple voltage through an insulating substrate in order to maintain the proper biasing of the substrate to attract the ions across the plasma sheath for implantation. In particular, for relatively thick insulating substrates, voltage coupling is limited by the low capacitance of the insulator substrate as compared to the capacitance of the plasma sheath above the surface of the substrates. This leads to a voltage divider circuit where most of the voltage is dropped across the substrate. For thin insulating substrates used in, for example, flat panel displays, a reasonable portion of the voltage is coupled to the substrate, but is quickly degraded. This is due, in part, to positive charging of the insulator substrate when the ions are implanted as well as the generation of secondary electrons when the ions strike the surface of the insulator substrate.
This is generally shown in
where a(t) represents the drop in effective voltage due to the surface charging of the insulator substrate 1 caused by the implanted ions together with the generated secondary electrons, and b(t) represents the capacitive divider of the insulator substrate 1 and sheath 4. Because the target substrate is an insulator, the properties of sheath 4 changes and a capacitive divider may exist thereby reducing the effective voltage. In addition, the charge build-up on the surface of the insulator target substrate further reduces the effective voltage. If the effective voltage is too small, then the implantation process may be compromised. Thus, there is a need to reduce the charge build-up on the surface of an insulator target substrate used in a PLAD system which maintains the effective voltage to provide the desired implant characteristics.
Exemplary embodiments of the present invention are directed to a control apparatus for plasma immersion ion implantation of a dielectric substrate and an associated method. In an exemplary embodiment, a plasma processing tool comprises a plasma chamber configured to generate a plasma having ions from a gas introduced into the chamber. A platen is configured to support and electrically connect to an insulator substrate for plasma doping. The platen is connected to a voltage source supplying negative bias voltage pulses at a first potential to the platen and to the substrate. An electrode is disposed above the generated plasma and receives negative bias voltage pulses at a second potential where the second potential is more negative than the first potential in order to give the electrons provided from the second electrode sufficient energy to overcome the negative voltage of the high voltage sheath around the substrate thereby reaching the substrate. When the ions strike the electrode, secondary electrons are generated which are accelerated toward the substrate at the second potential to neutralize charge build-up on the substrate.
A method for neutralizing charge build-up on a surface of an insulator target substrate in a plasma processing tool is disclosed comprising providing a reactive gas to a chamber and exciting the reactive gas to generate a plasma having ions. First bias voltage pulses are applied to an insulator substrate disposed in the chamber. Second bias voltage pulses re applied to an electrode disposed above the plasma where the second bias voltage pulses have a higher potential than the first bias voltage pulses to attract the ions toward the electrode. Secondary electrons are generated when the attracted ions strike a surface of the electrode. The secondary electrons are accelerated-toward the insulator substrate to neutralize charge build-up present on a surface of the substrate.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
The target substrate 5 may be an insulating substrate used in flat panel displays. The target substrate may also be, for example, low-temperature polycrystalline silicon (LTPS), thin film transistors (TFT), organic light emitting diodes (OLED), solar cells, etc. As mentioned above, because the target substrate is an insulator (e.g. glass, quartz, etc.), the sheath above the target becomes a capacitive divider due to the low capacitance of the target substrate 5 as compared to the capacitance of the sheath between the plasma and the surface of the target substrate 5. This reduces the effective implant voltage Veff (given in Eq. 1 above) which is further reduced by the build-up of charge on the surface of the insulated target substrate 5. In particular, when target substrate 5 is biased with DC voltage pulses to attract the ions across the plasma sheath, charge tends to accumulate on the surface of substrate 5. When the pulsed-on cycles of the plasma implant process are relatively low, this charge build-up tends to be efficiently neutralized by electrons that are present in the plasma 20. However, when the pulsed-on cycles increase to achieve desired throughputs and to maintain doping levels that are required for some modern devices, there is a shorter period of time where the build-up on substrate 5 can be neutralized during the off cycles. Consequently, charge build-up occurs on the surface of substrate 5. This may result in a relatively high potential voltage on the substrate which causes doping non-uniformities, arcing, and device damage. In other words, both the charge build-up and the reduced effective voltage negatively effects the implantation process.
The build-up of charge on the surface of the insulating target substrate 5 may be neutralized by providing a source of electrons (negative charge) to substrate 5. This is accomplished by providing an electrode 25 which may be, for example, in the form of a plate disposed below and insulated from baffle 11 by insulating portion 26 since baffle 11 is typically at ground potential. The electrode 25 is a conducting material which is compatible with plasma environments and may be, for example, aluminum, low resistivity SiC or Silicon coated aluminum. Alternatively, electrode 25 may be integrally formed with baffle 11 in which case baffle 11 is electrically isolated from the walls of chamber 12 and is configured to maintain the desired electrode potential to neutralize the charge build-up on the surface of target substrate 5. Generally, the charge build-up on the substrate 5 is neutralized by generating secondary electrons as a result of ions striking the surface of electrode plate 25 which are accelerated toward the cathode (substrate 5) at the potential placed on electrode plate 25.
This may be better understood by turning to
When these secondary electrons reach sheath 20a, they are decelerated. Because the voltage of electrode plate 25 is slightly higher than that of the insulator substrate 5, the secondary electrons generated from the electrode plate will reach substrate 5 through the high voltage sheath around the substrate 5 with very low energy, for example, typically less than 100V. These electrons neutralize the surface charge built-up on substrate 5. Ideally, for every ion that gets implanted in substrate 5 which generates a positive charge that builds-up on the surface thereof, a secondary electron from electrode plate 25 reaches substrate 5 and neutralizes a corresponding positive charge. This yield of secondary electrons from electrode plate 25 may be maximized to provide sufficient neutralization of the charge build-up on the surface of substrate 5. This may be accomplished by ensuring that the area of electrode plate 25 is greater than the area of substrate 5. In addition, electrode plate 25 may be configured to have a surface roughness to increase the incident angle of electrode plate 25, thereby increasing secondary electron yields. Alternatively, the surface of electrode plate 25 may be machined or treated to increase the probability of ion incidence and/or the electrode plate may be heated to its maximum thermal stability. By heating the electrode plate, the energy of the electrons in the conduction band increases, thereby increasing the probability of an electron being emitted from the surface.
As described above with respect to
In particular, the insulating layer 155 is selected to have the same properties as the insulating substrate 105. The insulating layer 155 is disposed on shield ring 150. Shield ring 150 is electrically connected to and functions as an extension of platen 114. In this manner, the bias voltage pulses applied to platen 114 are likewise applied to shield ring 150. Metal layer 160 is relatively thin, typically 10's of microns thick, and is used to monitor the voltage at the insulator target substrate. This monitored voltage represents the voltage at the surface of the insulator target substrate 105 being implanted. Based on this monitored voltage, the voltage pulses supplied to the electrode plate 125 may be controlled to attract ions from plasma 120. This in turn determines the generation of secondary electrons used to neutralize the charge build-up on the surface of insulator substrate 105.
The closed loop system includes shield ring 150 which is an extension of, and electrically connected to platen 114. Insulator 155 is disposed on shield ring 150 around the periphery of insulator substrate 105. This allows the same bias voltage applied to platen 114 to also be applied to shield ring 150 and consequently, insulator 155. By disposing the shield ring and insulator around the periphery of platen 114 and target insulator substrate 105 respectively, the closed loop system mimics the implant process received by substrate 105. Metal layer 160 is disposed on insulator 155 and a voltage monitor (probe) 165 is connected thereto to measure the surface voltage on insulator 155. This measured voltage on the surface of insulator 155 is understood to be the charge build-up generated on the surface of insulator substrate 105 since the insulator 155 is disposed around the periphery of substrate 105. Based on the measured voltage on the surface of insulator 155, the voltage pulses 130 applied to electrode 125 may be adjusted and/or controlled such that number of secondary electrons generated by ions that strike the surface of electrode 125 is sufficient to obtain the desired voltage on the surface of insulator target substrate 105.
In addition, the width of the voltage pulses 130 applied to electrode plate 125 may be adjusted to provide a longer pulse to attract ions toward the plate thereby increasing the number of secondary electrons generated. Moreover, a plurality of voltage pulses applied to the electrode 125 may occur within the timing of one pulse applied to the substrate. In particular,
Alternatively, the temperature of the electrode 125 may be controlled which impacts the number of secondary electrons generated when ions strike the surface. This may be used as an initial control to neutralize charge build-up on the surface of the substrate without the use of the control loop system comprised of the shield ring 150, insulator 155 and metal layer 160. In this manner, once the initial control of the charge build-up on the surface of the substrate is managed by changing the temperature of electrode 125, then the closed loop control system may be used to fine tune the generation of secondary electrons and neutralize charge build-up.
While the present invention has been disclosed with reference to certain embodiments, numerous modifications, alterations and changes to the described embodiments are possible without departing from the sphere and scope of the present invention, as defined in the appended claims. Accordingly, it is intended that the present invention not be limited to the described embodiments, but that it has the full scope defined by the language of the following claims, and equivalents thereof.
