Patent Application
20080142996
The disclosed embodiments relate generally to the manufacture of integrated circuit devices, and more particularly to controlling the flow of an underfill material over the surface of a substrate.
To package an integrated circuit (IC) die, the die is typically disposed on one surface of a substrate and electrically coupled with the substrate. By way of example, for a flip chip attachment process, an array of electrically conductive terminals on the die (e.g., metal bumps or columns) is coupled with a mating array of electrically conductive terminals on the substrate (e.g., metal pads or lands, solder bumps, etc.) to form a number of interconnects extending between the die and substrate. The substrate includes a number of electrically conductive terminals (e.g., metal bumps, columns, pins, etc.) on an opposing surface to electrically couple the package with a next-level component, such as a printed circuit board (e.g., a motherboard).
Both the interconnects attaching the IC die to the substrate and an interconnect structure (which may include a low-k dielectric material) formed over the active surface of the die may be susceptible to cracking or other failures resulting from thermally induced stresses and warpage. To improve the robustness of the above-described electrical (and mechanical) coupling between the die and substrate, as well as to minimize the effects of thermally induced stresses and warpage, a layer of an underfill material (e.g., an epoxy) may be disposed between the IC die and substrate. A common method to dispense an underfill material under a flip-chip mounted die is to dispense the underfill along one edge (or multiple edges) of the IC die and utilize capillary flow to draw the underfill into the space between the die and substrate. To achieve the desired capillary flow, a low viscosity underfill material may be used and/or the underfill may be heated to lower its viscosity. Due, at least in part, to this low viscosity, a “tongue” of underfill material may be created on the substrate surface adjacent the die.
The surface area of a substrate reserved for the mounting of other components (e.g., capacitors and other passive devices, other IC devices, etc.), or more generally that portion of the substrate surface where underfill flow is undesired, may be referred to as the keep-out zone (KOZ). The aforementioned underfill “tongue” remaining on the substrate can limit the KOZ, necessitating the use of a larger substrate to allow for formation of the tongue. However, for small form factor packages, as well as other packages, it may be desirable to use a smaller substrate to minimize the package's footprint. Thus, controlling the flow of underfill material on the substrate surface and maintaining the boundaries of the KOZ may be important considerations in the manufacture of small form factor packages. The ability to maintain the KOZ can enable the use of smaller substrates, as well as the closer spacing of IC die and/or other components (e.g., passives) on the substrate.
Illustrated in
Referring to
On the first side 112 of substrate 110, a die region 120 is provided. An integrated circuit (IC) die may be mounted on the package substrate 100 within the die region 120. Disposed within the die region 120 on the substrate first surface 112 is a number of electrically conductive terminals 130. According to one embodiment, the electrically conductive terminals 130 comprises an array of pads or lands that are arranged to mate with a corresponding array of terminals formed on an IC die that is to be flip-chip mounted on the package substrate 100. In this embodiment, the conductive terminals 130 may comprise copper (or a copper alloy or other metal) pads, and in a further embodiment solder bumps may be disposed on these copper pads (and the mating terminals on the IC die may, in one embodiment, comprise copper or other metal bumps or columns electrically coupled with the terminals 130 by, for example, a reflow process). It should be understood, however, that the disclosed embodiments are not limited to substrates adapted for flip-chip bonding and, further, that the electrically conductive terminals 130 may comprise any other type of terminal or element that may be used to form an electrical connection with an IC device (e.g., bond pads for wirebonding, etc.).
In another embodiment, a number of electrically conductive terminals (not shown in figures) may also be disposed on the substrate's opposing second side 114. The conductive terminals on the substrate's second side 114 may comprise metal bumps, columns, pins, etc., and these terminals may be used to electrically couple the package substrate 100 with a next-level component (e.g., a motherboard or other a printed circuit board, etc.).
Disposed on the first side 112 of substrate 110 is a polymer layer or coating 140. The polymer coating 140 comprises any polymer capable of impeding or inhibiting the flow of an underfill material. In one embodiment, the polymer coating 140 is arranged in a pattern that defines a keep-out zone (KOZ) or that otherwise prevents (or at least inhibits) the flow of underfill into the KOZ. For example, as shown in
In the embodiment of
As noted above, the polymer coating 140 may comprise any polymer capable of at least partially impeding the flow of an underfill material. In one embodiment, the polymer coating comprises a material that is non-wetting with respect to an underfill material. In another embodiment, the polymer coating 140 comprises a material having a surface energy in a range of approximately 6 mN/m to 20 mN/m. In a further embodiment, the polymer coating 140 comprises any polymer material that provides a contact angle greater than (or equal to) approximately 90 degrees. Also, in yet another embodiment, one or more properties of the polymer coating 140 may be altered by a thermal treatment. For example, a thermal treatment may be performed to cross-link the polymer, to alter the surface energy and/or contact angle (or to otherwise alter the wetting behavior), to alter another aspect of the polymer's surface chemistry, etc. According to one embodiment, the polymer coating 140 comprises a fluoropolymer. However, it should be understood that other polymer materials may also find application to the disclosed embodiments.
The polymer coating 140 may be disposed on the substrate 110 using any suitable process. For example, in one embodiment, the polymer material may be dispensed on the substrate using a needle. The needle dispenser can be moved relative to the substrate to trace out the desired pattern of polymer. In another embodiment, a pattern of the polymer material may be formed on the substrate by stencil printing. In a further embodiment, a pattern of the polymer material may be created by forming a mask over the substrate and then applying a layer of the polymer material by spin coating (or other blanket deposition technique). As the reader will appreciate, other processes and/or devices may be used to form the desired pattern of polymer material on the substrate. In one embodiment, the polymer may be dispensed in a solution including a solvent (e.g., a fluoropolymer in a solution including a fluorosolvent).
Referring now to
With reference to
After (or, alternatively, prior to) formation of the interconnects 275, an underfill material 290 is disposed between the IC die 270 and substrate 100. In one embodiment, the underfill layer 290 forms a mechanical bond between the IC die 270 and substrate 100 In another embodiment, the underfill layer 290 provides support to, and increases the strength of, the interconnects 275. The underfill 290 may comprise any material capable of performing one or more of the above-described as well as other functions. In one embodiment, the underfill material 290 comprises an epoxy. Typically, the underfill material 290 would be dispensed onto the substrate in a region between the polymer coating 140 and the adjacent edge of the IC die 270, and the underfill material flows between the IC die and substrate 110 due to capillary flow.
As shown in
Turning to
The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for a clear and comprehensive understanding of the disclosed embodiments and no unnecessary limitations are to be understood therefrom. Numerous additions, deletions, and modifications to the embodiments described herein, as well as alternative arrangements, may be devised by those skilled in the art without departing from the spirit of the disclosed embodiments and the scope of the appended claims.
