Patent Application
20210225803
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The Applicant has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Further, no references to third party patents or articles made herein is to be construed as an admission that the present invention is not entitled to antedate such material by virtue of prior invention.
The invention relates to an industrial system for forming covalently bonded semiconductor interfaces, the structure of covalently bonded semiconductor interfaces, and to methods for forming such interfaces at CMOS compatible temperatures.
The formation of an electrically conductive, covalent bond formed between two semiconductor wafers has met increasing interest in the past few decades. Especially covalent semiconductor bonding carried out at low temperatures (typically between room temperature and about 300° C.) may lead to monolithic structures which cannot be realized in any other way, since often the bonding partners comprise materials which do not allow any high temperature processing. This is the case, for example, for CMOS processed wafers containing a temperature sensitive stack of dielectric and metallic layers, or wafers made of materials with different thermal expansion coefficients and/or lattice parameters. Low bonding temperatures alone do not guarantee unimpaired electrical conduction across a bonding interface. In addition, the surfaces of both bonding partners must typically be atomically clean and oxide-free as well as smooth and flat. Clean silicon wafers have been shown to be spontaneously bondable at room temperature in a UHV (Ultra High Vacuum, defined hereinafter) bonding tool suitable for 100 mm wafer processing with bonds approaching bulk bond strength (see, for example, U. Gösele et al. in Appl. Phys. Lett. 67, 3614 (1995), the entire disclosure of which is hereby incorporated by reference). The question then is how to obtain clean semiconductor surfaces prior to low temperature bonding and how to keep them clean before the covalent bond is formed. This remains a serious issue, especially for materials which oxidize as easily as silicon. One way to obtain oxide-free silicon surfaces is wet chemical cleaning in the form of an HF dip. The resulting hydrogen termination passivates the surface and protects it from re-oxidation even in ambient atmosphere up to several hours. The hydrogen passivation needs to be removed before bonding, because hydrophobic bonding by means of hydrogen bridges is weak and therefore requires undesirable post-bonding annealing to temperatures above 700° C. to achieve high bond strength (see, for example, Q.-Y. Tong et al. in Appl. Phys. Lett. 64, 625 (1994), the entire disclosure of which is hereby incorporated by reference). Hydrogen can be removed from passivated surfaces by thermal annealing in ultra-high vacuum (UHV—attaining a base pressure in the range of about 1×10−9 to 1×10−10 mbar or even 10−10 to 10−11 mbar). This is the method used by Gösele et al. for Si—Si bonding, which, however, has the disadvantage of requiring temperatures above the monohydride desorption temperature of about 550° C. (see, for example, P. Gupta et al., in Phys. Rev. B 37, 8234 (1988) and U. Gösele et al. in Appl. Phys. Lett. 67, 3614 (1995), the entire disclosures of which are hereby incorporated by reference). Unfortunately, this is not compatible with fully CMOS processed wafers which require not only low temperatures during bonding but also in any pre-bonding cleaning step.
A possible way of removing surface oxides at low temperatures is the so-called surface activation method. It was originally introduced for Al—Al bonding by T. Suga et al. in Acta metall. mater. 40, 5133 (1992), the entire disclosure of which is hereby incorporated by reference. The method, essentially consisting of dry etching of the oxide by ion beam sputtering with ion energies on the order of 1 keV, was later shown to be applicable also to Si—Si bonding by Takagi et al. who coined the expression Surface Activated Bonding (SAB) (see, for example, H. Takagi et al. in Appl. Phys. Lett. 68, 2222 (1996), the entire disclosure of which is hereby incorporated by reference). Exceptionally high bond strength was achieved by the SAB method even for room temperature bonding. Dry etching of the oxide has, however, one drawback which is hard to avoid irrespective of the details of the parameters used. Surface bombardment by energetic ions inevitably causes surface damage during oxide removal, leading to an amorphous interlayer at the bonding interface with a thickness typically on the order of a few nanometres (see for example Takagi et al., in ECS Transactions 75, 3 (2016), the entire disclosure of which is hereby incorporated by reference). The high dangling bond density associated with the broken Si—Si bonds pins the Fermi level in the energy gap. The dangling bond density may be reduced by recrystallizing the amorphous layer, which, however, requires again annealing at temperatures typically above 500° C. Depending on the doping type and density of the bonding partners Fermi level pinning at the bonding interface may result in similar band bending and barrier formation as can be found at polycrystalline grain boundaries, with similar effects on the electrical properties. Especially for low doping densities, characterized by wide space charge regions through which tunnelling is impossible, the electrical resistance across such a bonding interface may exceed the bulk resistance by many orders of magnitude (see, for example, A. Jung et al. in J. Appl. Phys. 123, 085701 (2018), the entire disclosure of which is hereby incorporated by reference). Evidently, bonding of clean, crystalline surfaces in UHV may provide the lowest possible density of interface defect states, although, except for extremely accurate wafer alignment (both in terms of twist and tilt), barrier formation may not be prevented even in this case (see for example A. Reznicek et al. in MRS Symp. Proc. 681E, I4.4.1 (2001), the entire disclosure of which is hereby incorporated by reference).
A UHV bonding system for 200 mm wafers, based on SAB and comprising very accurate wafer alignment features, was introduced already in 2001 by Suga et al. at the 2001 Electronic Components and Technology Conference, the entire disclosure of which is hereby incorporated by reference. The wafer alignment up to a precision of ±0.5 μm, including maintaining parallelism between wafers, is established by means of piezo-actuators and infrared cameras, which is why the technique is limited to the bonding of infrared transparent wafers. While very suitable for the packaging of micro-electronic mechanical systems (MEMS), the amorphous semiconductor interfaces produced by this system are of major concern for the electric charge transport for the reasons explained above.
Similar drawbacks in terms of interfacial electric transport appear to exist for a high vacuum production tool introduced by EV Group but a few years ago (see for example, U.S. Pat. No. 9,899,223 to Wimplinger et al., the entire disclosure of which is hereby incorporated by reference). The reason is that here too dry etching of SiO2 by energetic ion bombardment results in amorphous interlayers several nanometres in width (see for example C. Flötgen et al., in ECS Transactions 64, 103 (2014), the entire disclosure of which is hereby incorporated by reference).
There is a need for a production system for covalent bonding of semiconductor wafers in ultrahigh vacuum up to 300 mm in size.
There is a need for a production system for covalent bonding of semiconductor wafers in ultrahigh vacuum comprising mutual wafer alignment at a 100 nm scale.
There is a need for a production system and process for covalent semiconductor wafer bonding which permits smooth, crystalline wafer surfaces to be created and maintained oxide-free for a length of time sufficient to carry out the bonding process under production conditions.
There is a need far a production system and process for covalent semiconductor wafer bonding which permits oxide removal and surface passivation without inducing surface amorphization.
There is a need for a production system and process for covalent semiconductor wafer bonding which permits the removal of passivating layers on wafers without inducing surface amorphization.
There is a need for a production system and process for covalent semiconductor wafer bonding which permits oxide-free, electrically conducting bonding interfaces to be created under production conditions.
There is a need for a production system and process permitting covalent semiconductor wafer bonding at temperatures compatible with CMOS processed wafer stacks.
There is a need for a production system and process for the covalent bonding of semiconductor wafers with different thermal expansion coefficients.
There is a need for a production system and process for covalent wafer bonding capable of providing bonding interfaces with defect densities low enough to ensure minimal interfacial barrier formation.
A production system for oxide-free, covalent semiconductor wafer bonding is provided. The system includes at least one module for wet chemical or vapour processing and at least one module for ultra-high vacuum (UHV) wafer processing. The module for wet chemical or vapour processing has chambers for oxide removal and for the provision of a surface passivation layer at or near atmospheric pressure. The module for ultra-high vacuum wafer processing includes at least one chamber. This chamber may be any one of the following: (i) a plasma chamber with a low energy plasma source and auxiliary laser irradiation suitable for the removal of surface passivation, (ii) an ultrahigh vacuum laser chamber with a visible or ultraviolet laser suitable for the photochemical or photo-thermal removal of a surface passivation layer, (iii) an ultrahigh vacuum thin film deposition chamber suitable for the provision of a thin, clean epitaxial semiconductor surface layer, (iv) an ultrahigh vacuum wafer flipping chamber, (v) an ultrahigh vacuum wafer annealing chamber, (vi) an ultrahigh vacuum wafer pre-alignment tool, and (v) an ultrahigh vacuum wafer bonding chamber comprising means for mutual wafer alignment at ultrahigh rotational and translational accuracy, the bonding chamber being optionally vibrationally decoupled from a wafer handling chamber. The modules for wet chemical and the modules for ultra-high vacuum processing are accessible through separate load-locks and are connected by at least one buffer chamber designed to avoid cross contamination during wafer transfer by robots in wafer handlers.
It is an object of the invention to provide a production system and process for the covalent, oxide- and particle-free bonding of semiconductor wafers up to 300 mm in size.
It is an object of the invention to provide a production system for the covalent, oxide- and particle-free bonding of semiconductor wafers up to 300 mm in size, mutually aligned with a precision in the 100 nm range.
It is an object of the invention to provide a production system and process for covalent wafer bonding for semiconductors with different thermal expansion coefficients.
It is an object of the invention to provide a production system and process for covalent, oxide-free semiconductor wafer bonding which combines modules for wet chemical wafer processing and modules for vacuum based wafer processing in a single machine.
It is an object of the invention to provide a production system and process for covalent semiconductor wafer bonding comprising an ultra-high vacuum (UHV) compatible environment to keep all clean wafer surfaces oxide-free.
It is an object of the invention to provide a production system and process for covalent semiconductor wafer bonding capable of providing clean, low-roughness wafer surfaces suitable for wafer bonding at CMOS compatible temperatures.
It is an object of the invention to provide a production system and process for covalent semiconductor wafer bonding capable of providing crystalline bonding interfaces at CMOS compatible temperatures.
It is an object of the invention to provide a production system and process for covalent semiconductor wafer bonding capable of providing bonding interfaces at CMOS compatible temperatures with minimal undesired electrical barrier formation by interfacial defect states.
It is an object of the invention to provide a production system and process for covalent semiconductor wafer bonding capable of providing bonding interfaces at CMOS compatible temperatures with minimal undesired electrical charge trapping and recombination at the bonding interface.
It is an object of the invention to provide a production system for covalent semiconductor wafer bonding of a modular design which is easy to service and maintain particle-free.
Referring now to
The first part 101 of the production system 100 for low-temperature covalent wafer bonding under UHV-compatible processing conditions comprises a central wafer handler 104 with a robot 108 capable of serving a multitude of processing chambers attached via UHV compatible gate valves 112. For average sized process chambers UHV of about (2−5)×10−10 mbar is attainable for example using a combination of a turbo-molecular vacuum pump available from Pfeiffer/Edwards and an Edwards scroll dry backing pump after baking for 24 h at 150° C. For example, with Ti sublimation pumps, cryopumps or ion getter pumps even lower pressures in the range of 10−10-10−11 mbar may be achieved. Central wafer handler 104 may be “bakeable” preferably to a temperature of about 150°-200° C. to remove moisture and to permit pumping to a base pressure of about 10−8 mbar or 10−8−5×10−9 mbar or even 5×10−9-10−10 mbar, for example, by a combination of turbomolecular and cryopumps. The production system comprises at least one load lock 116 for the insertion of wafer cassettes, equipped with vacuum pumps for evacuation to about 10−6-10−7 mbar or even less than 10−7 mbar. The at least one load lock 116 may optionally be equipped with provisions for wafer degassing, for example, at temperatures in the range of 100°-200° C. The production system 100 may further comprise one or several process chambers 120, 120′ with base pressures in the UHV range, dedicated to the removal of the surface passivation of wafers to expose clean semiconductor surfaces with reactive dangling bonds suitable for covalent semiconductor bonding. One process chamber 120′ may, for example, be a UHV laser processing chamber equipped for visible or UV laser exposure of the surfaces, the laser providing photon energies in a range of about 2-10 eV, permitting for example, either photochemical or photo-thermal hydrogen desorption from Si or other hydrogen passivated semiconductor surfaces (see, for example, A. Pusel et al., in Phys. Rev. Lett. 81, 645 (1998), the entire disclosure of which is hereby incorporated by reference). Laser processing chamber 120′ may be equipped with a rotatable wafer stage and with an auxiliary heater for uniform heating of the back of a wafer. The control of the wafer surface temperature may be provided by an infrared temperature sensor. The sensor may be mounted on a tilt module, permitting infrared radiation emitted from any point between the center and edge of the wafer to be measured. A feedback loop between the sensor and the rotation speed of the wafer stage and the power supplied to the laser may provide real time control of the surface temperature at any location on the wafer.
Alternatively, a process chamber may be equipped with a low energy plasma source. As an exemplary example we consider plasma chamber 120 equipped with vacuum pumps capable of providing a UHV base pressure in the range of 5×10−9-5×10−10 mbar or even 5×10−10-5×10−11 mbar (see also more detailed embodiment 500 of
Part 101 of the production system 100 for low-temperature covalent wafer bonding comprises further at least one UHV bonding chamber 124 with a base pressure in the range of 5×10−9-5×10−10 mbar. Preferably, the entire bonding chamber is temperature controlled within about 0.5°-1° C., or preferably within 0.1°-0.5° C., or even more preferably within 0.05°-0.1° C. Bonding chamber 124 may optionally be equipped with a wafer alignment system which permits the wafer pair to be mutually aligned with a precision of, for example, 50-200 nm prior to bonding. Bonding chamber 124 may be vibrationally decoupled by a bellows from wafer handler 104 to facilitate accurate wafer alignment. The wafer alignment system may, for example, comprise an optical vision control system based on confocal interferometric sensors, and a precision translation and rotation mechanical stage driven for example by stepper motors or piezo motors for translational and rotational fine positioning.
Embodiment 400 of a bonding chamber equipped with an ultra-precise wafer alignment system which is easily scalable to the bonding of 300 mm wafers will be introduced further below. Optionally, the bonding chucks holding the wafers may be heatable to a temperature of about 100°-300° C. Wafer bonding is, however, preferably carried out at room temperature at bonding pressures ranging between about 0 and 200 kN. Bonded wafers may instead optionally be annealed in UHV annealing chamber 128, which may offer batch annealing at temperatures in the range of 100°-400° C. Alternatively, annealing chamber 128 may be equipped for single wafer annealing up to a maximum temperature of about 900° C. Single wafer annealing may be used for example for the hydrogen desorption from semiconductor wafers which do not present any thermal budget problem, such as passivated Si or Ge wafers for which complete thermal H-desorption requires temperatures of at most 600° C. and 400° C., respectively.
Part 101 of the production system 100 for low-temperature covalent wafer bonding may further comprise wafer alignment UHV chamber 132 for wafer pre-alignment with a base pressure in the range of 5×10−9-5×10−10 mbar or even 5×10−10-5×10−11 mbar. Therein wafers may be pre-aligned rotationally to within a precision of about 0.1-0.5°, and translationally to within about 50-200 μm. Unless small features on the bonding partners need to be aligned, this pre-alignment may be sufficiently accurate for most applications of covalent bonding. Optionally, the pre-alignment of wafers may be carried out in handler 104 instead of a separate UHV chamber 132.
Furthermore, part 101 of the production system 100 for low-temperature covalent wafer bonding is equipped with UHV flipping chamber 136 pumped to a base pressure in the range of 5×10−9-5×10−10 mbar or even 5×10−10-5×10−11 mbar. Wafer flipping in chamber 136 may be required to bring the wafer surfaces to be bonded face-to-face in bonding chamber 124.
Finally, part 101 of the production system 100 for low-temperature covalent semiconductor wafer bonding may optionally comprise UHV chamber 138 with a base pressure in the range of about 5×10−9 to 5×10−10 mbar or even 5×10−10 to 5×10−11 mbar which may be equipped with means for thin film deposition for example of hydrogen passivated surfaces at substrate temperatures between room temperature and about 800° C. For temperature sensitive substrates, such as processed CMOS wafers, the slow deposition of very thin epitaxial semiconductor films a few monolayers in thickness at substrate temperatures between room temperature and about 300° C. may be an alternative way of preparing smooth, hydrogen-free crystalline surfaces suitable for covalent wafer bonding, provided that the chemical bond between the film material and hydrogen is weaker than the Si—H bond. Chamber 138 may, for example, be equipped with an optionally rotatable substrate holder in addition to a substrate heater and gas lines and mass flow controllers along with a low energy plasma source providing ion energies in the range of about 10-20 eV or even 5-10 eV, suitable for plasma assisted chemical vapour deposition for the epitaxial growth for example of 1-4 monolayers of Ge onto hydrogen terminated Si surfaces at very low temperatures, for example, between 150° and 300° C. and very low rates of, for example, 5-20 monolayers (ML) per minute or even 0.1 to 5 ML per minute. Alternatively, chamber 138 may be equipped with evaporators, such as electron beam evaporators or effusion cells, for example for the epitaxial deposition of a thin film of Ge or other semiconductor at similarly low rates. Slow epitaxial growth in UHV between room temperature and about 150°-300° C. may in fact be advantageous because it permits faster wafer transfer because there is no need for pumping down to UHV in contrast to a gas phase based technique. Furthermore, deposition rates can easily be controlled with great accuracy as they are independent of the substrate temperature, permitting accurate tailoring of layer thicknesses in the monolayer regime. Low deposition rates are desirable (or even necessary) in order to allow hydrogen to segregate from the passivated Si substrate surface to the surface of the growing Ge film (see, for example, T. Fujino et al., in Jpn. J. Appl. Phys. 40, L1173 (2001), the entire disclosure of which is hereby incorporated by reference). When the thickness of Ge films is kept below 4 ML, only a two-dimensional coherently strained (i.e. a layer the lattice parameter of which parallel to the interface is equal to the Si lattice parameter) wetting layer is formed and the nucleation of islands by means of the Stranski-Krastanow mechanism is suppressed (see, for example, M. Tomitori et al., in Appl. Surf. Sci. 76/77, 322 (1994), the entire disclosure of which is hereby incorporated by reference). Since hydrogen desorbs from Ge surfaces at about 300° C., a hydrogen-free Ge surface can be obtained at CMOS compatible temperatures in UITV (see, for example, D. Dick et al., in J. Phys. Chem. C 118, 482 (2014), the entire disclosure of which is hereby incorporated by reference). Alternatively, a short exposure to a low energy plasma or to laser irradiation near room temperature in plasma chamber 120 may be sufficient to provide a hydrogen-free, crystalline Ge surface. The invention therefore permits, for example, two Si wafers to be covalently bonded without the need of any surface bombardment by energetic particles by forming a Ge—Ge bond between two very thin Ge films epitaxially grown on the silicon wafers, for example, in UHV. Because the resulting Ge interfacial layer has a thickness of at most about one nanometre, corresponding to about 8 ML of Ge, or even substantially less, electrons can easily tunnel through. An ultrathin, coherently strained epitaxial Ge interlayer therefore does not contribute any significant resistance to the charge carrier transport across the bonding interface. The bonding of two Ge-terminated Si wafers instead of direct Si-to-Si bonding has the further advantage of a lower interfacial defect density because the higher mobility of Ge atoms is expected to lead to atomic reordering at the bonding interface at lower temperatures compared to Si interfaces. Hence the regular dislocation network due to wafer twist and tilt formed for Si interfaces only at annealing temperatures above about 800° C. (see for example T. Akatsu et al. in J. Mater. Sci. 39, 3031 (2004) and A. Reznicek et al. in MRS Symp. Proc. 681E, I4.4.1 (2001), the entire disclosures of which are hereby incorporated by reference) is expected to be present at Ge interfaces already in the as-bonded state or after annealing at temperatures as low as about 300° C. (see for example S. Ke et al. in J. Phys. D: Appl. Phys. 51, 265306 (2018), the entire disclosure of which is hereby incorporated by reference).That does not mean of course that the dislocation network at the bonding interface does not affect the electrical transport, but by keeping wafer twist and tilt small the dislocation density can be minimized.
The use of an epitaxial Ge interlayer is not limited to Si—Si bonding, but can easily be applied to the bonding of other materials with similar beneficial effects. One example is GaAs to Si bonding, which furthermore has the advantage of lattice matching between Ge and GaAs, as a result of which a Ge epitaxial layer on GaAs is defect free irrespective of its thickness. As an alternative to the slow epitaxial growth of an ultrathin Ge layer, another, preferably lattice-matched semiconductor layer may be epitaxially grown in chamber 138, fulfilling for example the same task of exchanging hydrogen-semiconductor bonds with semiconductor-semiconductor bonds. In an aspect of the embodiment UHV part 102 of the production system for wafer bonding may optionally be equipped with one or several chambers containing surface analysis tools for in-situ wafer inspection prior to wafer bonding. These tools may for example comprise an atomic force microscope (AFM) for surface roughness measurements, and a spectrometer for X-ray photoelectron spectroscopy (XPS) or Auger electron spectroscopy (AES) tool for chemical surface analysis.
The second part 102 of the production system 100 for low-temperature covalent wafer bonding comprises a wafer handling chamber 144 which may be of a simpler design compared to wafer handler 104 with robot 148, for example, for linear wafer transfer. Except for buffer chamber 140 which is attached to central handler 104 and except for handling chamber 144 the modules of part 102 are designed for processing in a dry inert gas atmosphere essentially at atmospheric pressure. The inert gases may, for example, comprise high purity oxygen-free and water-free nitrogen or argon. Part 102 is equipped with load-lock 160 for the introduction of wafer cassettes carrying the wafers to be either wet chemically or vapour cleaned. After cassette loading load-lock 160 may be evacuated to a pressure of about 10−5 to 10−6 mbar before being filled with high purity N2 or Ar at or near atmospheric pressure. Wet chemistry may be performed in at least one of a series of wet chemical processing modules or chambers 1561-156n, preferably made from stainless steel or PTFE (polytetrafluoroethylene), depending on the chemicals used inside. Each module from 1561-156n contains at least one tool from a list of tools, for example module 1561 solvent baths for degreasing, module 1562 acid baths for wafer dipping for example for a CAROS clean, module 1563 and 1564 baths for the SC1 and SC2 RCA wafer cleaning process, module 1565 for wet chemical oxide removal by an HF-dip, and for example chamber 1566 for an alternative oxide removal step by HF vapour, and chamber 1567 for deionized water rinsing and spin drying. Wet chemical processing in chambers 1561-156n is again performed in a high purity N2 or Ar atmosphere. Preferably, acid baths, deionized water rinse and inert gas lines are all equipped with particle filters, ensuring particle-free processing of all wafer surfaces. The natural oxide on Si wafers may be etched for example in module 1565 by a dilute, aqueous 2-5% HF solution for about 15-60 seconds and subsequently spin-rinsed in module 1567 by 18 MΩ deionized water upon which a H-passivated. Si surface is formed. For other semiconductor surfaces different etchants may be more appropriate, such as, for example, a 1:1 or more dilute solution of HCl:H2O for GaAs. Alternatively, at least one of processing chambers, for example 1566 may be equipped for wafer cleaning by etching gases or vapours, for example, HF vaporized from a HF/water solution or anhydrous HF gas (see, for example, P. A. M. van der Heide et al. in J. Vac. Sci. Technol. A 7, 1719 (1989), the entire disclosure of which is hereby incorporated by reference). The atmospheric pressure modules 1561-156n are separated from handling chamber 144 by special corrosion resistant gate valves 164, optionally in addition to vacuum gate valve 152. Enclosing processing chambers 1561-156n by corrosion resistant valves 164 may permit easy and safe removal for servicing of all parts operated at or near atmospheric pressure. Wafer transfer from load-lock 160 to processing modules 1561-156n and further to buffer chamber 140 is carried out by robot 148. Handling chamber 144 is optionally heatable to 100°-200° C. and preferably equipped with a fast pump for evacuation to a pressure of about 10−4 to 10−6 mbar. Buffer chamber 140 may also be equipped with a heating stage permitting wafer heating to about 100°-200° C., for example, by heating lamps. This may be advantageous for evacuating the chamber to high vacuum of a pressure of about 10−7 to 10−8 mbar, for example, by a combination of oil-free pre-vacuum and turbomolecular pumps. Wafer transfer from atmospheric pressure chamber 156n to UHV wafer handler 104 is therefore realized by a series of steps characterized by increasing vacuum quality.
The production system for semiconductor wafer bonding of the invention has a modular design, facilitating maintenance operations, as for example wet chemical chambers 1561-156n and load-lock 160 can safely be removed from vacuum system 101 for servicing. Similar ease of maintenance applies to vacuum chambers 116, 120, 120′, 124, 128, 132, 136, 140, 144, all of which can be mounted and remounted with the help of specially designed assembly/disassembly tooling without the need of breaking the vacuum in handler 104.
The production system for semiconductor wafer bonding of the invention may be operated fully automatically under computer control. Optionally, control computers offer remote access, for example, through the Internet or a remote desktop.
Referring now to
In an aspect of the embodiment chambers 220, 220′ may be present as two separate chambers attached to central handler 204, one for plasma processing and the other for laser processing, permitting more flexibility for example for the removal of the hydrogen passivation from different semiconductor surfaces. Production system 200 for low-temperature covalent wafer bonding comprises further at least one UHV bonding chamber 224 equipped with a wafer alignment system which permits the wafer pair to be mutually aligned with a precision of, for example, 50-200 nm prior to bonding. Preferably, entire bonding chamber 224 is temperature controlled within about 0.5°-1° C., or preferably within 0.1°-0.5° C., or even more preferably within 0.05°-0.1° C. Bonding chamber 224 may furthermore be vibrationally decoupled by a bellows from wafer handler 204 to facilitate accurate wafer alignment. Embodiment 400 of a wafer alignment system which is easily scalable to the bonding of 300 mm wafers will be introduced further below. Part 201 of the production system 200 for low-temperature covalent wafer bonding may further comprise wafer alignment UHV chamber 232 for wafer pre-alignment. Therein wafers may be pre-aligned rotationally to within a precision of about 0.1-0.5°, and translationally to within about 50-200 μm. Unless small features on the bonding partners need to be aligned, this pre-alignment may be sufficiently accurate for most applications of covalent bonding. Optionally, the pre-alignment of wafers may be carried out in handler 204 instead of a separate UHV chamber 232. Apart from a UHV wafer flipping chamber 236 and a thin film deposition chamber 238, equipped with substrate heater and tools for plasma assisted CVD or for thin film deposition in UHV similar to chamber 138, UHV vacuum system 201 may optionally comprise additional chambers, for example an annealing chamber 228 for post-bonding annealing or for pre-bonding single wafer annealing up to a maximum temperature of about 900° C. Single wafer annealing may be used for example for the hydrogen desorption from semiconductor wafers which do not present any thermal budget problem, such as passivated Si or Ge wafers for which complete thermal H-desorption requires temperatures of at most 600° C. and 400° C., respectively.
Optionally, UHV part 201 of the production system for low-temperature covalent semiconductor wafer bonding may furthermore be equipped also with a wafer storage chamber with a base pressure preferably in the range of 1×10−11 to 5×10−11 mbar, permitting hydrogen passivated wafers transferred from essentially atmospheric pressure part 202 to be stored for extended periods of time (e.g. for example one day). Such a chamber may act as a buffer to facilitate the synchronisation of processes requiring different processing times in order to increase the throughput of the wafer bonding system 200 as a whole.
Part 202 of the production system for wafer bonding contains a series of processing modules arranged around central handler 254 equipped with robot 258. Wafers are introduced through load-lock 260 connected via gate valve 262 with central handler 254 and transferred into a series of modules 2561 . . . 256n designed for wet chemical and/or gas phase cleaning all of which are connected to central handler 254 through corrosion resistant gate valves 264. Chamber 2561 may be a chamber equipped with solvent baths for degreasing of wafers, chamber 2562 for example for a CAROS clean, chamber 2563 and 2564 for the SC1 and SC2 steps of well-known RCA cleaning, chamber 2565 for wet chemical oxide removal by an HF-dip, and for example chamber 2566 for an alternative oxide removal step by HF vapour, and chamber 2567 for deionized water rinsing and spin drying. Optional chamber 270 may for example serve as a storage chamber for wafers from a cassette introduced through load-lock 260. Chamber 270, connected via gate valve 262 to central handler 254, can optionally be evacuated and/or filled with a inert gas atmosphere. Atmospheric pressure part 202 is separated from UHV part 201 by a buffer chamber 250 or preferably two buffer chambers 240, 250 successively pumped from atmospheric pressure to UHV in order to avoid cross-contamination between atmospheric pressure and UHV part.
Referring now to
In an aspect of the embodiment chambers 320, 320′ may be present as two separate chambers attached to central handler 304, one for plasma processing and the other for laser processing, permitting more flexibility for example for the removal of the hydrogen passivation from different semiconductor surfaces. Production system 300 for low-temperature covalent wafer bonding comprises further at least one UHV bonding chamber 324 equipped with a wafer alignment system which permits the wafer pair to be mutually aligned with a precision of, for example, 50-200 nm prior to bonding. Preferably, entire bonding chamber 324 is temperature controlled within about 0.5°-1° C., or preferably within 0.1°-0.5° C., or even more preferably within 0.05°-0.1° C. Bonding chamber 324 may furthermore be vibrationally decoupled by a bellows from wafer handler 304 to facilitate accurate wafer alignment. Embodiment 400 of a wafer alignment system which is easily scalable to the bonding of 300 mm wafers will be introduced below. Part 301 of the production system 300 for low-temperature covalent wafer bonding may further comprise wafer alignment UHV chamber 332 for wafer pre-alignment. Therein wafers may be pre-aligned rotationally to within a precision of about 0.1-1°, and translationally to within about 50-200 μm. Unless small features on the bonding partners need to be aligned, this pre-alignment may be sufficiently accurate for most applications of covalent bonding. Optionally, the pre-alignment of wafers may be carried out in handler 304 instead of a separate UHV chamber 332. Apart from UHV a wafer flipping chamber 336 and a thin film deposition chamber 338, equipped with substrate heater and tools for plasma assisted CVD or for thin film deposition in UHV similar to chamber 138, UHV vacuum system 301 may optionally comprise additional chambers, for example an annealing chamber 328 for post-bonding annealing or for pre-bonding single wafer annealing up to a maximum temperature of about 900° C. Single wafer annealing may be used for example for the hydrogen desorption from semiconductor wafers which do not present any thermal budget problem, such as passivated Si or Ge wafers for which complete thermal H-desorption requires temperatures of at most 600° C. and 400° C., respectively.
Optionally, UHV part 301 of the production system for low-temperature covalent semiconductor wafer bonding may furthermore be equipped also with a wafer storage chamber with a base pressure preferably in the range of 1×10−11 to 5×10−11 mbar, permitting hydrogen passivated wafers transferred by means of UHV suitcase 372 from essentially atmospheric pressure part 302 to be stored for extended periods of time (e.g. for example one day). Such a chamber may act as a buffer to facilitate the synchronisation of processes requiring different processing times in order to increase the throughput of the wafer bonding system 300 as a whole.
Part 302 of the production system for wafer bonding contains a series of processing modules arranged around central handler 354 equipped with robot 358. Wafers are introduced through load-lock 360 and transferred into a series of modules 3561 . . . 356n designed for wet chemical and/or gas phase cleaning and connected via corrosion resistant gate valves 364 to central handler 254 Chamber 3561 may be a chamber equipped with solvent baths for degreasing of wafers, chamber 2562 for example for a CAROS clean, chambers 3563 and 3564 for the SC1 and SC2 steps of well-known RCA cleaning, chamber 3565 for wet chemical oxide removal by an HF-dip, and for example chamber 3566 for an alternative oxide removal step by HF vapour, and chamber 2567 for deionized water rinsing and spin drying. Optional chamber 370 may for example serve as a storage chamber for wafers from a cassette introduced through load-lock 360. Optionally, after servicing, part 302 can be coupled to part 301 for example through buffer chambers 340, 350 connected through UHV gate valves 312, 362, after which the bonding system of embodiment 300 may become identical with that of embodiment 200.
Referring now to
After pre-alignment of the wafers in pre-alignment tool 132, 232, 332, and introduction into bonding chamber 404 the wafers are picked and placed by pins 426 onto electrostatic chucks or chuck modules 430, 440 which may optionally comprise integrated active heating and/or cooling. After activating the electrostatic chucks, keeping the wafers firmly held, pins 426 are retracted before the alignment procedure begins.
Bonding chamber 404 is equipped with an actuator in the form of a small electric piston 416 aligned with the central axis of the wafer alignment system. One set of at least three actuators in the form of pistons 420 is arranged symmetrically at equal distance from central piston 416 (see also top view 403 of chamber 404 in
Similar to the vertical wafer alignment, the rotational and translational wafer alignment is again controlled by confocal interferometric sensors 443. These are mounted on a set of at least two rotatable and translatable actuators 444 by means of which they can be moved into measurement positions between the wafers as in
All that is needed for precise wafer alignment in the sub-100 nm range are some alignment features 470, 472, 490, 492 at the periphery of both wafers providing a contrast for the reflected focused beams (
During all rotational and translational movements, the wafers are permanently kept parallel by actuating pistons 420. After completing the alignment, sensors 443 are rotated to home position. The final wafer approach happens during permanent compensation of any deviation from wafer parallelism until central piston 416 can be actuated to start the bonding wave after initial contact of the wafers. Thereafter, in order to apply a constant pressure homogeneously distributed across the wafers, actuators 420 operate under torque control. Optionally, additional optical cameras may facilitate course wafer alignment. Moreover, one or several laser interferometers accessing chuck modules 430, 440 through windows in chamber 406 may provide absolute alignment reference points correcting for any undesired internal movements for example as a result of thermal non-uniformities. Any chamber deformation during the application of the bonding forces exerted by actuators 420 may be monitored by pressure gauges distributed over chamber 406.
It is an advantage of the invention that wafer alignment does not require infrared transparency. By contrast, any bondable wafer whatever its nature can be used in the described approach.
Referring now to
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Upon approaching the final position, super precise parallelism on the order of 100 nm is established through a second close loop control with outer sensors 434, designed for larger working distance so that they can be focused on bottom chuck module 440. The final position distance between the upper and lower chuck module 430, 440 should be in a range of 5 to 20 mm, most preferably about 10 mm.
In step 803 confocal sensors 443, firmly connected to fine resolution rotatable and translatable actuator 444 are moved in between the two wafers to a pre-set sensing area controlled by the position controller unit.
In step 804 actuators 444 start scanning in sensor coordinate systems 482, 486 in x-y directions in order to find geometrical alignment features 470, 472 present on upper wafer 441. The shape of the alignment features 470, 472 on upper wafer 441 are determined by correlating the spatial movement of sensors 443 in coordinate systems 482, 486 with the signal detected from upwards focused beam 460. Thereby it becomes possible to reconstruct the surface topography or also the material contrast of the alignment features because the sensor can discriminate between different optical properties of materials, and for example the depth of oxide layers or trenches. Once the scan has been carried out by at least two sensors 443 located on opposite extremes of the upper wafer 441, stages 444 move upwards focused beams 460 of sensors 443 from random positions on the wafer, corresponding to initial coordinates 483, 487 in sensor coordinate systems 482, 486, exactly into centers 471, 473 of the geometrical alignment features corresponding to scanner coordinates 484, 488, whereupon the reliability of the previous scans is checked again. After the precise positioning of upwards focused beams 460 into the centers 471, 473 of alignment marks 470, 472 of upper wafer 441, actuators 444 remain stationary during all subsequent alignment sequences. In step 805, the high accuracy alignment of bottom chuck 440 is carried out to which bottom wafer 445 is firmly attached. The first alignment controlled by downwards focused beam 464 of sensor 443 is performed by actuating rotation 450 of bottom chuck module 440 to orient alignment features 490, 492 of bottom wafer 445 parallel to alignment features 470, 472 of upper wafer 441. The rotational alignment of the alignment features on top and bottom wafer is thereby monitored by rotational scanning in clockwise and anti-clockwise directions, permitting deeper trenches 474 of alignment features 490, 492 to be recognized by downward focused beams 464. Having generated an image of the trench profile on bottom wafer 445 permits parallel alignment of the alignment features on upper and bottom wafers for example along the x-axis of coordinate system 498 by once more activating rotation 450.
After the parallel alignment of the features on two extremes of the bottom wafer with the corresponding ones on the upper wafer, the rotation of stage 442 around axis 450 is stopped. In step 806, the centering of downwards focused beams 464 starts by scanning actuators 446, 448 of stage 442 in the x-y directions of stage coordinate system 498 in order to find now precisely the centers 491, 493 of the geometrical alignment features present on bottom wafer 445. Once the downwards focused beams 464 of at least two sensors 443 on opposite extremes of bottom wafer 445 have been centered, the upper and bottom wafers are aligned with very high accuracy on the order of 100 nm or even less. The x-y motorized stages 446, 448 hold then the final position in place, and no other correction needs to be performed.
In step 807, arms 443 are retracted to their home position shown in
It should be appreciated that the particular implementations shown and herein described are representative of the invention and its best mode and are not intended to limit the scope of the present invention in any way.
Many applications of the present invention may be formulated. As will be appreciated by skilled artisans, the present invention may be embodied as a system, a device, or a method.
The invention may be summarized by the feature sets defined by the appended claims, incorporated in this specification by reference thereto.
The present invention is described herein with reference to block diagrams, devices, components, and modules, according to various aspects of the invention. Moreover, the system contemplates the use, sale and/or distribution of any goods, services or information having similar functionality described herein.
The specification and figures should be considered in an illustrative manner, rather than a restrictive one and all modifications described herein are intended to be included within the scope of the invention claimed. Accordingly, the scope of the invention should be determined by the appended claims (as they currently exist or as later amended or added, and their legal equivalents) rather than by merely the examples described above. Steps recited in any method or process claims, unless otherwise expressly stated, may be executed in any order and are not limited to the specific order presented in any claim. Further, the elements and/or components recited in apparatus claims may be assembled or otherwise functionally configured in a variety of permutations to produce substantially the same result as the present invention. Consequently, the invention should not be interpreted as being limited to the specific configuration recited in the claims.
Benefits, other advantages and solutions mentioned herein are not to be construed as critical, required or essential features or components of any or all the claims.
As used herein, the terms “comprises”, “comprising”, or variations thereof, are intended to refer to a non-exclusive listing of elements, such that any apparatus, process, method, article, or composition of the invention that comprises a list of elements, that does not include only those elements recited, but may also include other elements such as those described in the instant specification. Unless otherwise explicitly stated, the use of the term “consisting” or “consisting of” or “consisting essentially of” is not intended to limit the scope of the invention to the enumerated elements named thereafter, unless otherwise indicated. Other combinations and/or modifications of the above-described elements, materials or structures used in the practice of the present invention may be varied or adapted by the skilled artisan to other designs without departing from the general principles of the invention.
The patents and articles mentioned above are hereby incorporated by reference herein, unless otherwise noted, to the extent that the same are not inconsistent with this disclosure.
Other characteristics and modes of execution of the invention are described in the appended claims.
Further, the invention should be considered as comprising all possible combinations of every feature described in the instant specification, appended claims, and/or drawing figures which may be considered new, inventive and industrially applicable.
Copyright may be owned by the Applicant(s) or their assignee and, with respect to express Licensees to third parties of the rights defined in one or more claims herein, no implied license is granted herein to use the invention as defined in the remaining claims. Further, vis-à-vis the public or third parties, no express or implied license is granted to prepare derivative works based on this patent specification, inclusive of the appendix hereto and any computer program comprised therein.
Additional features and functionality of the invention are described in the claims appended hereto. Such claims are hereby incorporated in their entirety by reference thereto in this specification and should be considered as part of the application as filed.
Multiple variations and modifications are possible in the embodiments of the invention described here. Although certain illustrative embodiments of the invention have been shown and described here, a wide range of changes, modifications, and substitutions is contemplated in the foregoing disclosure. While the above description contains many specific details, these should not be construed as limitations on the scope of the invention, but rather exemplify one or another preferred embodiment thereof. In some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the foregoing description be construed broadly and understood as being illustrative only, the spirit and scope of the invention being limited only by the claims which ultimately issue in this application.
The following US patent documents, foreign patent documents, and additional publications are incorporated herein by reference thereto, as if fully set forth herein, and relied upon:
US patent documents
This application claims priority to and benefit of U.S. Provisional Application No. 62/688,420 filed 22 Jun. 2019, which is incorporated herein by reference and relied upon.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2019/055293 | 6/24/2019 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62688420 | Jun 2018 | US |
