The present disclosure relates generally to semiconductors, and more particularly, to crack-free III-V epitaxy on germanium-on-insulator (GOI) substrates and method for forming the same.
Integration of III-V devices with germanium and silicon CMOS devices on the same substrate is based upon the use of germanium-on-insulator (GOI) wafers to serve as a template for subsequent III-V epi growth. GOI wafers include, for example, germanium on silicon dioxide on a silicon handle wafer.
In an effort to reduce the defectivity level in a gallium arsenide (GaAs) on germanium (Ge) bulk substrate process, indium (In) was added to the process to adjust the lattice constant thereof for a more perfect match. However, when this same one-and-a-half percent (1.5%) InGaAs epi was used for GOI substrates, it was quickly discovered that it does not work. There were two failure modes, both observed in optical microscope inspections. The first failure mode comprised a cross hatching of the epi, indicating serious defectivity. The second failure mode comprised actual delamination of the films at the germanium to silicon dioxide interface at the edges of the GOI wafer. In addition, subsequent device processing leads to delamination throughout the GOI wafer.
The delamination problem discussed above is believed to be caused by differences between the coefficient of thermal expansion (CTE) of silicon (Si), germanium (Ge), and gallium arsenide (GaAs). Whereas Ge and GaAs CTEs are closely matched, the CTE of Si is much smaller and thus the thick silicon handle wafer constrains the Ge expansion during heating for epi growth. The lattice parameter for 1.5% InGaAs does not match the constrained Ge and thus as the film grows, it exceeds the critical thickness and relaxes through defect formation. Then, upon cool down, the entire III-V epi and the Ge upon which it resides become tensile. Furthermore, if the thickness is great enough, then the strain energy exceeds the adhesion of the germanium to silicon dioxide interface. One cannot retune the InGaAs system to match the constrained Ge at growth temperature, and even if one could do so, the CTE difference remains and the system will become tensile and likely fail upon return to room temperature.
The growth of GaAs epi on bulk Ge is a known process, used for solar cells for space applications. In addition, the method of tuning the lattice constant of GaAs by adding In to better match bulk Ge is known. However, such a method does not face a CTE mismatch problem because the known method involves growing GaAs on a free standing Ge substrate.
The CTE mismatch between GaAs and silicon has been identified as a problem for direct growth of GaAs on silicon. However, because of the extreme lattice constant differences, it is not clear how to tune the lattice constant to grow defect free epi nor is there a single crystal to amorphous interface where adhesion is a concern.
AlGaInP and specifically Ga0.52In0.48P have been grown on GaAs and Ge substrates with an intervening buffer layer. These were lattice matched to GaAs and were chosen for their wide direct energy gaps in the III-V alloys for visible light emitters. However, they were not deposited directly on Ge, not deposited on GOI wafers, and not lattice matched to silicon constrained Ge at the growth temperature.
Turning now to
On the other hand, it is possible for an InGaAs epitaxial layer to be grown on a bulk Ge substrate with an absence of misfit dislocations. However, if the InGaAs epitaxial layer were grown on the Ge layer 14 of the GOI substrate 10, the resulting InGaAs epi layer would also include misfit dislocations due to lattice parameter mismatches between the epitaxial layer 22 and the Ge layer 14.
Accordingly, it would be desirable to provide an improved epitaxial method for overcoming the problems in the art as discussed above.
The embodiments of the present disclosure are illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
The embodiments of the present disclosure include selecting a III-V materials system for epitaxial growth on GOI that meets two criteria: (1) the CTE must be closer to Si; and (2) the material composition can be adjusted to match the silicon constrained Ge lattice constant at, or specifically slightly removed from, the growth temperature. In this regard, III-V alloys that have CTE's closer to Si and that can be lattice matched to constrained Ge include, for example, at least InGaP, InAlP, and GaAsP which are used in the industry. Other suitable III-V alloys may also exist. It is noted that at the low phosphorus (P) composition needed to lattice match constrained Ge, GaAsP will have a CTE close to GaAs and thus is not a good candidate. On the other hand, InGaP and InAlP have (with their quartemary AlGaInP) CTE's around 5E-6/K. Taking InGaP as an example, a lattice match at a 700 C growth temperature occurs for an indium composition of forty-seven percent (47%) and, with its estimated CTE, will have a tensile room temperature mismatch of about IE-3, about one-third (⅓) that of GaAs. Since the strain energy goes as the square of the mismatch, the InGaP film on GOI has approximately one-ninth ( 1/9) the tensile strain energy of the corresponding GaAs film. Thus, a properly chosen InGaP film of device thickness is expected to be stable on GOI and have low defectivity.
The method according to the embodiments of the present disclosure resolves several problems in a new way as follows. Epitaxial growth on GOI substrates with one-and-a-half percent (1.5%) InGaAs material showed high defectivity and began to show microcracks or delamination on GOI substrates at thicknesses approaching three (3) microns. It is believed that the new materials system according to the embodiments of the present disclosure, when properly tuned, will allow equivalent or greater epi thicknesses without delamination and will serve either as the buffer layer or as part of the active device layer for HBT's, LED's, lasers, detectors, and the like.
Various process details, for example, nucleation sequence, growth conditions, etc., are selected in a manner so as to yield low defectivity, thick III-V epi layers on GOI substrates. In one embodiment, the process is chosen so as to demonstrate certain defectivity specifications (<1E5/cm2). Accordingly, the embodiments of the present disclosure provide a method for use to fully integrate III-V devices and silicon (or Ge) FETs into a integrated circuit product.
According to one embodiment of the present disclosure, a method for growing low defectivity thick III-V epi on Germanium on Insulator (GOI) substrates that will survive subsequent processing requires the selection of a material according to two criteria: (1) the CTE of the material must be as close as possible to Si, and (2) the material composition can be adjusted to match the silicon constrained Ge lattice constant at, or specifically slightly removed from, the growth temperature. Furthermore, the method according to the present embodiments enable growing of thick III-V epi on GOI substrates with low defectivity and stress levels sufficiently low to prevent delamination.
Three well known ternary III-V alloys that have CTE's closer to Si and that can be lattice matched to constrained Ge include InGaP, InAlP, and GaAsP. In one embodiment, InGaP is preferred and its composition can be varied to lattice match (i) bulk Ge, (ii) SiGe with a high Ge content, or (iii) constrained Ge on a GOI substrate. A lattice match at a 700 C growth temperature occurs for an indium composition of about forty-seven percent (47%) and, with its estimated CTE, will have a tensile room temperature mismatch of about 1E-3, about one-third (⅓) that of GaAs. A thick InGaP buffer layer can be grown either directly on the GOI Ge or upon a thin GaAs nucleation layer. In the later instance, the thin GaAs nucleation layer has a thickness below a critical thickness for the formation of dislocations.
In demonstrating a workability of the method according to the present embodiments, it is first noted that a calculated stress of InGaP and GaAs films is on the order of 146 MPa for InGaP and 257 MPa for GaAs. Wafer bow measurements of the stress of the InGaP films on GOI for several samples showed stress on the order of 92 MPa for a first sample, on the order of 130 MPa for a second sample, and on the order of 170 MPa for a third sample. In addition, an HBT structure was built in which the structure showed no presence of delamination.
Accordingly, the method of the present disclosure can be used to provide an optimized InGaP composition (i.e., depending on growth temperature), in addition to using a very thin optional GaAs layer as a nucleation layer, that can serve as a base material upon which to build III-V HBT, FET, or optoelectronic devices. In addition, the III-V epi layer on GOI substrate according to the embodiments of the present disclosure is of thickness sufficient for a corresponding III-V HBT, FET, or optoelectronic device(s).
The various embodiments of the present disclosure provide a broad materials platform that enables heterogeneous integration of III-V with silicon. The embodiments relate to III-V technology, and also to less than 90 nm silicon MOS integrated circuit devices and structures.
The embodiments of the present disclosure advantageously provide a materials platform to enable products which benefit from the monolithic integration of III-V devices with silicon. Such products may include one or more of the following:
According to one embodiment, the method includes choosing a III-V material that has two important attributes. In a first attribute, the III-V material must lattice match to the compressively strained Ge film of a GOI substrate at growth temperature (i.e., between 600 C and 740 C). With this first attribute, the film grows with low mismatch and thereby enables the formation of thick layers (as required for many III-V devices). In a second attribute, the III-V material must have a CTE as close as possible to the silicon handle wafer rather than Ge. With this second attribute, when cooled down, the tensile stress is minimized so that the corresponding films do not delaminate.
In one embodiment, InGaP is used as the III-V material. The InGaP material composition can be tuned to adjust the lattice parameter. In addition, estimating the InGaP CTE from the binary InP and GaP values suggests that the strain energy will be reduced by nearly an order of magnitude.
According to one embodiment, a method of forming crack-free III-V epitaxy on a germanium-on-insulator (GOI) substrate comprises: measuring a lattice parameter of the bonded layer at a first temperature; calculating the lattice parameter of the bonded layer as a function of a coefficient of thermal expansion (CTE) of the handle substrate at an epitaxial growth temperature, the epitaxial growth temperature being different from the first temperature; selecting an epitaxial composition from a class of III-V material for epitaxial growth overlying the bonded layer, wherein the selected epitaxial composition is adjusted to have a lattice parameter that approximates the calculated lattice parameter of the bonded layer at the epitaxy growth temperature; and growing the epitaxial layer over the bonded layer with use of the adjusted epitaxial composition.
In another embodiment, the GOI substrate includes a thin bonded layer and a thick handle substrate, wherein the bonded layer is constrained by the handle substrate. For example, the bonded layer can include germanium (Ge) and the handle substrate can include silicon (Si). In addition, the GOI substrate includes a coefficient of thermal expansion (CTE) mismatched substrate, wherein the grown epitaxial layer is lattice matched to silicon (Si) constrained germanium (Ge) at the epitaxy growth temperature. For example, the epitaxy growth temperature may include a temperature on the order of 900 K. In addition, the adjusted epitaxial composition can comprise, for example, Ga0.53In0.47P. Furthermore, the grown epitaxial layer may comprise Ga0.53In0.47P having a lattice parameter that approximates the lattice parameter of the bonded Ge layer at an epitaxial growth temperature of 900 K. The epitaxial growth temperature can also include a temperature in a range from 400° C. to 750° C. Still further, the method may comprise providing a nucleation layer over the bonded layer prior to growing the functional epitaxial layers.
In another embodiment, a method of forming III-V epitaxy comprises providing a coefficient of thermal expansion (CTE) mismatched substrate including (i) a handle substrate having a first coefficient of thermal expansion, and (ii) a bonded layer over the handle substrate, the bonded layer having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion, the bonded layer further having a lattice parameter that is influenced by the handle substrate. A III-V epitaxial layer is grown over the bonded layer at an epitaxial growth temperature, wherein the epitaxial layer comprises a material composition adjusted for having a lattice parameter that approximates the lattice parameter of the bonded layer at the epitaxial growth temperature.
The epitaxial layer can comprise, for example, a material composition having been adjusted for lattice matching the bonded layer at the epitaxial growth temperature. The handle substrate can comprise, for example, at least one selected from the group consisting of silicon, glass, plastic, and sapphire. In addition, the bonded layer can comprise, for example, at least one selected from the group consisting of germanium and a compound semiconductor material. Alternatively, the bonded layer may comprise a first Group IV element compound, and the epitaxial layer may comprise a second Group III-V element compound. In one embodiment, the bonded layer comprises germanium and the epitaxial layer comprises indium gallium phosphide. In particular, the epitaxial layer can comprise Ga0.53In0.47P.
In addition, the CTE mismatched substrate can comprise, for example, a germanium-on-insulator (GOI) substrate. The bonded layer lattice parameter can be constrained by the handle substrate. Furthermore, the epitaxial layer can be characterized by a defectivity of less than 105 defects/cm2.
According to another embodiment, an apparatus comprises a substrate having a coefficient of thermal expansion (CTE) mismatch, wherein the substrate includes a handle substrate having a first coefficient of thermal expansion and a bonded layer over the handle substrate having a second coefficient of thermal expansion. The bonded layer further includes a lattice parameter that is influenced by the handle substrate. In addition, the apparatus includes an epitaxial layer over the bonded layer. The epitaxial layer comprises a material having a lattice parameter that approximates the lattice parameter of the bonded layer at an epitaxial growth temperature.
In one embodiment, the epitaxial growth temperature is a temperature in a range from 400° C. to 750° C. The handle layer comprises at least one material selected from the group consisting of silicon, glass, plastic, and sapphire. Alternatively, the bonded layer can comprise a first Group IV element compound. For example, the bonded layer may comprise one of germanium or a compound semiconductor. The epitaxial layer can comprise a second Group III-V element compound. In addition, the epitaxial layer can include a layer having a varying composition. In another embodiment, the bonded layer comprises germanium and the epitaxial layer comprises indium gallium phosphide.
In another embodiment, the handle substrate and the bonded layer are crystalline, however, the bonded layer has a lattice structure that is constrained by the handle substrate lattice structure as temperature is changed. In another embodiment, the epitaxial layer is a compound semiconductor. Furthermore, the epitaxial layer has a defect density of less than 105 defects/cm2 and there is not delamination or cracking of the epitaxy. In other words, the epitaxial layer is free of catastrophic defects. Catastrophic defects can include, for example, cracking or delamination of the bonded layer or the epitaxy layer from the handle substrate. Alternatively, the epitaxial layer exhibits a substantial absence of misfit dislocations.
In another embodiment, a method of growing an epitaxial layer over a multi-layer substrate includes providing a handle substrate with a first coefficient of thermal expansion and a second layer with a second coefficient of thermal expansion bonded to the handle substrate. The method further includes measuring a first lattice parameter of the second layer at a first temperature and calculating a second lattice parameter of the second layer at a second temperature. The second lattice parameter at the second temperature is a function of the first coefficient of thermal expansion and the first lattice parameter. Upon calculating the second lattice parameter of the second layer at the second temperature, the method includes adjusting a composition of epitaxial layer to have a lattice parameter that approximates the second lattice parameter and growing the epitaxial layer using the adjusted composition. Furthermore, the method includes selecting an epitaxial composition from a plurality of available epitaxial compositions which has a coefficient of thermal expansion closest to the first coefficient of thermal expansion. In another embodiment, the method includes providing the handle substrate and the second layer, wherein the second layer is physically coupled to the handle substrate via an insulating layer.
In yet another embodiment, the step of measuring a lattice parameter can comprise using x-ray diffraction. In addition, calculating the lattice parameter can include: (i) averaging the coefficient of thermal expansion from the first temperature to the second temperature, or (ii) integrating the coefficient of thermal expansion from the first temperature to the second temperature.
In other embodiments, other candidate III-V materials may be possible. Also, one may choose the lattice constant slightly mismatched so as to grow the III-V epi slightly compressive at growth temperature (but not so compressive that the film will relax for a given thickness) which will further reduce the tensile strain at room temperature.
The embodiments of the present disclosure solve problems and issues faced in the growing III-V epi on GOI, such as GaAs on GOI, which has not previously been known.
In the foregoing specification, the disclosure has been described with reference to various embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present embodiments as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present embodiments. For example, the present embodiments can apply to semiconductor device technologies where minimal defectivity is crucial to the device performance.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the term “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.