Claims
- 1. An interlace grid array package structure comprising:a lead frame having a central die paddle and a plurality of leads spaced around the die paddle, wherein the lead frame has a first side and a second side; a wafer chip attached to the die paddle on the first side of the lead frame, wherein the wafer chip is electrically connected to the lead frame; a package material for enclosing the wafer chip and the lead frame on the first side; and a interlace grid array tape attached to the second side of the lead frame, wherein the interlace grid array tape has a plurality of holes arranged alternately into a grid array, and the holes of the interlace grid array tape match in positions to the respective leads of the lead frame, so that the leads are partially exposed through the holes of the cross grid array tape.
- 2. The structure of claim 1, wherein the material for forming the lead frames includes copper.
- 3. The structure of claim 1, wherein the material for forming the lead frames includes alloy.
- 4. The structure of claim 1, wherein the wafer chip is connected electrically to the lead frame through a flip chip method.
- 5. The structure of claim 1, wherein the wafer chip is connected electrically to the lead frame through a wire bonding.
- 6. The structure of claim 1, wherein the packaging material includes resins.
- 7. The structure of claim 1, wherein the packaging material includes plastics.
- 8. The structure of claim 1, wherein the packaging material includes ceramics.
- 9. The structure of claim 1, wherein the material for forming the interlace grid array tape includes polyimide.
- 10. The structure of claim 1, wherein the material for forming the interlace grid array tape includes a polymer material.
- 11. The structure of claim 1, wherein the material for forming the interlace grid array tape includes a substance that has a low affinity for soldering compound.
- 12. The structure of claim 1, wherein the number of holes in the interlace grid array tape is the same as the number of leads in the lead frame.
- 13. The structure of claim 1, wherein the number of holes in the interlace grid array tape is different from the number of leads in the lead frame.
Priority Claims (1)
Number |
Date |
Country |
Kind |
87102396 A |
Feb 1998 |
TW |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 09/095,043 filed on Jun. 10, 1998 now U.S. Pat. No. 6,190,938.
US Referenced Citations (7)
Number |
Name |
Date |
Kind |
5569955 |
Chillara et al. |
Oct 1996 |
A |
5847455 |
Manteghi |
Dec 1998 |
A |
5864470 |
Shim et al. |
Jan 1999 |
A |
5894108 |
Mostafazadeh |
Apr 1999 |
A |
5976912 |
Fukutomi et al. |
Nov 1999 |
A |
6025650 |
Tsuji et al. |
Feb 2000 |
A |
6064111 |
Sota et al. |
May 2000 |
A |