Claims
- 1. A dynamic random access memory (DRAM) device comprising:
(a) a substrate of semiconductor material having a main outer surface; (b) a plurality of substantially parallel word lines located outwardly of said main outer surface of said substrate, each of said word lines having a word line width defined by first and second word line edges and being separated from adjacent word lines by a word line separation distance; (c) a plurality of substantially parallel bit lines located outwardly of said main outer surface of said substrate, each of said bit lines having a bit line width defined by first and second bit line edges and being separated from adjacent bit lines by a bit line separation distance, said bit lines being substantially perpendicular to said word lines; and (d) a plurality of memory cells each associated with an intersection of a given one of said first and second word line edges of a given one of said word lines and a given one of said first and second bit line edges of a given one of said bit lines, each of said memory cells in turn comprising:
(i) a pillar of semiconductor material extending outward from said main outer surface of said substrate and being electrically isolated from adjacent memory cells, said pillar having a pillar outer surface, said pillar including an active region of said semiconductor material substantially centered inward of said intersection, said pillar being formed with a hole region defined by a hole floor and at least one hole wall, said hole floor being located outwardly of said main outer surface of said substrate; (ii) a storage node offset from said active region of said pillar in a direction away from said given one of said word lines and said given one of said bit lines; (iii) a storage node plug extending from said storage node through said hole region in said pillar to contact said hole floor and form thereat a storage node contact and one of a drain and a source of a MOS transistor, said storage node plug being electrically isolated from said at least one hole wall; (iv) a bit line plug extending from said given one of said bit lines inwardly to contact said pillar outer surface and form thereat a bit line contact and another of a drain and a source of said MOS transistor; and (v) a word line plug extending from said given one of said word lines through said hole region in said pillar and terminating outwardly of said hole floor, said word line plug being electrically isolated from said semiconductor material of said pillar such that a portion of said word line plug adjacent to and electrically isolated from said semiconductor material of said pillar forms a gate of said MOS transistor with a corresponding portion of said semiconductor material of said pillar forming a channel region of said MOS transistor.
- 2. The device of claim 1, wherein said pillars of semiconductor material are isolated from adjacent pillars by trench isolation.
- 3. The device of claim 1, wherein said substrate comprises silicon and wherein said gate is isolated from said channel region by gate silicon dioxide.
- 4. The device of claim 1, wherein said word line width, said word line separation distance, said bit line width and said bit line separation distance are all substantially equal to a characteristic minimum feature size F such that a planform area of each of said memory cells is substantially 4F2.
- 5. The device of claim 1, wherein said direction in which said storage node is offset from said active region is substantially identical for all of said memory cells.
- 6. The device of claim 1, wherein said direction in which said storage node is offset from said active region is substantially identical for all memory cells associated with a given one of said bit lines and is opposite, in a direction substantially parallel to said bit lines, for all memory cells associated with an adjacent one of said bit lines.
- 7. The device of claim 1, wherein each of said storage node plug, said bit line plug and said word line plug have an outline when viewed in plan view, and wherein at least two of said storage node plug, said word line plug, and said bit line plug are not enclosed by any of said outlines of any other of said storage node plug, said bit line plug and said word line plug.
- 8. The device of claim 7, wherein all three of said storage node plug, said word line plug and said bit line plug are not enclosed by any of said outlines of any other of said storage node plug, said bit line plug and said word line plug.
- 9. The device of claim 8, wherein said storage node plug, said word line plug and said bit line plug are all substantially solid when viewed in plan.
- 10. The device of claim 1, wherein said storage node plug, said bit line plug and said word line plug form a substantially asymmetric structure when viewed in plan.
- 11. The device of claim 10, wherein said storage node plug, said bit line plug and said word line plug are all substantially solid when viewed in plan.
- 12. A method for manufacturing a dynamic random access memory (DRAM) device, said method comprising the steps of:
(a) providing a substrate of semiconductor material having a main outer surface; (b) forming a plurality of pillars of semiconductor material extending outward from said main outer surface of said substrate, each of said pillars having a pillar outer surface, said pillars being formed using a first mask, said pillars being electrically isolated from each other and including an active region of said semiconductor material; (c) forming a plurality of substantially parallel bit lines located outwardly of said main outer surface of said substrate, each of said bit lines having a bit line width defined by first and second bit line edges and being separated from adjacent bit lines by a bit line separation distance, said bit lines being formed using a second mask; (d) interconnecting said bit lines with said pillar outer surfaces via a plurality of bit line plugs so as to form, at intersections of said bit line plugs with said pillar outer surfaces, a plurality of bit line contacts and one of sources and drains of a plurality of MOS transistors; (e) forming at least one hole region defined by a hole floor and at least one hole wall in each of said plurality of pillars, said hole floors being located outwardly of said main outer surface of said substrate; (f) forming a plurality of substantially parallel word lines located outwardly of said main outer surface of said substrate, each of said word lines having a word line width defined by first and second word line edges and being separated from adjacent word lines by a word line separation distance, said word lines being substantially perpendicular to said bit lines, said word lines being formed using a third mask, a given one of said first and second word line edges of a given one of said word lines and a given one of said first and second bit line edges of a given one of said bit lines intersecting substantially outward of a center of a given one of said active regions; (g) locating a word line plug in each of said hole regions, each of said word line plugs extending from a corresponding adjacent one of said word lines inwardly into said hole region and terminating outward of said hole floor, each of said word line plugs being electrically isolated from said semiconductor material of said pillar such that a portion of each of said word line plugs adjacent to and electrically isolated from said semiconductor material of said pillar forms a gate of said MOS transistor with a corresponding portion of said semiconductor material of said pillar forming a channel region of said MOS transistor; (h) forming a plurality of storage nodes, one for each of said active regions, each of said storage nodes being offset from its corresponding one of said active regions in a direction away from said given one of said word lines and said given one of said bit lines which intersect substantially outwardly of said center of said given one of said active regions, said storage nodes being formed using a fourth mask; and (i) interconnecting said storage nodes with said hole floors of said pillars via a plurality of storage node plugs so as to form, at intersections of said storage node plugs with said hole floors, a plurality of storage node contacts and another of sources and drains of said plurality of MOS transistors, said storage node plugs extending through said hole regions in said pillars and being electrically isolated from said hole walls and said word line plugs.
- 13. The method of claim 12, further comprising the additional step of forming a plurality of trench isolators between said pillars to obtain said electrical isolation.
- 14. The method of claim 12, further comprising the additional step of forming a layer of gate SiO2 between each of said gates and each of said corresponding portions of said semiconductor material of said pillars.
- 15. The method of claim 12, wherein:
step (c) comprises forming said bit lines such that said bit line width and said bit line separation distance are both substantially equal to a characteristic minimum feature size F; step (f) comprises forming said word lines such that said word line width and said word line separation distance are also both substantially equal to said characteristic minimum feature size F; whereby a planform area of each of a plurality of memory cells, formed one at each of said plurality of pillars, is substantially 4F2.
- 16. The method of claim 12, wherein step (h) comprises forming said storage nodes such that said direction in which each of said storage nodes is offset from its corresponding one of said active regions is substantially identical for all of said storage nodes.
- 17. The method of claim 12, wherein step (h) comprises the sub-steps of:
(h-1) forming those of said storage nodes which are associated with even-numbered bit lines with said direction in which each of said storage nodes is offset from its corresponding one of said active regions substantially identical to each other; and (h-2) forming those of said storage nodes which are associated with odd numbered bit lines with said direction in which each of said storage nodes is offset from its corresponding one of said active regions substantially identical to each other and opposite to said direction for those storage nodes associated with said even numbered bit lines in a direction substantially parallel to said bit lines.
- 18. The method of claim 12, wherein:
step (d) comprises forming said bit line plugs such that they have a bit line plug outline when viewed in plan view; and step (g) comprises forming said word line plugs such that they have a word line plug outline when viewed in plan view; and step (i) comprises forming said storage node plugs such that they have a storage node plug outline when viewed in plan view; further comprising the additional step of shaping said bit line plugs, said word line plugs and said storage node plugs such that at least two of said word line plugs, said bit line plugs and said storage node plugs are not enclosed by any of said outlines of any other of said storage node plugs, said word line plugs and said bit line plugs.
- 19. The method of claim 18, wherein said shaping step comprises shaping said bit line plugs, said word line plugs and said storage node plugs such that all three of said bit line plugs, said word line plugs and said storage node plugs are not enclosed by any of said outlines of any other of said word line plugs, said bit line plugs and said storage node plugs.
- 20. The method of claim 19, wherein said shaping step comprises shaping said word line plugs, said bit line plugs and said storage node plugs such that all three of said plugs are solid when viewed in plan.
- 21. The method of claim 12, further comprising the additional step of shaping said storage node plugs, said bit line plugs and said word line plugs such that, for each of said pillars, associated ones of said storage node plugs, said bit line plugs and said word line plugs form a substantially asymmetric structure when viewed in plan.
- 22. The method of claim 21, wherein said shaping step comprises shaping said storage node plugs, said bit line plugs and said word line plugs such that each of said storage node plugs, said bit line plugs and said word line plugs has a substantially solid cross section when viewed in plan.
Parent Case Info
[0001] This application claims priority under 35 USC §119(e)(1) of provisional application No. 60/099,508 filed Sep. 8, 1999.
Provisional Applications (1)
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Number |
Date |
Country |
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60099508 |
Sep 1998 |
US |