Claims
- 1. A data processor executing instructions, comprising:an address register holding an operand address; a memory access unit coupled to said address register and accessing a memory to read 2n-bit data from a memory location of successive addresses, said operand address specifying the memory location; a 2n-bit data bus having 2n bit width and transferring the 2n-bit data from the memory simultaneously; a 2n-bit interface data register coupled to said 2n-bit data bus and holding the 2n-bit data transferred through said 2n-bit data bus; first and second n-bit buses each having n bit width and coupled to said 2n-bit interface data register; a register file coupled to said first and second n-bit buses, and including a plurality of n-bit registers each holding n-bit data; and an ALU having a first input receiving a first operand of at most n-bits from said register file and a second input receiving a second operand of at most n-bits from said register file, said ALU performing an operation on the first and second operands; wherein load operations are capable of being executed such that one half n-bit word and the other half n-bit word of the 2n-bit data are loaded to first and second ones of said plurality of n-bit registers from said 2n-bit interface data register through said first and second n-bit data buses, respectively, and such that one half-n-bit word of the 2n-bit data is loaded to a third one of said plurality of n-bit registers from said 2n-bit interface data register through said first n-bit data bus while the other half n-bit word of the 2n-bit data is not loaded to any registers coupled to said second n-bit data bus.
- 2. A data processor executing instructions, comprising:an address register holding an operand address; a memory access unit coupled to said address register and accessing a memory to store 2n-bit data into a memory location of successive addresses, said operand address specifying the memory location; a 2n-bit interface data register holding the 2n-bit data; a 2n-bit data bus having 2n bit width, said 2n-bit data bus coupled to said 2n bit interface data register and transferring the 2n-bit data to the memory from said 2n-bit interface data register simultaneously; first and second n-bit data buses each having n bit width and coupled to said 2n-bit interface data register; a register file coupled to said first and second n-bit buses, and including a plurality of n-bit registers each holding n-bit data; and an ALU having a first input receiving a first operand of at most n-bit from said register file and a second input receiving a second operand of at most n-bit from said register file, and ALU performing an operation on the first and second operands; wherein store operations are capable of being executed such that two n-bit words, which are one half and the other half of the 2n-bit data, are stored to said 2n-bit interface data register from first and second ones of said plurality of n-bit registers through said first and second n-bit data buses, respectively, and such that an n-bit word, which is one half of the 2n-bit data, is stored to said 2n-bit interface data register from a third one of said plurality of n-bit registers through said first n-bit data bus while an n-bit word are not stored to 2n-bit interface data register from any registers coupled to said second n-bit data bus.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 1-326254 |
Dec 1989 |
JP |
|
Parent Case Info
This is a continuation of application No. Ser. 08/548,766, filed Oct. 26. 1995 now U.S. Pat. No. 5,652,900 which is a continuation of Ser. No. 07/622,066 filed Dec. 13, 1990, now U.S. Pat. No. 5,481,734 the disclosure of which is incorporated by reference.
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Continuations (2)
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Number |
Date |
Country |
| Parent |
08/548766 |
Oct 1995 |
US |
| Child |
08/887681 |
|
US |
| Parent |
07/627066 |
Dec 1990 |
US |
| Child |
08/548766 |
|
US |
Patent Grant
6757809
