Claims
- 1. A Dynamic Random Access Memory (DRAM) device comprising:at least one DRAM memory array including a plurality of memory cells and a plurality of pairs of true and complementary digit lines coupled to the plurality of memory cells; and a plurality of sense amplifiers, each sense amplifier of said plurality of sense amplifiers including: isolating circuitry coupled between an equilibrate bias node of the DRAM device and one pair of digit lines of the plurality of pairs of digit lines of the at least one DRAM memory array isolating the one pair of digit lines from the equilibrate bias node and a cell plate voltage thereon during a margin test mode of the DRAM device; and switching circuitry coupled to the one pair of digit lines providing a ground voltage thereto during the margin test mode stressing all the plurality of memory cells of the at least one DRAM memory array substantially simultaneously.
- 2. The DRAM device of claim 1, wherein each of said switching circuitry comprises one or more NMOS transistors.
- 3. The DRAM device of claim 1, wherein the cell plate voltage comprises one-half a supply voltage of the DRAM device.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/392,154, filed Sep. 8, 1999 now U.S. Pat. No. 6,101,139, issued Aug. 8, 2000, which is continuation of application Ser. No. 09/026,244, filed Feb. 19, 1998, now U.S. Pat. No. 6,002,622, issued Dec. 14, 1999.
US Referenced Citations (13)
Non-Patent Literature Citations (1)
Entry |
Prince, B., “Semiconductor Memories: A Handbook of Design, Manufacture and Application,” (Wiley 1991, reprinted 1996). |
Continuations (2)
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Number |
Date |
Country |
Parent |
09/392154 |
Sep 1999 |
US |
Child |
09/583478 |
|
US |
Parent |
09/026244 |
Feb 1998 |
US |
Child |
09/392154 |
|
US |