Device and method for testing memory access time using PLL

Abstract

A device and method for testing memory access times of a memory using a phase-locked loop (PLL) are described. The device for testing the memory access time of a memory may include a PLL and a test unit, and may also include a memory controller. The PLL may generate a test signal having a variable period. The test unit may compare the test signal with a memory output and may output the result of the comparison as a test result for the memory access time. The test unit may include a delay portion and a test portion. The delay portion may delay the test signal to generate first to n-th (n may be a natural number) sub-test signals. The test portion may compare the first to n-th sub-test signals with the memory output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted.

FIG. 1 is a schematic block diagram of a conventional test device having an access-time measurement block (AMB).

FIG. 2 is a block diagram of an example test device for testing the memory access time of a memory using a phase-locked loop (PLL) according to example embodiments.

FIG. 3 is a circuit diagram of the example test device of FIG. 2.

FIG. 4 is a block diagram of an example test device for testing the memory access time of a memory according to example embodiments.

FIG. 5 is a schematic block diagram of an example semiconductor device having a built-in self-test (BIST) circuit, and including the example test device of FIG. 2 or the example test device of FIG. 4.

FIG. 6 is a flowchart of a method of testing the memory access time of a memory using a PLL according example embodiments.

Claims

1. A device for testing the memory access time of a memory, comprising: a PLL (phase-locked loop) for generating a test signal having a variable period; anda test unit for comparing the test signal with a memory output and for outputting the result of the comparison as a test result for the memory access time.

2. The device of claim 1, further comprising: a memory controller for transmitting a memory control signal having a longer period than the test signal to the memory, wherein the test unit is activated in response to the memory control signal.

3. The device of claim 2, wherein the test unit comprises: a delay portion for delaying the test signal in order to generate first to n-th (n is a natural number) sub-test signals; anda test portion for comparing the memory output with the first to n-th sub-test signals.

4. The device of claim 3, wherein the k-th sub-test signal (1≦k≦n, k is a natural number) is obtained by delaying the test signal by (k−1) times the period of the test signal.

5. The device of claim 3, wherein the delay portion includes first to n-th delay flip-flops, and the test portion includes first to n-th test flip-flops.

6. The device of claim 5, wherein the first to n-th delay flip-flops output the corresponding first to n-th sub-test signals in response to a test enable signal.

7. The device of claim 6, wherein the test enable signal is synchronized with a memory clock signal, which is an operating clock signal of the memory activated in response to the memory control signal.

8. The device of claim 7, wherein the test enable signal is the memory control signal inverted.

9. The device of claim 6, further comprising a test enable signal generator for generating the test enable signal.

10. The device of claim 5, wherein the first to n-th test flip-flops compare the corresponding first to n-th sub-test signals with the memory output and output the results of the comparison.

11. The device of claim 10, wherein, when the corresponding sub-test signal is coincident with the memory output, the corresponding test flip-flop outputs a logic-high signal.

12. The device of claim 11, wherein the memory access time is between a lower bound and an upper bound, the lower bound being the time determined by adding the propagation delay time of the sub-test signal having the longest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-low L, to the period of the test signal, and the upper bound being the time determined by adding the propagation delay time of the sub-test signal having the shortest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-high signal, to the period of the test signal.

13. The device of claim 2, further comprising a slow signal generator for generating a slow signal by dividing the test signal by 2m (m is a natural number).

14. The device of claim 13, wherein the slow signal generator includes m divider flip-flops.

15. The device of claim 13, wherein the memory controller inverts the slow signal in response to the enable signal in order to produce the memory control signal.

16. The device of claim 1, wherein the memory is RAM (random-access memory).

17. A built-in self-test circuit (BIST) comprising the device of claim 1.

18. The device of claim 1, wherein the test unit comprises: a delay portion delaying the test signal to generate first to n-th (n is a natural number) sub test signals; anda test portion comparing the corresponding first to n-th sub test signals with the memory output.

19. The device of claim 18, wherein the k-th sub-test signal (1≦k≦n, k is a natural number) is obtained by delaying the test signal by (k−1) times the period of the test signal.

20. The device of claim 19, wherein the delay portion includes first to n-th delay flip-flops, and the test portion includes first to n-th test flip-flops.

21. The device of claim 20, wherein the first to n-th delay flip-flops respectively output the corresponding first to n-th sub-test signals using the test signal.

22. The device of claim 20, wherein the first to n-th test flip-flops respectively compare the first to n-th sub-test signals with the memory output and output the results of the comparison.

23. The device of claim 22, wherein, when a sub-test signal corresponding to any one of the first to n-th test flip-flops is coincident with the memory output, the corresponding test flip-flop outputs a logic-high signal.

24. The device of claim 18, wherein the memory access time is between a lower bound and an upper bound, the lower bound being the time determined by adding the propagation delay time of the sub-test signal having the longest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-low L, to the period of the test signal, and the upper bound being the time determined by adding the propagation delay time of the sub-test signal having the shortest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-high signal, to the period of the test signal.

25. A built-in self-test circuit (BIST) comprising the device of claim 18.

26. A method of testing the memory access time of a memory, comprising: generating a test signal having a variable period;generating a memory control signal having a longer period than the test signal and transmitting the memory control signal to the memory; andcomparing the test signal with a memory output activated in response to the memory control signal and determining the memory access time.

27. The method of claim 26, wherein testing the memory access time comprises: generating first to n-th (n is a natural number) sub-test signals using the test signal; andcomparing the corresponding first to n-th sub-test signals with the memory output.

28. The method of claim 27, wherein the k-th sub-test signal (1≦k≦n, k is a natural number) obtained by delaying the test signal by (k−1) times the period of the test signal.

29. The method of claim 27, wherein generating the first to n-th sub-test signals includes generating the sub-test signals using first to n-th delay flip-flops in response to a test enable signal.

30. The method of claim 29, wherein the test enable signal is synchronized with a memory clock signal, which is an operating clock signal of the memory activated in response to the memory control signal and is the memory control signal inverted.

31. The method of claim 27, wherein comparing the first to n-th sub-test signals with the memory output includes outputting the results of the comparison by the first to n-th test flip-flops.

32. The method of claim 31, wherein, when the sub-test signal corresponding to any one of the first to n-th test flip-flops is coincident with the memory output, the associated test flip-flop outputs a logic-high signal.

33. The method of claim 32, wherein the memory access time is between a lower bound and an upper bound, the lower bound being the time determined by adding the propagation delay time of the sub-test signal having the longest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-low L, to the period of the test signal, and the upper bound being the time determined by adding the propagation delay time of the sub-test signal having the shortest delay time, among delay times of the sub-test signals input to the flip-flops which output a logic-high signal, to the period of the test signal.