None.
The invention relates to a workpiece support used in semiconductor plating systems having electrodes which engage the workpieces for electroplating metals, such as copper and others, onto seed, barrier and other layers formed on semiconductor wafers and other semiconductor workpieces.
In the production of semiconductor wafers and other semiconductor articles it is necessary to plate metals onto the semiconductor surface to provide conductive areas which transfer electrical current. There are two primary types of plating layers formed on the wafer or other workpiece. One is a blanket layer used to provide a metallic layer which covers large areas of the wafer. The other is a patterned layer which is discontinuous and provides various localized areas that form electrically conductive paths within the layer and to adjacent layers of the wafer or other device being formed. Plating can occur on a flat metal layer, through a non-conducting mask to an underlying metal layer or onto a patterned non-flat substrate.
There are a wide range of manufacturing processes that may be used to deposit the metallization on the workpiece in the desired manner. Such processes included chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), electroplating, and a damascene process where holes, more commonly called vias, trenches and other recesses are formed in the layer of semiconductor material in which a pattern of copper is desired. In the damascene process the wafer is first provided with a metallic seed layer which is used to conduct electrical current during a subsequent metal electroplating step. The seed layer is a very thin layer of metal which can be laid down using several processes. The seed layer of metal can be laid down using PVD or CVD processes to produce a layer on the order of 1000 angstroms thick. The seed layer can advantageously be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface which is convoluted by the presence of vias, trenches, or other device features which are recessed. This convoluted nature of the exposed surface provides increased difficulties in forming the seed layer in a uniform manner. Non-uniformities in the seed layer can result in variations in the electrical current passing from the exposed surface of the wafer during the subsequent electroplating process. This in turn can lead to non-uniformities in the blanket layer electroplated onto the seed layer. Such non-uniformities can cause deformities and failures in the resulting semiconductor device being formed.
In the damascene processes, after the seed layer is laid down, then it is typical to plate additional metal (e.g., copper) onto the seed layer in the form of a blanket layer formed thereon. The blanket layer is typically electroplated and is used to fill the vias and trenches. The blanket layer is also typically plated to an extent which forms an overlying layer. Such a blanket layer will typically be formed in thicknesses on the order of 3,000-15,000 angstroms (0.3-1.5 microns). Chemical mechanical polishing (“CMP”) is used to remove any excess copper and other metal above the features.
As damascene-interconnect feature sizes shrink, the barrier layer and seed layers used for manufacturing device metal interconnects (i.e. the dual-damascene process) become thinner and more resistive. Furthermore, it becomes more difficult to provide a uniform seed-layer thickness on the sidewalls of features as the features shrink. The seed layers are typically deposited using relatively expensive PVD vacuum processes and it may be necessary to improve the sidewall coverage by using a process such as the “seed layer repair” and “seed layer enhancement” processes developed by Semitool and disclosed in U.S. Pat. No. 6,197,181. It would be of great benefit to plate the seed layer directly on the barrier in a conformal manner, thereby, insuring good sidewall coverage and omitting the expense of the PVD process altogether.
To plate directly on a thin barrier layer, the very strong terminal effect created by the high sheet resistance must be overcome. This is very challenging when contacting the wafer around its circumference because a high voltage is required to pass current from the contact to the center of the wafer in order to plate at the center. The current will preferentially plate near the contact to avoid the sheet resistance. An electrolytic bath with a low conductivity reduces the terminal effect, but untested ultra low conductivity bath formulations (less than 1 mS/cm2 and down to 0.001 mS/cm2) would be required to enable relative uniform plating on the barrier layers expected below 45 nm feature sizes.
Moreover, the difficulty of plating on a barrier layer (or seed layer) is aggravated when the layer covers features on the surface of the wafer. In general, these features increase the effective length of the conductive film and, thus, increase the film sheet resistance compared to a blanket film. Typically these features are via and trench geometries (e.g. dual-damascene features) to be filled with copper to form metal interconnects. But not only do the features add to the overall sheet resistance, they can also create regions of anisotropic sheet-resistance making some areas of the wafer extremely difficult to plate. For example, the barrier layer covering trenches aligned with the current flow (e.g. along radial lines) will be less resistive than trenches perpendicular to the current flow. In addition, there may be underlying layers or pads that are more conductive than the barrier layer or seed layer connecting various features that are to be plated. For example, one via array may be connected to another via array by such an underlying structure. This conductive structure can shunt current and influence local plating voltages, thereby, disrupting the plating on the barrier layer. Accordingly, there is a need for electroplating equipment and methods that overcome the challenges inherent in plating highly resistive barrier and seed layers.
The present invention is provided to solve the problems discussed above and other problems, and to provide advantages and aspects not provided by prior electroplating equipment and methods of this type. A full discussion of the features and advantages of the present invention is deferred to the following detailed description, which proceeds with reference to the accompanying drawings.
The present invention proposes mechanical schemes to increase the contact points across a semiconductor workpiece in an electroplating vessel, rather than (or in addition to) contacting the wafer around its circumference as is the case in typical electroplating equipment and processes. By utilizing the gaps called “streets” or “scribes” that separate the individual dice on a wafer, it is possible to contact or touch the wafer in these streets without harming the devices on the wafer. The additional contact locations help to overcome the terminal effect caused by the very high sheet resistance of thin barrier layers and enable plating a conformal seed layer or feature filling directly on thin barrier layers.
In some embodiments of the present invention, the contact to the wafer approaches the die or device level in order to provide localized plating in an electrochemical plating vessel. For example, in one embodiment the present invention provides a wafer support for use in electroplating a semiconductor workpiece. The wafer support comprises a plurality of discrete contacts that make point contacts at selected points with the streets of the wafer. The discrete point contacts may contact the wafer at each corner of a die (or less frequently). In another embodiment of the present invention, continuous contacts may run along the entire length of the streets formed between the devices formed in the semiconductor wafer. The contacts may run along only the vertical streets or the horizontal streets, or may run along both directions forming a grid-like support structure. In any of these embodiments, the circumference/periphery of the semiconductor workpiece may (or may not) also be electrically contacted.
Since a plurality of discrete contact points or a grid-like contact structure may disrupt the electrolyte flow and mass transfer to the wafer when it is added to a conventional fountain plater, another aspect of the present invention combines the street contacts with a sparger flow system. Such a system allows for device-scale delivery and removal of process fluid, and local control of the current to each die from the anode.
To eliminate the die-specific nature of the contact geometry associated with a certain aspects of the present invention, an alternative embodiment of the present invention provides for relatively high conductivity current paths (e.g., bus paths) to be formed or imbedded in the streets. Thus, even when a conventional circumferential contact is used, the highly conductive streets provide a low resistance path around each die, effectively achieving the same result as contacting the wafer locally around each device.
Even more uniform barrier and seed layer plating may be achieved by coupling the localized die-level contact schemes discussed above with localized plating. For example, local die level anode shapes (or smaller) may be moved and/or controlled to enable better die scale plating. By locally plating one die at a time, the terminal effect is reduced because the overall current passing though the barrier at a given time is reduced and the voltage variations throughout the film are correspondingly reduced. Similarly, localized/dynamic control of the individual contacts across the streets or the circumference can create more controlled localized plating. For example, only a portion of the circumferential or street contacts may be active at a certain time. This dynamic control could be cycled around the wafer creating varying current flow directions and potential drops across the wafer to overcome the effects of anisotropic sheet-resistance and shorting by underlying conductive pads.
Other features and advantages of the invention will be apparent from the following specification taken in conjunction with the following drawings.
To understand the present invention, it will now be described by way of example, with reference to the accompanying drawings in which:
While this invention is susceptible of embodiments in many different forms, there is shown in the drawings and will herein be described in detail preferred embodiments of the invention with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspect of the invention to the embodiments illustrated.
Turning to
The workpiece contact assembly 25 sits atop the bowl 22 and is generally comprised of a contact plate 32 which supports the workpiece and a sparger plate 33 for distributing process fluid to the device side of the workpiece. Appropriate electrical connections are made with the contact assembly 25 to provide controlled electrical power to the contact assembly 25. Various embodiments of the workpiece contact assembly 25 will be discussed in greater detail below.
The process head assembly 15 accepts the workpiece W for processing and introduces the workpiece to the bowl assembly 20 by placing the workpiece onto the contact plate 32 for processing, and removes the workpiece W from the bowl assembly 20 after processing for transition to, for example, another processing station. The process head assembly 15 is comprised of a process head 34 and a rotor 35. The process head 34 holds a rotor drive assembly (not shown) which includes, among other components, a motor for spinning the process head assembly about the axis R. The process head 34 also includes an actuator that cooperates with components in the rotor 35 which cause fingers 36, which extend outwardly from the face of rotor 35, to engage and disengage from the periphery of the workpiece W.
The process head assembly 15 is preferably supported by process head operator 30. The operator 30 includes a linear drive 37 which is used to adjust the height of the process head assembly 15 with respect to the bowl assembly 20. The process head assembly 15 also includes a head rotor drive 38 which operates to rotate the process head assembly 15 about a horizontal axis H. The rotational movement of the process head assembly 15 allows it to be placed in a first position (approximately 180 degrees from the position of the process head assembly shown in
It should be understood by those having skill in the art that the contact assembly 25 of the present invention can be used in a plating reactor wherein the plating bath is comprised of a single electrolyte which is introduced into a bowl 22 having only a single compartment, rather than the multi-compartment bowl 22 and the use of a catholyte and an anolyte as disclosed in
With reference specifically to
The sparger plate 33 and the contact plate 32 will now be described in greater detail with reference to a preferred embodiment shown in
The sparger plate 33 is comprised of a base plate 43 having a plurality of spaced-apart, hollow cells 44 projecting outwardly therefrom. Each cell 44 has at least one aperture 44a, and preferably a plurality of apertures 44a for distributing the plating chemistry to the device side of the workpiece W. Because the cells 44 are spaced apart from one another, a groove 33a is formed between the cells 44. When the contact plate 32 and the sparger plate 33 are combined, the conductive members 32a of the contact plate 32 fit within the grooves 33a of the sparger plate 33 so that the sparger apertures 44a are positioned adjacent the workpiece W and in close proximity to the electrical contacts made with the workpiece W. As best shown in
Referring to
The conductive members 32a of the contact plate 32 may take many different forms in the present invention. Turning to
To eliminate the die-specific nature of the contact geometry associated with a certain aspects of the present invention, an alternative embodiment of the present invention provides for relatively high conductivity current paths (e.g., bus paths) to be formed or imbedded in the streets. This can be accomplished by creating conductive streets or electrical bus paths on the workpiece W. For example, a PVD copper bus line is deposited on the workpiece W. The bus line may be only within a first layer and contact to the bus lines is maintained on subsequent layers by having vias connecting to the bus path. Thus, even when a conventional circumferential contact is used, the highly conductive streets provide a low resistance path around each die, effectively achieving the same result as contacting the wafer locally around each device.
In another aspect of the present invention, even more uniform barrier and seed layer plating may be achieved by coupling the localized die-level contact schemes discussed above with localized plating. For example, local die level anode shapes (or smaller) may be moved and/or controlled to enable better die scale plating. By locally plating one die at a time, the terminal effect is reduced because the overall current passing though the barrier at a given time is reduced and the voltage variations throughout the film are correspondingly reduced. Similarly, localized/dynamic control of the individual contacts across the streets or the circumference can create more controlled localized plating. For example, only a portion of the circumferential or street contacts may be active at a certain time. This dynamic control could be cycled around the wafer creating varying current flow directions and potential drops across the wafer to overcome the effects of anisotropic sheet-resistance and shorting by underlying conductive pads.
While the specific embodiments have been illustrated and described, numerous modifications come to mind without significantly departing from the spirit of the invention, and the scope of protection is only limited by the scope of the accompanying Claims.
This application is a nonprovisional of U.S. Provisional Patent Application No. 60/669,312, filed Apr. 7, 2005, now pending. Priority to this application is claimed under 35 U.S.C. §§ 119, and the disclosure of this application is incorporated herein by reference in its entirety.
Number | Date | Country | |
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60669312 | Apr 2005 | US |