DIRECT BONDING AND DEBONDING OF ELEMENTS

BACKGROUND
Field

The field relates to direct bonding of a semiconductor element to a carrier, removing the carrier from the semiconductor element after the direct bonding, and structures therefor.

Description of the Related Art

In some applications, semiconductor elements (such as wafers and dies) are temporarily bonded to carriers for intermediate processing. However, it can be challenging to process (e.g., thin or conduct backside processing using conventional temporary bonding materials (adhesives). Accordingly, there remains a continuing need for improved methods and structures for temporary bonding.

BRIEF DESCRIPTION OF THE DRAWINGS

Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.

FIG. 1A is a schematic cross-sectional side view of two elements prior to direct hybrid bonding.

FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after direct hybrid bonding.

FIG. 2A is a schematic cross-sectional side view of a carrier.

FIG. 2B is a schematic cross-sectional side view of the carrier after being prepared for direct bonding.

FIG. 2C is a schematic cross-sectional side view of a semiconductor element with a bonding layer.

FIG. 2D is a schematic cross-sectional side view of the semiconductor element with the bonding layer after being prepared for direct bonding.

FIG. 2E is a schematic cross-sectional side view of a bonded structure.

FIG. 2F is a schematic cross-sectional side view of the bonded structure of FIG. 2E reproduced for illustration purposes.

FIG. 2G is a schematic cross-sectional side view of the carrier and the semiconductor element after de-bonding.

FIG. 2H is a schematic cross-sectional side view of the carrier and the semiconductor element on a debond tape.

FIG. 21 is a schematic cross-sectional side view of the carrier and the semiconductor element after de-bonding.

FIG. 3 is a schematic cross-sectional side view of a bonded structure according to an embodiment.

FIG. 4 is a schematic cross-sectional side view of a bonded structure according to another embodiment.

FIG. 5A is a schematic cross-sectional side view of a bonded structure according to another embodiment.

FIG. 5B is an enlarged view of a portion of the bonded structure shown in FIG. 5A.

FIG. 6A is a schematic cross-sectional side view of a semiconductor element with a bonding layer.

FIG. 6B is a schematic cross-sectional side view of the semiconductor element with the bonding layer after being prepared for direct bonding.

FIG. 6C is a schematic cross-sectional side view of a carrier.

FIG. 6D is a schematic cross-sectional side view of the carrier after being prepared for direct bonding.

FIG. 6E is a schematic cross-sectional side view of a bonded structure.

DETAILED DESCRIPTION

Embodiments described herein can combine direct bonding or hybrid direct bonding techniques with temporary bonding layers that are configured to release or debond the directly bonded elements.

Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. FIGS. 1A and 1B schematically illustrate a process for forming a directly hybrid bonded structure without an intervening adhesive according to some embodiments. In FIGS. 1A and 1B, a bonded structure 100 comprises two elements 102 and 104 that can be directly bonded to one another at a bond interface 118 without an intervening adhesive. Two or more microelectronic elements 102 and 104 (such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, individual active devices such as power switches, etc.) may be stacked on or bonded to one another to form the bonded structure 100. Conductive features 106a (e.g., contact pads, exposed ends of vias (e.g., TSVs), or a through substrate electrodes) of a first element 102 may be electrically connected to corresponding conductive features 106b of a second element 104. Any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so forth. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent one another along the first element 102. In some embodiments, the laterally stacked additional element may be smaller than the second element. In some embodiments, the laterally stacked additional element may be two times smaller than the second element.

In some embodiments, the elements 102 and 104 are directly bonded to one another without an adhesive. In various embodiments, a non-conductive field region that includes a non-conductive or dielectric material can serve as a first bonding layer 108a of the first element 102 which can be directly bonded to a corresponding non-conductive field region that includes a non-conductive or dielectric material serving as a second bonding layer 108b of the second element 104 without an adhesive. The non-conductive bonding layers 108a and 108b can be disposed on respective front sides 114a and 114b of device portions 110a and 110b, such as a semiconductor (e.g., silicon) portion of the elements 102, 103. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the device portions 110a and 110b. Active devices and/or circuitry can be disposed at or near the front sides 114a and 114b of the device portions 110a and 110b, and/or at or near opposite backsides 116a and 116b of the device portions 110a and 110b. Bonding layers can be provided on front sides and/or back sides of the elements. The non-conductive material can be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 can be directly bonded to the corresponding non-conductive bonding layer 108b of the second element 104 using dielectric-to-dielectric bonding techniques. For example, non-conductive or dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. It should be appreciated that in various embodiments, the bonding layers 108a and/or 108b can comprise a non-conductive material such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SiCOH dielectrics, silicon carbonitride or diamond-like carbon or a material comprising a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite the inclusion of carbon. In some embodiments, the dielectric materials do not comprise polymer materials, such as epoxy, resin or molding materials.

In some embodiments, the device portions 110a and 110b can have a significantly different coefficients of thermal expansion (CTEs) defining a heterogenous structure. The CTE difference between the device portions 110a and 110b, and particularly between bulk semiconductor, typically single crystal portions of the device portions 110a, 110b, can be greater than 5 ppm or greater than 10 ppm. For example, the CTE difference between the device portions 110a and 110b can be in a range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of the device portions 110a and 110b can comprise optoelectronic single crystal materials, including perovskite materials, that are useful for optical piezoelectric or pyroelectric applications, and the other of the device portions 110a, 110b comprises a more conventional substrate material. For example, one of the device portions 110a, 110b comprises lithium tantalate (LiTaO₃) or lithium niobate (LiNbO₃), and the other one of the device portions 110a, 110b comprises silicon (Si), quartz, fused silica glass, sapphire, or a glass. In other embodiments, one of the device portions 110a and 110b comprises a III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other one of the device portions 110a and 110b can comprise a non-III-V semiconductor material, such as silicon (Si), or can comprise other materials with similar CTE, such as quartz, fused silica glass, sapphire, or a glass.

In various embodiments, direct hybrid bonds can be formed without an intervening adhesive. For example, nonconductive bonding surfaces 112a and 112b can be polished to a high degree of smoothness. The bonding surfaces 112a and 112b can be cleaned and exposed to a plasma and/or etchants to activate the surfaces 112a and 112b. In some embodiments, the surfaces 112a and 112b can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces 112a and 112b, and the termination process can provide additional chemical species at the bonding surfaces 112a and 112b that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surfaces 112a and 112b. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. For example, in some embodiments, the bonding surface(s) 112a, 112b can be exposed to a nitrogen-containing plasma. Further, in some embodiments, the bonding surfaces 112a and 112b can be exposed to fluorine. For example, there may be one or multiple fluorine peaks at or near a bond interface 118 between the first and second elements 102, 104. Thus, in the directly bonded structure 100, the bond interface 118 between two non-conductive materials (e.g., the bonding layers 108a and 108b) can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bond interface 118. Additional examples of activation and/or termination treatments may be found throughout U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.

In various embodiments, conductive features 106a of the first element 102 can also be directly bonded to corresponding conductive features 106b of the second element 104. For example, a direct hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along the bond interface 118 that includes covalently direct bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., conductive feature 106a to conductive feature 106b) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. In direct hybrid bonding embodiments described herein, conductive features are provided within non-conductive bonding layers, and both conductive and nonconductive features are prepared for direct bonding, such as by the planarization, activation and/or termination treatments described above. Thus, the bonding surface prepared for direct bonding includes both conductive and non-conductive features.

For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (for example, inorganic dielectric surfaces) can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact features (e.g., conductive features 106a and 106b which may be at least partially surrounded by non-conductive dielectric field regions within the bonding layers 108a, 108b) may also directly bond to one another without an intervening adhesive. In various embodiments, the conductive features 106a, 106b can comprise discrete pads or traces at least partially embedded in the non-conductive field regions. In some embodiments, the conductive contact features can comprise exposed contact surfaces of through substrate vias (e.g., through silicon vias (TSVs)). In some embodiments, the respective conductive features 106a and 106b can be recessed below exterior (e.g., upper) surfaces (non-conductive bonding surfaces 112a and 112b) of the dielectric field region or non-conductive bonding layers 108a and 108b, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. In various embodiments, prior to direct bonding, the recesses in the opposing elements can be sized such that the total gap between opposing contact pads is less than 15 nm, or less than 10 nm. The non-conductive bonding layers 108a and 108b can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a and 106b can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI®, techniques commercially available from Adeia of San Jose, Calif., can enable high density of conductive features 106a and 106b to be connected across the direct bond interface 118 (e.g., small or fine pitches for regular arrays). In some embodiments, the pitch of the conductive features 106a and 106b, such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 100 microns or less than 10 microns or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 106a and 106b to one of the dimensions (e.g., a diameter) of the bonding pad is less than is less than 20, or less than 10, or less than 5, or less than 3 and sometimes desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 20 microns, e.g., in a range of 0.3 to 3 microns. In various embodiments, the conductive features 106a and 106b and/or traces can comprise copper or copper alloys, although other metals may be suitable. For example, the conductive features disclosed herein, such as the conductive features 106a and 106b, can comprise fine-grain metal (e.g., a fine-grain copper).

Thus, in direct bonding processes, a first element 102 can be directly bonded to a second element 104 without an intervening adhesive. In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 104 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 104 can comprise a carrier or substrate (e.g., a wafer). The embodiments disclosed herein can accordingly apply to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In wafer-to-wafer (W2W) processes, two or more wafers can be directly bonded to one another (e.g., direct hybrid bonded) and singulated using a suitable singulation process. After singulation, side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush and may include markings indicative of the common singulation process for the bonded structure (e.g., saw markings if a saw singulation process is used).

As explained herein, the first and second elements 102 and 104 can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface compared to a deposition. In one application, a width of the first element 102 in the bonded structure is similar to a width of the second element 104. In some other embodiments, a width of the first element 102 in the bonded structure 100 is different from a width of the second element 104. Similarly, the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element. The first and second elements 102 and 104 can accordingly comprise non-deposited elements. Further, directly bonded structures 100, unlike deposited layers, can include a defect region along the bond interface 118 in which nanometer-scale voids (nanovoids) are present. The nanovoids may be formed due to activation of the bonding surfaces 112a and 112b (e.g., exposure to a plasma). As explained above, the bond interface 118 can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface 118. The nitrogen peak can be detectable using secondary ion mass spectroscopy (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace OH groups of a hydrolyzed (OH-terminated) surface with NH2 molecules, yielding a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface 118. In some embodiments, the bond interface 118 can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers 108a and 108b can also comprise polished surfaces that are planarized to a high degree of smoothness.

In various embodiments, the metal-to-metal bonds between the conductive features 106a and 106b can be joined such that metal grains grow into each other across the bond interface 118. In some embodiments, the metal is or includes copper, which can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface 118. In some embodiments, the conductive features 106a and 106b may include nanotwinned copper grain structure, which can aid in merging the conductive features during anneal. The bond interface 118 can extend substantially entirely to at least a portion of the bonded conductive features 106a and 106b, such that there is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer may be provided under and/or laterally surrounding the conductive features 106a and 106b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features 106a and 106b, for example, as described in U.S. Pat. No. 11,195,748, which is incorporated by reference herein in its entirety and for all purposes.

Beneficially, the use of the hybrid bonding techniques described herein can enable extremely fine pitch between adjacent conductive features 106a and 106b, and/or small pad sizes. For example, in various embodiments, the pitch p (i.e., the distance from edge-to-edge or center-to-center, as shown in FIG. 1A) between adjacent conductive features 106a (or 106b) can be in a range of 0.5 microns to 50 microns, in a range of 0.75 microns to 25 microns, in a range of 1 micron to 25 microns, in a range of 1 micron to 10 microns, or in a range of 1 micron to 5 microns. Further, a major lateral dimension (e.g., a pad diameter) can be small as well, e.g., in a range of 0.25 microns to 30 microns, in a range of 0.25 microns to 5 microns, or in a range of 0.5 microns to 5 microns.

As described above, the non-conductive bonding layers 108a, 108b can be directly bonded to one another without an adhesive and, subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a, 106b can expand and contact one another to form a metal-to-metal direct bond. In some embodiments, the materials of the conductive features 106a, 106b can interdiffuse during the annealing process.

In some applications, it may be desirable to utilize thinned semiconductor elements, for example, in multi-element device stacks, such as memory devices. For example, a semiconductor element (such as a semiconductor device wafer) can be temporarily bonded to a carrier (e.g., a glass or silicon carrier wafer) by way of an adhesive (e.g., a polymer film or an organic adhesive), such as a heat curable or UV curable adhesive. The backside of the semiconductor element can be thinned by, for example, grinding and/or chemical mechanical polishing (CMP). Moreover, additional backside processing may be performed on the backside of the semiconductor element with the semiconductor element adhered to the carrier. For example, metallization or back-end-of-line (BEOL) layers may be deposited or otherwise provided on the thinned semiconductor element.

However, the use of adhesives in temporary bonds can be challenging in a number of respects. For example, as the device wafer is thinned, the residual stress from the BEOL film as well as any thermal processing may cause lateral expansion of the die size because the organic adhesive may not provide a sufficient bond strength to constrain the lateral growth of the device wafer. Furthermore, the mechanical stability of the adhesive bond between the device wafer and the carrier wafer during the thinning process (e.g., a grinding process) may deteriorate or become unreliable due to the forces imparted during thinning. The adhesive may have thickness non-uniformity or uneven thickness along a bonding surface. In some cases, the thinning process may also cause the thickness of the device wafer to vary significantly so as to exceed a desired total thickness variation (TTV). For example, the intervening temporary adhesive between the device wafer and the carrier wafer can have non-uniformities that can result in excessive thickness variation upon thinning. Moreover, the temporary adhesive bond may not have sufficient thermal and/or chemical stability when exposed to various processes. For example, the temporary adhesive may degrade when exposed to the chemicals used for wafer cleaning, electrochemical deposition (ECD), and/or CMP. The adhesive may alternatively or additionally decompose during deposition and/or etch processes (such as chemical vapor deposition (CVD), plasma-enhanced CVD, physical vapor deposition, etc.). For another example, the organic adhesive may have relatively low thermal conductivity. In addition, when the carrier and adhesive are removed from the device wafer, the device wafer may include residue from the adhesive, which may cause the use of an extra cleaning step. Accordingly, there remains a continuing need for improved methods and structures for temporarily bonding elements for processing (e.g., thinning) the element.

FIGS. 2A-2E illustrate a bonding method and FIGS. 2F-2I illustrate a de-bonding or releasing method according to various embodiments. The bonding method and the de-bonding method can be performed in sequence to form a processed (e.g., thinned) element. FIG. 2A is a schematic cross-sectional side view of a first element (e.g., a carrier 10). The carrier 10 can comprise an intervening layer 14, which may be an inorganic layer such as a silicon oxide, on the substrate 12, a release layer 16 on the intervening layer 14, and a bonding layer 18, which can also be a dielectric layer such as a silicon oxide layer, on the release layer 16. In the illustrated embodiment, the release layer 16 is prepared with the carrier 10. However, in some other embodiments, the release layer 16 can be prepared with a semiconductor element 20 on a device portion 22 at FIG. 2C (see FIGS. 6A-6I). In some embodiments, the substrate 12 can comprise a wafer. The substrate 12 can comprise any suitable material such as glass, low-doped silicon, etc. In some embodiments, the substrate 12 can comprise a bulk carrier portion. Each of the intervening layer 14 and the bonding layer 18 can comprise a non-conductive material, such as the materials noted above as suitable for direct bonding, including but not limited to silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, etc. The intervening layer 14 can be thin. For example, the intervening layer 14 can be in a range between 50 nm and 500 nm, or 100 nm and 200 nm. The intervening layer 14 may serve an adhesion function between the release layer 16 and the substrate 12. If neither barrier function nor adhesion functions are called for, for example with a sacrificial or non-active carrier such as a glass substrate, the intervening layer 14 can be omitted.

The release layer 16 can comprise a material that is configured to outgas in response to application of thermal energy. In some embodiments, the release layer 16 can outgas in response to heating or radiating. For example, the release layer 16 can be configured to outgas in response to radiant heating, laser rastering, rapid thermal annealing, thermal annealing, or microwave heating. In some embodiments, the release layer 16 can comprise a carbon-containing layer, such as a primarily carbon layer. The release layer 16 can comprise amorphous carbon that includes contaminants. The contaminants can include species that can become volatile and evolve as gas upon absorption of energy. In some embodiments, the volatile species include hydrogen. In some embodiments, the volatile species include a halogen, such as chlorine or fluorine. The contaminants can also include species that do not evolve gas, in addition to the volatile species.

In some embodiments, the release layer 16 can comprise amorphous carbon with hydrogen and fluorine. The release layer 16 can include volatilizable constituents sufficient to allow mechanical release upon absorption of energy, but has a composition that is mechanically sound for supporting subsequent processing as described herein. In some embodiments, hydrogen and fluorine can represent between about 10 wt. % and 85 wt. % of the release layer 16, more particularly between about 30 wt. % and 65 wt. %.

The release layer 16 can be deposited on the intervening layer 14. For example, the release layer 16 can be deposited by way of chemical vapor deposition (CVD), and more particularly by plasma-enhanced CVD (PECVD), or physical vapor deposition (PVD). The release layer 16 can have a thickness in a range of, for example, 10 nm to 3 μm, from 10 nm to 500 nm, or more particularly in a range of, for example, 200 nm to 500 nm. In other embodiments, the release layer can have a thickness from about 500 nm to 1 μm. In general, the thickness can be selected to generate sufficient outgassing to allow physical separation and can be readily deposited with available equipment. Because one of the functions of the release layer 16 can be to absorb thermal energy in order to release gases, a thicker layer may be advisable if thickness uniformity can be maintained. The thickness of the release layer 16 can have a thickness uniformity less than, for example, 3%, or less than, for example, 1.5%.

Providing the release layer 16 by PECVD advantageously enables deposition at low temperatures and tuning deposition parameters to tune the release gas(es) content of the release layer 16. For example, PECVD of an α-C:H, F layer can employ hydrocarbon and/or hydrofluorocarbon precursors (e.g., CHF₃, CH₄, CF₄, C₂H₆, C₃F₆, C₄F₈, C₆F₆, C₆H₅F, HFPO, SF₆, NF₃, H₂, N₂, He, Ar, CH₄, C₂H₂, C₆H₆, etc.) and inert gas. Other alkanes that are partially or fully fluorinated and can be readily delivered into the vacuum chamber in the gas phase may also be employed. Further, alkene analogues material may be employed. Among other parameters, deposition temperature, plasma power and pressure can be tuned to tune the hydrogen and/or fluorine content. Desirably, the content is sufficient to allow volatilizing between 10% and 95% of the film thickness, more particularly between 50% and 90% of the film thickness, upon heating as described below. At the same time, an α-C:H, F (originally developed for low k applications in semiconductor interconnect layers) can be robust enough to withstand the desired processing of the temporarily bonded structure, and provide a sufficiently uniform thickness to provide a flat overlying bonding layer 18. Particular settings will of course depend upon the tool being employed for the deposition. One non-limiting example is the use of an ECR plasma at 2 mTorr and 600 W of applied plasma-generating power. Deposition temperatures can be, for example, 50° C. to 300° C., desirably less than 200° C. The deposition temperature for providing the release layer 16 is lower than a release temperature for releasing the release layer 16. Advantageously, no post-deposition anneal is performed to avoid loss of hydrogen and fluorine content.

At FIG. 2B, after depositing the bonding layer 18 over the release layer, the bonding layer 18 can be prepared for direct bonding. A bonding surface of the bonding layer 18 can be polished to a high degree of smoothness. For example, the bonding surface can be polished to a root-mean-square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The bonding surface can be cleaned and exposed to a plasma and/or etchants to activate the bonding surface thereby at least partially defining a prepared surface 18a. In some embodiments, the bonding surface can be terminated with a species that enhances direct bonding strength for the non-conductive bonding layers after activation or during activation (e.g., during the plasma and/or etch processes).

FIG. 2C is a schematic cross-sectional side view of a second element, in this case a semiconductor element 20 with a bonding layer 24. Like the bonding layer 18 of the carrier 10, the bonding layer 24 of the second element can comprise an inorganic, non-conductive material, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, etc. The semiconductor element 20 can comprise a semiconductor device element in wafer form or as a singulated integrated device die. The semiconductor element 20 can comprise a device portion 22 having active circuitry and/or devices therein. As described above, in some other embodiments, the release layer 16 can be prepared with the semiconductor element 20, instead of preparing the release layer 16 with the carrier 10.

At FIG. 2D, the bonding dielectric layer 24 can be prepared for direct bonding. A bonding surface of the bonding dielectric layer 24 can be polished to a high degree of smoothness. For example, the bonding surface can be polished to a root-mean-square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The bonding surface can be cleaned and exposed to a plasma and/or etchants to activate the bonding surface thereby at least partially defining a prepared surface 24a. In some embodiments, the bonding surface can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes).

At FIG. 2E, the semiconductor element 20 can be bonded to the carrier 10.

The prepared surface 24a of the semiconductor element 20 and the prepared surface 18a of the carrier 10 can be directly bonded to one another without an intervening adhesive along a bonding interface 26. As described above, direct bonding can be conducted at room temperature and without externally applied pressure (apart from, for example, a light directed touch to initiate bond front propagation), with or without subsequent annealing to strengthen the direct bond.

FIG. 2F is a schematic cross-sectional side view of a bonded structure 30 formed in FIG. 2E. The bonded structure 30 includes the semiconductor element 20 that is directly bonded to the carrier 10. The device portion 22 of the semiconductor element 20 can be processed. In some embodiments, the device portion 22 of the semiconductor element 20 can be thinned or otherwise processed (e.g., by addition of BEOL layers) while in the bonded structure 30. For example, a backside 22a of the device portion 22 can be thinned by way of grinding and/or chemical mechanical polishing (CMP). Other processing at this stage can include robotic transfer and bonding the backside of the semiconductor element 20 to a third element (not shown).

At FIG. 2G, after any processing, the carrier 10 of the bonded structure 30 can be removed from the semiconductor element 20 by transferring thermal energy to the release layer 16 to thereby induce diffusion of gas out of the release layer 16. In some embodiments, the release layer 16 can outgas hydrogen and/or fluorine. The thermal energy can be transferred to the release layer 16 by, for example, radiating, laser rastering, thermal annealing, rapid thermal annealing, microwave heating, etc. When radiant heat or laser raster is used for transferring thermal energy to the release layer 16, the substrate 12 can comprise a material that is transparent to the light. The laser or radiant heating light can irradiate the release layer 16 through the substrate 12 thereby heating the release layer 16 to cause outgassing. In some embodiments, the release layer 16 can be locally heated. In some other embodiments, the entire bonded structure 30 can be heated. In some embodiments, the thermal energy can heat the release layer 16 to a temperature of about 100° C. to 400° C., particularly about 200° C. to 250° C. In some embodiments, the temperature for heating the release layer 16 can be at least 50° C. higher than the deposition temperature used for depositing the release layer 16.

An amount of gas released from the release layer 16 can be controlled. In some embodiments, the temperature applied to the release layer 16 can be controlled to change the amount of gas released from the release layer 16. In some embodiments, amount of the gaseous elements incorporated in the release layer 16 can be modulated by controlling the deposition process of the release layer 16 to change the amount of gas released from the release layer 16 upon heating. For example, the amount of volatile gases within the release layer 16 can be adjusted by adjusting a fluorine and/or hydrogen content in the release layer 16, such as by control of the plasma power, substrate bias, precursor flow rate, pressure and/or substrate temperature in a release layer deposition process.

Alternatively, at FIG. 2H, a debond tape 32 or other element can be attached to the substrate 12 prior to removing the carrier 10 from the semiconductor element 20. In some embodiments, the debond tape 32 can comprise a dicing tape.

At FIG. 21, the carrier 10 of the bonded structure 30 can be removed from the semiconductor element 20 by transferring thermal energy to the release layer 16 to thereby induce diffusion of gas out of the release layer 16.

In some embodiments, after the carrier 10 is removed from the semiconductor element 20, a surface of the semiconductor element 20 can be ashed to clean residues of the release layer 16. Though the release layer 16 is provided with the carrier 10 in the illustrated embodiments, in various embodiments, the release layer 16 can alternatively be provided with the semiconductor element 20 (see FIGS. 6A-6E). Also, in various embodiments, the carrier 10 can comprise a semiconductor element, and two semiconductor elements can be directly bonded and de-bonded.

After processing the semiconductor element 20, the semiconductor element 20 can be bonded to another element (not shown). In some embodiments, the semiconductor element 20 can be directly bonded to another element without an intervening adhesive. For example, the semiconductor element 20 and the other element can be directly bonded to one another in a manner described with respect to FIGS. 1A and 1B. For example, the semiconductor element 20 can comprise the first element 102 and the other element can comprise the second element 104 of FIGS. 1A and 1B.

FIG. 3 is a schematic cross-sectional side view of a bonded structure 34 according to an embodiment. Unless otherwise noted, the components of FIG. 3 may be similar to or the same as like components of FIGS. 1A to 2I. The release layer 16 can have a footprint that is smaller than a footprint of the substrate 12 or the intervening layer 14 of the carrier 10. The footprint of the release layer 16 can be sized to provide sufficient bonding strength for processing (thinning) the semiconductor element 20, and for release of the elements upon outgassing. In some embodiments, side edges of the release layer 16 can be covered by the material of the intervening layer 14 or the bonding layer 18. The intervening layer 14 or the bonding layer 18 can protect the side edges of the release layer 16 from chemicals used in intervening process steps before releasing the release layer 16.

FIG. 4 is a schematic cross-sectional side view of a bonded structure 36 according to an embodiment. Unless otherwise noted, the components of FIG. 4 may be similar to or the same as like components of FIGS. 1A to 3. The bonded structure 36 can include two release layers (a first release layer 16 and a second release layer 16′). In some embodiments, the first layer 16 can be provided with the carrier 10, and the second release layer 16′ can be provided with the semiconductor element 20. For example, the semiconductor element 20 can comprise the device portion 22, an intervening layer 38 on the device portion 22, the second release layer 16′ on the intervening layer 38, and the bonding layer 24 on the second release layer 16′, and the carrier 10 can comprise the substrate 12, the intervening layer 14 on the substrate 12, the first release layer 16 over the intervening layer 14, and the bonding layer 18 over the intervening layer 14. The bonding layers 18, 24 can be bonded along the bonding interface 26 as shown in FIG. 4.

In some embodiments, the first release layer 16 and the second release layer 16′ can comprise the same material or different materials. For example, the first release layer 16 and the second release layer 16′ can comprise different ratios of fluorine and/or hydrogen. By having different release layers for the first and second release layers 16, 16′, temperatures at which the first and second release layers 16, 16′ outgas can be controlled.

FIG. 5A is a schematic cross-sectional side view of a bonded structure 40 according to an embodiment. FIG. 5B is an enlarged view of a portion of the bonded structure 40 shown in FIG. 5A. Unless otherwise noted, the components of FIGS. 5A and 5B may be similar to or the same as like components of FIGS. 1A to 4. The bonded structure 40 can include a reflective layer 42 and a dielectric layer 44 disposed between the reflective layer 42 and the substrate 12. The reflective layer 42 can be beneficial when radiant energy (e.g., laser rastering) is used to induce diffusion of gas from the release layer 16. For example, laser light can reach the release layer 16 through the substrate 12 and some of the laser light can pass through the release layer 16. The reflective layer 42 can reflect the laser light that passed through the release layer 16 back to the release layer 16 there my enhancing or maximizing transfer of energy from the laser light source to the release layer 16. In some embodiments, the reflective layer 42 can comprise a reflective metal that is reflective against a wavelength of the radiant energy. Therefore, the reflective layer 42 can reflect the laser light back into the release layer 16 to facilitate the decomposition. In some embodiments, the reflective layer 42 can be partially transparent.

In FIGS. 2A and 2B, the release layer 16 is prepared with the carrier 10. However, as discussed herein, in some other embodiments, the release layer 16 can be prepared with a semiconductor element 20 on a device portion 22. FIGS. 6A-6E illustrate a bonding method according to various embodiments in which the release layer 16 is prepared with a semiconductor element 20. FIGS. 6A-6E can be generally similar to FIGS. 2A-2E. Unless otherwise noted, the components of FIGS. 6A-6E may be similar to or the same as like components of other figures disclosed herein.

In one aspect, a bonding method is disclosed. The bonding method can include providing a first element having a device portion and a first nonconductive bonding material disposed over the device portion of the first element. The bonding method can include providing a second element that includes a carrier. The second element has a substrate and a second nonconductive bonding material disposed over the substrate of the second element. The bonding method can include depositing a release layer between the device portion and the first nonconductive bonding material of the first element or between the substrate and the second nonconductive bonding material of the second element. The bonding method can include directly bonding the first nonconductive bonding material of the first element to the second nonconductive bonding material of the second element without an intervening adhesive. The bonding method can include removing the second element from the first element by transferring thermal energy to the release layer to thereby induce diffusion of gas including volatile species out of the release layer.

In one embodiment, the volatile species includes hydrogen.

In one embodiment, the volatile species includes a halogen.

In one embodiment, the volatile species includes hydrogen and fluorine.

In one embodiment, the release layer is deposited by way of plasma-enhanced vapor deposition (PECVD).

In one embodiment, the release layer has a thickness in a range between 10 nm to 3 μm.

In one embodiment, the release layer includes carbon. The release layer can include amorphous carbon. The amorphous carbon can include hydrogen. The amorphous carbon can include fluorine.

In one embodiment, the transferring thermal energy includes heating the directly bonded second element and first element.

In one embodiment, the transferring thermal energy includes radiating the release layer through the substrate of the second element. The radiating can include laser rastering. The substrate can be transparent to laser light used for the laser rastering.

In one embodiment, the transferring thermal energy includes rapid thermal annealing, thermal annealing, or microwave heating.

In one embodiment, the transferring thermal energy causes the release layer to outgas volatile species thereby weakening a bond between the first element and the second element to effectuate the removal of the second element from the first element. The volatile species can include hydrogen. The volatile species can include a halogen. The volatile species can include hydrogen and fluorine.

In one embodiment, the directly bonding includes contacting the first element and the second element and heating the contacted first element and second element with a first temperature lower than a second temperature used for heating the directly bonded second element and first element for the removal. The second temperature can be in a range of 100° C. to 400° C. The second temperature can be in a range of 200° C. to 250° C.

In one embodiment, the bonding method further includes, prior to the direct bonding, activating at least one of a surface of the first nonconductive bonding material and a surface of the second nonconductive bonding material.

In one embodiment, the first nonconductive bonding material includes an inorganic dielectric material.

In one embodiment, the second nonconductive bonding material includes an inorganic dielectric material.

In one embodiment, the depositing the release layer is conducted on an intervening layer such that the intervening layer is positioned between the substrate of the second element and the release layer. The intervening layer can be configured to serve an adhesion function between the release layer and the substrate.

In one embodiment, the bonding method further includes, after the directly bonding, processing the first element. The processing the first element can include thinning a back side of the first element. The back side is opposite the first nonconductive bonding material. The processing the first element can include forming interconnects on the back side of the first element. The bonding method can further include bonding a debond tape to the thinned back side of the first element. The removing can be performed after bonding the debond tape to the first element. The bonding method can further include directly bonding a second first element to the first element. The removing can be performed after directly bonding the second first element to the first element.

In one embodiment, the bonding method further includes, after the removing, ashing a surface of the first element removed from the second element.

In one embodiment, the bonding method further includes, after the removing, singulating the first element into a plurality of singulated first elements.

In one embodiment, the bonding method further includes, before the removing, singulating the second element and the first element into a plurality of bonded structures.

In one embodiment, the depositing the release layer is conducted on an intervening layer over the device portion of the first element, such that the intervening layer is positioned between the device portion of the first element and the release layer.

In one embodiment, the depositing the release layer is conducted on the second element prior to forming the second nonconductive bonding material. A footprint of the release layer can be smaller than a footprint of the second nonconductive bonding material such that an end of the release layer is inset relative to an end of the second nonconductive bonding material. The end of the release layer can be covered by the second nonconductive bonding material. The bonding method can further include depositing a second release layer between the device portion and the first nonconductive bonding material of the first element. The second release layer can be configured to outgas at a temperature that is higher than a temperature for the release layer to outgas.

In one embodiment, the bonding method further includes tuning a deposition process for depositing the release layer to tune an amount of volatile gases within the release layer. Tuning the amount of volatile gases can include adjusting a fluorine-hydrogen ratio. Tuning the amount of volatile gases can include adjusting a substrate bias or a deposition precursor flow rate of a plasma enhance chemical vapor deposition process.

In one embodiment, the bonding method further includes providing a reflection layer between the release layer and the first element.

In one embodiment, the volatile gaseous species includes fluorine and hydrogen.

In one embodiment, the method further includes removing the second element from the first element by transferring thermal energy to the amorphous carbon layer to induce diffusion of gas out of the amorphous carbon layer

In one embodiment, providing the second element includes depositing the amorphous carbon layer by way of plasma-enhanced chemical vapor deposition (PECVD).

In one embodiment, the transferring thermal energy includes heating the directly bonded second element and first element.

In one embodiment, the transferring thermal energy includes radiating the amorphous carbon layer through the substrate of the second element. The radiating can include laser rastering, and wherein the substrate is transparent to laser light used for the laser rastering.

In one embodiment, the transferring thermal energy includes rapid thermal annealing, thermal annealing, or microwave heating.

In one embodiment, the transferring thermal energy causes the amorphous carbon layer to outgas hydrogen and fluorine thereby weakening the amorphous carbon layer to effectuate the removal of the second element from the first element.

In one embodiment, the first nonconductive bonding material includes a dielectric material.

In one embodiment, the second nonconductive bonding material includes a dielectric material.

In one embodiment, the bonding method further includes, after the directly bonding, thinning a back side of the first element, the back side opposite the nonconductive bonding material. The bonding method can further include bonding a debond tape to the thinned back side of the first element. The removing can be performed after bonding the debond tape to the first element. The bonding method can further includes directly bonding a second first element to the first element. The removing can be performed after directly bonding the second first element to the first element.

In one embodiment, the bonding method further includes, after the removing, ashing a surface of the first element removed from the second element.

In one embodiment, the bonding method further includes, after the removing, singulating the first element into a plurality of singulated first elements.

In one embodiment, the bonding method further includes, before the removing, singulating the second element and the first element into a plurality of bonded structures.

In one embodiment, a footprint of the amorphous carbon layer is smaller than a footprint of the second nonconductive bonding material.

In one embodiment, the bonding method further includes depositing a second amorphous carbon layer between the device portion and the first nonconductive bonding material. The amorphous carbon layer can be disposed between the substrate and the second nonconductive bonding material.

In one embodiment, the bonding method further includes tuning an amount of volatile gases within the amorphous carbon layer by tuning deposition conditions for the amorphous carbon layer. Adjusting the amount of volatile gases can include adjusting a fluorine-hydrogen ratio.

In one embodiment, the bonding method further includes providing a reflection layer between the amorphous carbon layer and the first element.

In one aspect, a carrier is disclosed. The carrier can include a substrate, an intervening layer on the substrate, a deposited carbon layer that is configured to outgas when heated, and a nonconductive bonding layer on the deposited carbon layer. The nonconductive bonding layer is configured to directly bond to a semiconductor element.

In one embodiment, the deposited carbon layer includes amorphous carbon.

The amorphous carbon can include fluorine and hydrogen. The deposited carbon layer can have a thickness uniformity within 3%. The fluorine and hydrogen can represent between 10 wt. % and 85 wt. % of the deposited carbon layer.

In one embodiment, the nonconductive bonding layer is prepared for direct bonding. A surface of the nonconductive bonding layer can have a root-mean-square (rms) surface roughness of less than 2 nm and is configured for direct bonding.

In one aspect, a semiconductor element is disclosed. The semiconductor element can include a device portion, an intervening layer on the device portion, a deposited release layer that is configured to outgas hydrogen and fluorine when heated, a nonconductive bonding layer on the deposited release layer. The nonconductive bonding layer is configured to directly bond to an element.

In one embodiment, the deposited release layer is an amorphous carbon layer that comprises hydrogen and fluorine. The fluorine and hydrogen can represent between 10 wt. % and 85 wt. % of the deposited carbon layer.

In one embodiment, the deposited release layer has a thickness uniformity within 3%.

In one embodiment, the nonconductive bonding layer is prepared for direct bonding. A surface of the nonconductive bonding layer has a root-mean-square (rms) surface roughness of less than 2 nm.

In one aspect, a temporary bonding method is disclosed. the bonding method can include providing a first element having a device portion and a first nonconductive bonding material disposed over the device portion of the first element. The bonding method can include providing a second element having a substrate and a second nonconductive bonding material disposed over the substrate of the second element. The bonding method can include depositing a release layer by way of plasma enriched chemical vapor deposition (PECVD) between the device portion and the first nonconductive bonding material of the first element, or between the substrate and the second nonconductive bonding material of the second element. The bonding method can include directly bonding the first nonconductive bonding material of the first element to the second nonconductive bonding material of the second element without an intervening adhesive.

In one embodiment, the transferring thermal energy induces diffusion of hydrogen and fluorine.

In one embodiment, the bonding method further includes removing the second element from the first element by transferring thermal energy to the release layer to thereby induce diffusion of gas out of the release layer. The release layer can include an amorphous carbon layer that includes hydrogen and fluorine. Removing can include outgassing hydrogen and fluorine.

In one aspect, a bonding method is disclosed. The bonding method can include providing a first element having a device portion and a first nonconductive material disposed over the device portion of the first element. The bonding method can include providing a second element having a substrate and a second nonconductive material disposed over the substrate of the second element. The bonding method can include depositing a release layer by way of plasma enriched chemical vapor deposition (PECVD) on the first nonconductive material of the first element or the second nonconductive material of the second element. The bonding method can include providing a third nonconductive material on the release layer, and directly bonding the first nonconductive material or the second nonconductive material to the third nonconductive material without an intervening adhesive.

In one embodiment, the first, second, and third nonconductive materials comprises an inorganic dielectric material.

In one embodiment, the release layer includes an amorphous carbon layer that includes hydrogen and fluorine that can outgas in response to heating.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

DIRECT BONDING AND DEBONDING OF ELEMENTS

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