Patent Application
20240420917
A sample may be evaluated by scanning one or more regions of the sample with an electron beam. The sample may be a semiconductor wafer that includes multiple dies. Other samples may be provided.
A sample may include a vast number of structural elements of microscopic scale. For example, a sample may include structural elements having dimensions that are less than 10 microns, less than 1 micron, less than one hundred nanometers, and even below one hundred nanometers.
Various regions of the wafer may be scanned during one or more types of wafer evaluations. The scanning can be executed by a charged particle evaluation system.
A defect review (DR) scanning electron microscope may scan multiple regions of the sample in order to review suspected defects.
A critical dimension (CD) scanning electron microscope may scan multiple regions of the sample in order to measure critical dimensions.
A metrology system may scan multiple regions and measure structural elements located within the multiple regions of the sample.
An electron beam inspection system may scan multiple regions and inspect elements located within the multiple regions of the sample.
A single scan of a region (that includes one or more structural elements of interest) may provide a frame which may exhibit a relatively low signal to noise ratio. In order to improve the signal to noise ratio, the region is scanned multiple times (for example between 10 and 50 times, between 20 and 30 times, and the like) to provide multiple frames.
The multiple frames are processed (for example are added to each other or averaged) to provide a single image of the region. The single image exhibits a much higher signal to noise ratio than the single frame.
The region usually includes non-conductive elements or only partially conductive elements (such as semiconductors, dielectric materials, and the like).
The scanning of a region that includes non-conductive elements or only partially conductive elements charges the surface of the region.
The charging of the surface of the region may reduce the quality of the frame and may reduce the quality of the image.
There is a growing need to discharge the surface of the region.
There is provided a system for discharging a region of a sample, the system includes (a) illumination optics that is configured to discharge the region by illuminating the region of the sample with a laser pulse during an illumination iteration; and (b) a timing circuit that is configured to trigger the illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam.
There is provided a method for discharging a region of a sample, the method includes (a) triggering, by a timing circuit, an illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam; and (b) discharging, by illumination optics, the region by illuminating the region of the sample with a laser pulse during the illumination iteration.
There is provided a non-transitory computer readable medium that stores instructions that once executed by a timing circuit, causes the timing circuit to: (a) trigger an illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam; wherein the illumination iteration includes discharging, by illumination optics, the region by illuminating the region of the sample with a laser pulse.
The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with specimen s, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure.
However, it will be understood by those skilled in the art that the present embodiments of the disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present embodiments of the disclosure.
The subject matter regarded as the embodiments of the disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The embodiments of the disclosure, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.
Because the illustrated embodiments of the disclosure may for the most part, be implemented using optical and/or electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present embodiments of the disclosure and in order not to obfuscate or distract from the teachings of the present embodiments of the disclosure.
Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method and should be applied mutatis mutandis to a computer program product that stores instructions that once executed result in the execution of the method.
Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system should be applied mutatis mutandis to a computer program product that stores instructions that can be executed by the system.
Any reference in the specification to a computer program product should be applied mutatis mutandis to a method that may be executed when executing instructions stored in the computer program product and should be applied mutandis to a system that is configured to executing instructions stored in the computer program product.
The term and/or means additionally or alternatively. For example A and/or B means only A, or only B or A and B.
It has been found that a region that is scanned by an electron beam may be discharged using light.
The region is scanned by an electron beam using a scan pattern that includes one or more idle periods during which the region is not illuminated by the electron beam. A single scan of the region (following the scan pattern) may result in a single frame. Multiple frames may be generated during a scan session to be processed and provide a single image of the region.
A line of a region is a sub-region that is illuminated by the electron beam when the electron beam linearly scans the region. The width of the line is the width of a spot formed by the electron beam on the region. The length of the line is mainly determined by the length of the linear scan.
In an example of a scan pattern, a line of the region is scanned with the electron beam, from left to right, till reaching the right end of the line. After reaching the right end of the line, the electron beam is turned off and is directed back to a left end of the next line. After reaching the left end of the next line, the electron beam scans the next line until reaching the right end of the next line.
The region may be discharged during an illumination iteration.
The illumination iteration may occur during an idle period.
The illumination iteration may be shorter than the idle period (for example be of a duration of that ranges between 10-95 percent of the idle period, be of duration that ranges between 30-80 percent of the idle period, and the like).
Multiple illumination iterations may occur during a scanning of the region with an electron beam, for example, an illumination iteration may occur after each line of the region is scanned), or may occur during only some of the idle periods that occur during a scan of the region, for example, once per a first number (N1) of scan lines.
The time difference between adjacent illumination iterations may be determined by an operator of the scanning electron microscope, by a manufacturer of the scanning electron microscope, or any authorized person.
The time difference between adjacent illumination iterations may remain unchanged, or may be changed over time.
The time difference may be determined based on the charging state of sample. For example—a first region of the sample that is charged faster than a second region of the sample may require more frequent illumination iterations than the second region.
The time difference between adjacent illumination iterations may equal a product of multiplication between N1 and a time difference between the scanning of consecutive lines of the sample.
Non limiting examples of the value of N1 are four, five, six, seven, eight, nine, ten, fifteen, and more.
Discharging a region of the sample involve reducing the charging of the surface of the region. The reduction may discharge the entire charge or may reduce the charge without nullifying the charge.
The environment of the system includes a charged particle evaluation system 100. The charged particle evaluation system 100 uses charged particles to evaluate a sample.
The charged particle evaluation system may be (i) a defect review scanning electron microscope SEMVISION™ of APPLIED MATERIALS™ Inc. of San Jose, California, (ii) a metrology system such as the PROVision™ 3E Ebeam™ metrology system of APPLIED MATERIALS™, (iii) an electron beam inspection system such as the PRIMEVISION™ of APPLIED MATERIALS™, or (iv) a critical dimension scanning electron microscope such as the VERITYSEM™ of APPLIED MATERIALS™, and the like. The charge particle evaluation system may manufactured by vendors such as HITACHI™ of Tokyo, Japan, or KLA™ Corporation of Milpitas, California, or may be manufactured by other vendors.
According to one or more embodiments, system 10 includes illumination optics 20 that is configured to discharge the region by illuminating the region of the sample with one or more laser pulses during an illumination iteration.
System 10 also includes a timing circuit 30 that is configured to trigger the illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam.
The illumination optics 20 may include one or more additional optical components such as focusing lenses, collimators, polarization control elements, and the like.
The charged particle evaluation system 100 includes:
The column 110 includes electron optics such as electron beam source 112 and electron beam manipulation optics 114.
The electron beam manipulation optics 114 is configured to propagate the electron beam 321 through the column (for example while bypassing mirror 23) till exiting from the column.
The electron beam manipulation optics 114 may include deflection lenses, focusing lenses, electron beam collimating optics, electron beam shaping optics, and the like. Examples of a column 110 that includes multiple deflection coils for double-deflecting an electron beam are illustrated in U.S. Pat. No. 7,847,267 of Shemesh et al.
The optical axis 191 of the electron beam 190 is a vertical axis through which the electron beam propagated before the bypassing of the mirror and after the bypassing of the mirror.
The bypass magnetic scan coils 111 are configured to: (i) tilt the electron beam at a first direction, (ii) tilt the electron beam at an opposite direction such as to propagate along a secondary optical axis 192 that is parallel to the optical axis but spaced apart from the optical axis, (iii) tilt the electron beam at a second direction, towards the optical axis, and (iv) tilt the electron beam, at a direction opposing the second direction, such as to propagate along the optical axis. A system and method for double tilt is described at U.S. Pat. No. 6,674,075 of Petrov et al. and is incorporated herein by reference.
The charged particle evaluation system may also include a vacuum system (not shown) configured to maintain the column is maintained in vacuum, a high power supply unit (not shown) configured to provide high voltage signals to accelerate the electron beam and to decelerate the electron beam.
The sensing unit 130 also include one or more detectors. The one or more detectors may include secondary electron detectors, backscattered electron detectors. Detectors for detecting photons and additionally or alternatively x-rays may also be included in the charged particle evaluation system. Examples of a column 110 that includes multiple sensors are illustrated in U.S. Pat. No. 7,847,267 of Shemesh et al.
Any detector of the charged particle evaluation system may be located within the column or outside the column. A detector may include a single sensing segment, may include multiple sensing segments, may be a part of an array of sensors, and the like.
The sample 320 is supported and moved by a mechanical stage 333.
The timing circuit 30 includes one or more integrated circuits. In one embodiment the timing circuit is implemented by a Field Programmable Gate Array (FPGA). It should be noted that the timing circuit can be implemented by an Application Specific Integrated Circuit (ASIC), may be implemented by a hardware accelerator, by a central processing unit, by a microcontroller, and the like.
There may be multiple idle periods per a scanning period. A scanning period is a period during which the region is scanned.
The timing circuit may trigger one or more illumination iterations during the scanning period-especially during one or more idle periods of a scanning period. For example—the illumination iterations may be triggered once per N1 idle periods.
The timing circuit may trigger any illumination iteration based on one or more timing constraints. The one or more timing constraints may include at least one out of (a) a time difference between adjacent illumination iterations of the different illumination iterations—for example a time required to scan N1 lines of the region, (b) the timing of one or more idle periods, and the like.
A timing of an idle period may include at least one of a start of the idle period, the entire duration of the idle period, a part of the duration of the idle period, or an end of the idle period.
The charged particle evaluation system may include a field of view that includes a group of regions. Thus, the charged particle evaluation system may scan each one of the regions of the groups of regions by deflecting the electron beam, and without introduction of a mechanical movement between the sample and the column 110.
If the laser pulse illuminates the entire field of view (all regions of the group of regions), then the mirror 23 does not need to tuned to illuminate the specific region that is currently scanned by the electron beam, and the illumination optics may be fixed in the sense that they do not need to track the region that is currently being illuminated. In this case the mirror 23 may be a fixed mirror. Additionally or alternatively, the illumination optics do not need to have scanning or deflecting optics for directing the laser pulses onto a specific region within the field of view.
It may be beneficial to illuminate only a part of the field of view, for example, illuminating only the region that is being scanned, to provide more laser energy to the region and to speed the discharging of the region.
When only a part of the field of view is illuminated, the illumination optics may be adjustable and is configured to direct the light (laser pulses 195) only (or mostly) on a region that is scanned. In this case the mirror 23 may be a movable mirror (for example rotates about a rotation axis by an engine (not shown)) and additionally or alternatively the illumination optics may include other scanning or deflecting optics (such as not or more mirrors that are movable and additionally or alternatively rotatable in relation to each other) for directing the laser pulses onto a specific region within the field of view.
According to an embodiment of the disclosure, the timing circuit may generate timing signals during scan sessions and between scan sessions.
The timing signals generated by the timing circuit may include:
Assuming that an illumination iteration is required each time N1 are scanned-then the second period is N1 times longer than the first period.
According to an embodiment of the disclosure the timing circuit may synchronize the generation of the first timing signal and the second timing signals with each scan of a region.
According to an embodiment of the disclosure the timing circuit may generate the first timing signal and the second timing signals in an uninterrupted manner-even between one scan session to another. The uninterrupted generation of the first timing signal and the second timing signals may simplify the generation of the timing signals any may improve the lifespan of the laser.
When generating the first timing signal and the second timing signals in an uninterrupted manner (even between one scan session to another), the scan controller 122 may align the start of a scanning of the region with the first timing signal.
Assuming that N1 equals three, then two illumination iterations will occur during the scanning of region 231. The first illumination iteration may occur at either one of the first retrace period 242-1, the second retrace period 242-2 and the third retrace period 242-3. The second illumination iteration will occur three scan lines afterwards.
The various signals include control signals generated by the scan controller 122. The control signals may include:
The various signals also include second timing signal 212 that is generated by the timing circuit—and triggers an illumination iteration. The second timing signal is set only during idle periods in which an illumination iteration occurs, for example one per each N1 idle periods.
Timing diagram 200-3 also illustrates that the scan on signal 207 is aligned to the second timing signal 212.
The timing circuit 30 includes:
Method 600 may be executed by the timing circuit and also may be executed by the illumination optics illustrated in any one of
Method 600 may start by step 610 of triggering, by a timing circuit, an illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam. The triggering may follow a reception of a start scan command. The one or more timing constraints may include at least one out of (a) a time difference between adjacent illumination iterations of the different illumination iterations, for example a time required to scan N1 lines of the region, (b) the timing of one or more idle periods, and the like.
The triggering may include generating, by the timing circuit, a second timing signal and a third timing signal, both explained in the above text. The triggering is responsive to one or more variables such as N1 and Dii.
Step 610 may be followed by step 620 of discharging, by illumination optics, the region of the sample by illuminating the region of the sample with a light, such as a laser pulse, during the illumination iteration.
Steps 610 and 620 may be executed multiple times.
Method 600 may also include step 630 of aligning a scan on signal with a first timing signal generated by the timing circuit. The aligning may be responsive to variable Dss.
System 10′ does include a mirror (denoted 23 in
In
In
In
The timing circuit 30 is also located outside the vacuum chamber 334.
The charged particle evaluation system 100 of
In the foregoing specification, the embodiments of the disclosure have been described with reference to specific examples of embodiments. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the appended claims.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein may be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
Furthermore, the terms “assert” or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.
Any reference to the term “comprising” or “having” or “including” should be applied mutatis mutandis to “consisting” and additionally or alternatively should be applied mutatis mutandis to “consisting essentially of”.
Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Also, for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.
Also, for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to embodiments containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
While certain features of the embodiments have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
