Claims
- 1. A semiconductor device structure, the structure comprising:a substrate; a gate structure formed upon the substrate, the gate structure comprising a gate electrode having at least one sidewall, wherein at least one permanent spacer is formed on the at least one sidewall of the gate structure; and a disposable spacer formed upon the at least one permanent spacer, the disposable spacer comprising a germanium-silicon alloy, wherein the germanium-silicon alloy includes a first portion (x) of germanium and a second portion (1−x) of silicon, and further wherein x is greater than about 0.2.
- 2. The structure of claim 1, wherein the at least one PMOS device comprises at least one p-type region formed in the substrate adjacent the gate structure thereof, wherein the p-type region is offset from the gate structure by the disposable spacer.
- 3. The structure of claim 1, wherein the gate structure of the at least one NMOS device comprises at least one permanent spacer formed on at least one sidewall of a gate electrode, and further wherein the width of the at least one permanent spacer is optimized for implant offset of an n-type region in the substrate adjacent the gate structure of the at least one NMOS device.
- 4. An intermediate structure for use during offset implantation of regions of MOS devices, the intermediate structure comprising:a substrate; gate structures formed in relation to the substrate for both PMOS and NMOS devices, wherein each gate structure comprises a gate electrode comprising at least one sidewall, wherein at least one permanent spacer is formed on the at least one sidewall of each gate structure; and a disposable spacer formed upon the at least one permanent spacer of each gate structure, wherein the disposable spacer comprises a germanium-silicon alloy, wherein the germanium-silicon alloy comprises a first portion (x) of germanium and a second portion (1−x) of silicon, and further wherein x is greater than about 0.2.
- 5. The structure of claim 4, wherein x is greater than 0.7.
- 6. The structure of claim 5, wherein x is greater than 0.9.
- 7. The structure of claim 4, wherein each PMOS device comprises at least one p-type region formed in the substrate adjacent the gate structure thereof, wherein the p-type region is offset from the gate structure by a distance based on the width of the disposable spacer.
- 8. The structure of claim 4, wherein the width of the at least one permanent spacer of each gate structure is optimized for implant offset from a gate structure of an NMOS device.
Parent Case Info
This is a division of application Ser. No. 08/755,449, filed Nov. 22, 1996, (pending), which is incorporated herein by reference, now U.S. Pat. No. 6,087,239.
US Referenced Citations (15)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2 249 867 |
May 1992 |
GB |
Non-Patent Literature Citations (2)
Entry |
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