Patent Application
20230187342
The present invention generally relates to semiconductor devices, and more specifically, to improving semiconductor device fabrication using dopant-free inhibitors for area selective depositions for creating fully aligned vias (FAVs).
Integrated circuits commonly include electrically conductive microelectronic structures, known as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are usually formed by a lithographic process. Representatively, a photoresist layer can be spin coated over a dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask and then the exposed layer can be developed in order to form an opening in the photoresist layer. An opening for the via can be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. The via opening can be filled with one or more metals or other conductive materials to form a metal-filled via.
Embodiments of the present invention are directed to a method of forming a fully-aligned via (FAV) structure. A non-limiting example of the method includes arranging conductive material adjacent to a dielectric pad and chemically deactivating a surface of the conductive material by forming a dopant-free surface-aligned monolayer (SAM) thereon. Dielectric material is deposited onto the dielectric pad aside the dopant-free SAM and the dopant-free SAM is removed from the surface of the conductive material.
Embodiments of the present invention are directed to a method of forming a fully-aligned via (FAV) structure. A non-limiting example of the method includes arranging metal between dielectric pads, chemically deactivating a surface of the metal by forming a dopant-free surface-aligned monolayer (SAM) comprising hydroxamic acid thereon, depositing, by chemical vapor deposition (CVD), a low-k dielectric material onto the dielectric pads at opposite sides of the dopant-free SAM and removing the dopant-free SAM from the surface of the metal to form the FAV.
Embodiments of the invention are directed to a fully-aligned via (FAV) precursor structure. A non-limiting example of the FAV precursor structure includes conductive material arranged adjacent to a dielectric pad and a dopant-free surface-aligned monolayer (SAM) formed on a surface of the conductive material to chemically deactivate the surface of the conductive material.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.
In the accompanying figures and following detailed description of the disclosed embodiments, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, fully-aligned via (FAV) topography is often required at tight pitches to ensure sufficient margin between a contact, which is disposed in electrical contact with a first metallization interconnect, and a second metallization contact adjacent to the first metallization contact. Typically, FAV topography is achieved by metal recess processes. However, it has been found that metal recess processes tend to introduce relatively large variability in certain line properties (e.g., resistance and capacitance or RC-delays) due to non-uniformities in recess depths.
Selective dielectric deposition has therefore been developed as an alternative to metal recess processes. Selective dielectric deposition generally requires a self-aligned deposition of an inhibitor on a metallic surface followed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and is less susceptible to swings in RC-delays from variations in film thicknesses as metal recess processes.
A problem with selective dielectric deposition is that achieving an FAV topography requires selective deposition of dielectric on a dielectric. This necessitates a protection of the metal surface and only organic monolayers provide an acceptable level of selectivity for a desired thickness of surface topography introduced in a self-aligned manner (e.g., selective adhesion to a metal surface). Unfortunately, introductions of surface materials or solutions (?) demonstrated in the literature typically rely on either phosphonic or thiol for selective adhesion and metal surfaces are often sensitive to impurities. The sensitivity of metal surfaces to impurities, such as phosphorous and thiols, results in such phosphorous and thiols being materials that can be difficult to fully remove from the metal surfaces after a selective deposition process and may subsequently present reliability issues. Furthermore, residual inhibiting material may be present on interlayer dielectric (ILD) surfaces.
Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing for growth of a low-k silicon oxycarbide (SiCOH) selectively on top of a dielectric. Successfully growing one type of dielectric on top of another type of dielectric has great potential for a variety of semiconductor applications, including the creation of fully aligned vias (FAVs). One issue with such growth is lateral deposition, which impacts the implementation of thicker selective dielectric growth. Therefore, long chain self-assembled monolayers or surface aligned monolayers (SAMs) with stable cross-linking are employed. By using long chain cross-linking surface SAMs bonded to a conductive surface or region, lateral growth can be successfully inhibited. Polymerization can occur by thermal and ultraviolet (UV) cure. The polymerization process can be triggered by a number of stimuli, including temperature. In one instance, a temperature of about 80-100° C. can start this polymerization process, if it is in an inert environment. The removal of the long chain SAM results in the formation of a selective FAV structure.
The above-described aspects of the invention address the shortcomings of the prior art by providing for SAMs that are dopant-free inhibitors for selective depositions. The dopant-free inhibitors provide for short exposure times leading to high static water contact angles (1 minute=107°) and selectivity for metal surfaces. The dopant-free inhibitors exhibit increased acidity, which increases binding energies to metal surfaces, and are effective at blocking certain ALD processes.
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In accordance with one or more embodiments of the present invention, the conductive material 301 includes metal and the dopant-free SAM 401 is configured to resist formation of sulfuric, phosphoric and boric acids upon exposure to moisture which can then react with the metal of the conductive material 301. Thus, the dopant-free SAM 401 can include a head group lacking sulfur, phosphorous and boron. The dopant-free SAM 401 should also include a head group lacking flourine, chlorine and indium due to potential for corrosion with the metal of the conductive surface 303. In addition, the dopant-free SAM 401 should also include a head group lacking arsenic, aluminum and selenium, which are less reactive and more benign than the other potential dopants listed above, but which should still be avoided. In some cases, the dopant-free SAM 401 can include a head group that includes a carbon-flourine (C—F) group.
With the dopant-free SAM 401 provided without the dopants listed above (i.e., sulfur, phosphorous, boron, flourine, chlorine, indium, arsenic, aluminum and selenium and combinations thereof), the dopant-free SAM 401 offers certain advantages. Sulfur and phosphorous, in particular, can react readily with metal, especially in the presence of moisture to form sulfur-based and phosphoric-based acids that can subsequently degrade the metal and consequently degrade its resistance and stability during fabrication. Indeed, even if surface layers of sulfur and phosphorus can be removed, very small amounts of sulfur and phosphorous may remain in the metal after fabrication and even these small amounts can degrade the metal during operations. Providing the dopant-free SAM 401 avoids the possibility of even small amounts of such dopants to invade and degrade the metal of the conductive material 301.
As an example, the dopant-free SAM 401 can include hydroxamic acid. More generally, the dopant-free SAM 401 can be provided as a terminal n-hydroxamic acid in its head group and a long chain aliphatic compound with the following structure, which can produce a stable solution in 4-methyl-2-pentanol for example.
The use of hydroxamic acids and other similar compounds is helpful in forming the sought-after FAV. This is because hydroxamic acids can acts an inhibiting material that chemically deactivates the conductive surface 303 of the conductive material 301 for an area selective deposition of a dielectric material, such as a low-k dielectric material, during a CVD process.
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In accordance with embodiments, the additional SAMs 501 can have similar chemical structures as the dopant-free SAM 401. Alternatively, the additional SAMs 501 can have unique or progressively unique chemical structures. For example, a first layer 5021 of the stack 502 above the dopant-free SAM 401 can include some dopants which are less reactive and slightly more benign than phosphorous and sulfur, such as arsenic, aluminum and selenium, and a second layer 5022 of the stack 502 above the first layer 5021 can include dopants, such as phosphorous and sulfur, because these dopants will not touch or otherwise come into contact with the metal of the conductive material 301.
The following description will relate to those cases where additional SAMs 501 are deposited onto the dopant-free SAM 401 to form the stack 502. In these cases, the additional SAMs 501 can have variable chemical structures.
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In accordance with embodiments, the first and second dielectric pads 302 can be formed of an interlayer dielectric (ILD), such as ultra low-k SiCOH or other similar materials, and the dielectric material deposited into the first and second dielectric pads 302 can be formed of SiCOH, low-k SiCOH or other similar materials.
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Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The phrase “selective to,” such as, for example, “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.
The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases can be controlled and the system parameters can be set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. An epitaxially grown semiconductor material can have substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface can take on a {100} orientation. In some embodiments of the invention, epitaxial growth and/or deposition processes can be selective to forming on semiconductor surface, and cannot deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.
As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
The flowchart and block diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
