Patent Application
20240071913
The present disclosure relates to integrated circuits, and more particularly, to interconnect features.
Memory of an integrated circuit is sometimes embedded within the interconnect structure of the integrated circuit. Example such memories include dynamic random access memory (DRAM) and static random access memory (SRAM), both of which can persistently store data while power is applied. While such memories can be configured differently (e.g., DRAM cells may be implemented with a transistor and capacitor and rely on refresh circuitry, while SRAM cells include six transistors and need no refresh circuit), they include the use of word lines and bit lines. For example, in one configuration, each SRAM bit cell consists of six transistors (a 6T configuration). In such a 6T configuration, four of the transistors are arranged to form a bistable latch. The bistable latch is capable of assuming one of two stable states—either a high-resistance state which may be representative of an ‘off’ or ‘0’ state, or a low-resistance state which may be representative of an ‘on’ or ‘1’ state. Each of these states corresponds to a logic value (0 or 1) of the bit of data stored in the SRAM bit cell. Further, the remaining two transistors are coupled to the latch to provide switchable access to the latch as may be used during read and write operations involving the SRAM bit cell. These access transistors are coupled to a word line and two bit lines. The word line controls the access transistors, causing them to couple the bit lines to the latch during read and write operations and to decouple the bit lines from the latch at other times. During a read or write operation involving SRAM, the bit lines are pre-charged to a state appropriate to implement the read or write operation, and the word line is activated (i.e., pulsed) to couple the latch to the bit lines for a duration of time. During a read operation, when the word line is activated the bit lines discharge to a voltage proportional to the state of the latch. A sense amplifier coupled to the bit lines detects the change in voltage on the bit lines and amplifies the change to a data signal having a value of 0 or 1. This data signal is stored in a buffer and/or provided to an output bus.
There remain a number of non-trivial issues with respect to interconnect structures having memory embedded therein.
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. Likewise, while the thickness of a given first layer may appear to be similar in thickness to a second layer, in actuality that first layer may be much thinner or thicker than the second layer; same goes for other layer or feature dimensions.
Techniques are provided herein to form an integrated circuit comprising a double-decked vertical stack of interconnect features. For example, the double-decked vertical stack of interconnect features comprises a lower interconnect feature and an upper interconnect feature, where the lower and upper interconnect features extend within a single interconnect layer. In an example, the lower and upper interconnect features extend between a lower etch stop layer and an upper etch stop layer. In an example, the lower interconnect feature is made relatively wider, e.g., to reduce ohmic resistance of the stack. In contrast, another relatively narrow (e.g., narrower than the lower interconnect feature) laterally adjacent single interconnect feature (e.g., laterally adjacent to the stack) extends through the interconnect layer, and extends between the lower etch stop layer and the upper etch stop layer. The single interconnect feature may be made narrower, e.g., which increases its ohmic resistance, but reduces the capacitance. The relatively narrow single interconnect feature may be used for transmission of logic signals (such as for word lines and/or VCC of a memory cell) that can withstand relatively high ohmic resistance but that prefer lower capacitance. On the other hand, the vertical stack of the lower and upper interconnect features (with at least the lower interconnect feature being relatively wide) may be used for power and/or analog signals (such as for bit lines and/or bit line bar signals of a memory cell) that prefer lower resistance.
In one embodiment, an integrated circuit structure comprises a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth and fifth interconnect features within the second interconnect layer.
In another embodiment, an integrated circuit structure comprises an upper etch stop layer, and a lower etch stop layer below the upper etch stop layer. The upper and lower etch stop layers effectively define the top and bottom surfaces of one interconnect layer of an overall interconnect structure including one or more additional interconnect layers. Each of the upper and lower etch stop layer comprises corresponding dielectric materials. In an example, a first interconnect feature extends from the lower etch stop layer to the upper etch stop layer. In an example, a vertical stack of a second interconnect feature and a third interconnect feature extends from the lower etch stop layer to the upper etch stop layer. For example, the second interconnect feature extends from the lower etch stop layer, the third interconnect feature extends from the upper etch stop layer, and an upper surface of the second interconnect feature and a lower surface of the third interconnect feature makes contact at a plane between the upper and lower etch stop layers.
In yet another embodiment, an integrated circuit structure comprises a vertical stack of a lower interconnect feature, an intermediate interconnect feature, and an upper interconnect feature. For example, in the vertical stack, a lower surface of the intermediate interconnect feature is on an upper surface of the lower interconnect feature, and a lower surface of the upper interconnect feature is on an upper surface of the intermediate interconnect feature. In an example, the intermediate interconnect feature comprises (i) conductive fill material, (ii) a first section of a layer comprising conductive material on side surfaces of the conductive fill material, and (iii) a second section of the layer comprising conductive material on a bottom surface of the conductive fill material. In an example, a thickness of the first section of the layer is at least 0.75 nanometer (nm), or at least 1 nm more than a thickness of the second section of the layer. Numerous configurations and variations will be apparent in light of this disclosure.
General Overview
As noted above, there remain a number of non-trivial issues with respect to interconnect structures having memory embedded therein. Consider, for instance, the competing interests of word lines and bit lines. In more detail, logic signals such as word line signals of a memory cell may be able to withstand higher ohmic resistance, but prefer a lower capacitance path to achieve sufficient access speed. So, for example, a word line may benefit from the relatively low parasitic capacitance attributable to a short height and not be excessively encumbered due to the higher resistance attributable to a narrow width. In contrast, power signals such as bit line signals of a memory cell may be able to withstand higher capacitance, but prefer a lower resistance path to achieve less power consumption. So, for example, a bit line may benefit from the relatively low resistance attributable to a tall and wide configuration and not be excessively encumbered due to the attendant higher parasitic capacitance. Thus, there are conflicting requirements of height and width of various interconnect features.
Accordingly, techniques are provided herein to address the competing interests of embedded memory interconnect features. In an example, an integrated circuit (IC) is configured to simultaneously (i) provide shorter and narrower paths for a first type of signals (e.g., logic signals such as word line signals) thereby providing relatively low capacitance paths for the first type of signals, and (ii) provide taller and wider paths for a second type of signals (e.g., power signals such as bit line signals) thereby providing relatively low resistance paths for the second type of signals. For example, within an upper interconnect layer (e.g., interconnect layer 136, see
In an example, a lower interconnect layer (e.g., interconnect layer 132 of
In an example, the upper interconnect layer includes (i) a second narrow interconnect feature (e.g., interconnect feature 112a, see
Thus, the first type of signal is transmitted through the first narrow interconnect feature and the second narrow interconnect feature, whereas the second type of signal is transmitted through the first wide interconnect feature, the second wide interconnect feature, and the third narrow interconnect feature. Note that a height of the second narrow interconnect feature is h1, whereas a height of the second wide interconnect feature is h2 (see
Because the first wide interconnect feature and the second wide interconnect feature forms a combined wide and tall interconnect feature, an ohmic resistance of this combined wide and tall interconnect feature is relatively less, which provides a relatively low resistance path for the second type of signal. On the other hand, the first narrow interconnect feature and the second narrow interconnect feature provides a relatively high resistance, but low capacitance, path for the first type of signal. Note that because the first narrow interconnect feature (which may be a narrow conductive line, see
In one embodiment, each of the above discussed interconnect features comprise conductive fill material, and conductive barrier or liner layer on sidewalls and/or bottom surface of the conductive fill material. In an example, the conductive fill material of an interconnect feature tends to diffuse within adjacent dielectric material. The barrier or liner layers, in an example, prevent or reduce diffusion of the conductive fill material of an interconnect feature to adjacent dielectric material. In another example, the barrier or liner layers of an interconnect feature facilitate better adhesion of the conductive fill material on walls of the interconnect feature.
In an example, a section of the barrier layer on a bottom surface of the above discussed second wide interconnect feature is made relatively thin, e.g., thinner than another section of the barrier layer of side surfaces of the second wide interconnect feature. Thus, the relatively thick section of the barrier layer of side surfaces of the second wide interconnect feature prevents, or otherwise reduces, diffusion of the conductive fill material to adjacent dielectric material. The relatively thin section of the barrier layer of the bottom surface of the second wide interconnect feature ensures that the resistance between the first wide and second wide interconnect features are relatively low. Thus, the previously discussed combined wide interconnect feature (which is a combination of the first wide and second wide interconnect features) is relatively low. Example materials and widths of the barrier layers have been discussed herein below in further detail.
In an example, the varying thickness of the barrier layer of the second wide interconnect feature may be achieved through a selective deposition process. For example, after a recess (e.g., recess 316a, see
As previously discussed herein, the third narrow interconnect feature (which may be a conductive via) is above, and in contact with, the second wide interconnect feature (which may be a conductive line). In an example, when forming the third narrow interconnect feature, a recess etching process (where the third narrow interconnect feature is to be formed within the recess, such as recess 320a of
In an example, to form the structure discussed herein above, the lower interconnect layer comprising the first wide and first narrow interconnect features are formed. Note that while the above discussion focuses on some example wide and narrow interconnect features, the structure may include several such wide and narrow interconnect feature. Subsequently, an etch stop layer is deposited above the lower interconnect layer. Then a bottom section of dielectric material of the upper interconnect layer is deposited, where the bottom section of dielectric material of the upper interconnect layer has a height of h2 (see
Subsequently, additional dielectric material of the upper interconnect layer is deposited, such that the height of the dielectric material is now h1, see
The use of “group IV semiconductor material” (or “group IV material” or generally, “IV”) herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and so forth. The use of “group III-V semiconductor material” (or “group III-V material” or generally, “III-V”) herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example.
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the material has an element that is not in the other material.
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For example, in some embodiments, such tools may be used to detect (i) a lower interconnect layer (e.g., which may be a lower metallization level) comprising one or more lower narrow interconnect features and one or more lower wide interconnect features, and (ii) an upper interconnect layer comprising one or more upper narrow interconnect features and one or more upper wide interconnect features. For example, a first upper narrow interconnect feature may be formed above a first lower narrow interconnect feature, where the vertical stack of the first lower narrow interconnect feature and the first upper narrow interconnect feature is used to transmit a first type of signal. An upper wide interconnect feature may be formed above a lower wide interconnect feature, and a second upper narrow interconnect feature may be formed above the upper wide interconnect feature. In an example, the vertical stack of the lower wide interconnect feature, the upper wide interconnect feature, and the second upper narrow interconnect feature is used to transmit a second type of signal. In an example, the upper wide interconnect feature forms a mid-level or double-decked metallization level for the second type of signal, where the signal path for the first type of signal lacks the mid-level or double-decked metallization level. In an example, such tools may also be used to detect the upper wide interconnect feature having (i) relatively thick section of the barrier layer on side surfaces, (ii) relatively thin section of the barrier layer on a bottom surface, and (iii) relatively thick capping layer on an upper surface. Numerous configurations and variations will be apparent in light of this disclosure.
Architecture
As illustrated, the structure 100 comprises the lower interconnect layer 132, and the upper interconnect layer 136 above the lower interconnect layer 132. An etch stop layer 133 is between the upper and lower interconnect layers 132, 136. Another etch stop layer 137 is above the upper interconnect layer 136. In an example, each etch stop layer acts to stop an etch process occurring in an interconnect layer above the etch stop layer. For example, the etch stop layer 133 stops an etch process occurring through a dielectric material 134 of the interconnect layer 136 (e.g., the etch stop layer 133 stops the etch process to form the recesses 312 and 320, see
The lower interconnect layer 132 comprises dielectric material 130, and a plurality of interconnect features 104a, 108a, 104b, 108b, and 104c extending through the dielectric material 130. Note that a number and/or location of the various interconnect features illustrated in
Each interconnect feature comprises conductive fill material (e.g., one or more metals and/or alloys thereof) and one or more barrier or liner layers at least in part around the conductive fill material. For example, the conductive fill material of an interconnect feature tends to diffuse within adjacent dielectric material. In an example where the conductive fill material is copper, the diffusion may result in formation of undesirable copper oxide. The barrier or liner layers, in an example, prevent or reduce diffusion of the conductive fill material of an interconnect feature to adjacent dielectric material of the corresponding interconnect layer. In another example, the barrier or liner layers of an interconnect feature facilitate better adhesion of the conductive fill material on walls of the interconnect feature.
For example, the interconnect feature 104a comprises conductive fill material 102a (also referred to herein simply as conductive material 102a) and barrier layer 103a; the interconnect feature 108a comprises conductive material 106a and barrier layer 107a; the interconnect feature 104b comprises conductive material 102b and barrier layer 103b; the interconnect feature 108b comprises conductive material 106b and barrier layer 107b; and the interconnect feature 104c comprises conductive material 102c and barrier layer 103c. As illustrated, for each of the interconnect features of the lower interconnect layer 132, the corresponding barrier layers are on sidewalls and on a bottom surface of the interconnect feature. Suitable materials for the barrier layers (which may also be referred to herein as liner layers) of the various interconnect features include barrier layer refractory metals and alloys, cobalt, cobalt-nickel (CoNi), ruthenium-cobalt combination, molybdenum, nickel, manganese, titanium-tungsten (Ti), tantalum (Ta), tantalum-nitride (TaN), tantalum-silicon-nitride (TaSiN), titanium-nitride (TiN), titanium-silicon-nitride (TiSiN), tungsten (XV), tungsten-nitride (WN), tungsten-silicon-nitride (WiSiN), and/or combinations of such materials (e.g., a multi-lay stack of Ta/TaN). In an example, the conductive fill materials of the various interconnect features comprises suitable conductive materials such as pure copper, ruthenium, molybdenum, tungsten, aluminum, an alloy such as copper-tin (CuSn), copper indium (CuIn), copper-antimony (CuSb), copper-bismuth (CuBi), copper-rhenium (CuRe), and/or any other suitable conductive material.
As illustrated, the interconnect features 102a, 102b, 102c have substantially a same width w5, where the width w5 is measured in a horizontal direction that is perpendicular to an imaginary vertical line passing through the interconnect features 108a, 116a, and 120a. For example, the widths of each of the interconnect features 102a, 102b, 102c is within 0.5 nm or 1 nm of the width w5.
Note that in an example, at least some of the interconnect features is tapered towards the bottom. For example, a width of a lower section of an interconnect feature is less than a width of an upper section of the interconnect feature. The tapering may be due to formation of recesses (e.g., within which the interconnect features are to be eventually formed) from a top-side or front side of the structure. In some other examples, the interconnect features may not be tapered. In an example, due to the tapering, the horizontal width of an interconnect feature (such as interconnect feature 104a) may vary along a vertical length of the interconnect feature. Accordingly, the width of an interconnect feature (such as width w5) is an average width and/or is measured about half-way along the vertical length of the interconnect feature.
As illustrated, the interconnect features 108a, 108b have substantially a same width w6, where the width w6 is measured in a horizontal direction that is perpendicular to an imaginary vertical line passing through the interconnect features 108a, 116a, and 120a. For example, the widths of each of the interconnect features 108a, 108b is within 0.5 nm or 1 nm of the width w6. Similar to the discussion with respect to the width w5, the width w6 of the interconnect feature 108a is an average width, e.g., measured about half-way along the vertical length of the interconnect feature 108a.
In an example, the width w6 is greater than the width w5, as illustrated. For example, the width w6 is at least 1 nm, or at least 2 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm greater than the width w5. In an example, the width w6 is in the range of 20 nm to 40 nm, or in the subrange of 20-36 nm, or 20-30 nm, or 20-25 nm, or 26-40 nm, or 26-36 nm, or 26-32 nm, or another appropriate subrange thereof. In an example, the width w5 is in the range of 8 nm to 25 nm, or in the subrange of 8-20 nm, or 8-12 nm, or 15-25 nm, or 15-20 nm, or another appropriate subrange thereof. In an example, width w6 is at least 5%, or at least 10%, or at least 15%, or at least 20%, or at least 25% greater than the width w5.
In an example, signals that demand relatively low resistance are transmitted through one or both the interconnect features 108a, 108b, and signals that can tolerate relatively high resistance are transmitted through one or more of the interconnect features 104a, 104b, 104c. For example, the interconnect features 104a, 104b, 104c having the narrow width w5 may be used for communicating logic signals, and the interconnect features 106a, 106b having the wide width w6 may be used for communicating analog signals and/or power signals. For example, in the context of a memory array, one or more of the narrower interconnect features 104a, 104b, 104c are used to transmit word line (WL) signals and/or memory VCC signal, whereas one or more of the wider interconnect features 108a, 108b are used to transmit bit line (BL) and/or bit line bar (BLB) signals. For example,
Referring to
Note that
Referring again to
For example, the interconnect feature 112a comprises conductive material 110a, and barrier layer 111a on sidewalls and bottom surface of the conductive material 110a; the interconnect feature 120a comprises conductive material 118a, and barrier layer 119a on sidewalls and bottom surface of the conductive material 118a; the interconnect feature 112b comprises conductive material 110b, and barrier layer 112b on sidewalls and bottom surface of the conductive material 110b; the interconnect feature 120b comprises conductive material 118b, and barrier layer 119b on sidewalls and bottom surface of the conductive material 118b; and the interconnect feature 112c comprises conductive material 110c, and barrier layer 111c on sidewalls and bottom surface of the conductive material 110c. Example composition of each of the conductive materials and barrier layers for various interconnect features have been discussed herein above with respect to the interconnect features of the lower interconnect layer 132.
In an example, a width of each barrier layer of the interconnect features 112a, 112b, 112c, 120a, and 120b is substantially the same, e.g., within 0.5 nm or 1 nm of each other. In an example, the width of each barrier layer of the interconnect features 112a, 112b, 112c, 120a, and 120b is substantially equal to the above discussed width w1.
In one embodiment, the interconnect feature 116a comprises conductive material 114a, section 115al of a barrier layer on sidewalls of the conductive material 114a, section 115a2 of the barrier layer on bottom surface of the conductive material 114a, and a capping layer 115a3 on a top surface of the conductive material 114a, as illustrated in
Similarly, the interconnect feature 116b comprises conductive material 114b, section 115b1 of a barrier layer on sidewalls of the conductive material 114b, section 115b2 of the barrier layer on bottom surface of the conductive material 114b, and a capping layer 115b3 on a top surface of the conductive material 114b, as also illustrated in
In an example, the interconnect features 116a and 116b have similar shape and dimensions. Various features and dimensions of the interconnect feature 116a are discussed herein below, and such discussion also applies to the interconnect feature 116b.
As illustrated, the interconnect features 108a, 116a, and 120a form a vertical stack of interconnect features. A vertical stack of interconnect features 116a and 120a extends between the etch stop layer 133 and the etch stop layer 137 (note that the interconnect feature 116a extends through the etch stop layer 133, to contact the upper surface of the interconnect feature 108a). The interconnect features 116a and 120a makes contact at a plane between the two etch stop layers 133, 137. The interconnect features 116b, 120b have similar configuration. Also, each of the interconnect features 112a, 112b, 112c extends from the lower etch stop layer 133 to the upper etch stop layer 137. As illustrated, each of the interconnect features 112a, 112b, 112c extends through the lower etch stop layer 133, to respectively make contact with the interconnect features 104a, 104b, 104c.
As illustrated, the upper surfaces of the interconnect features 104a, 108a, 104b, 108b, 104c are substantially coplanar (e.g., vertically separated by at most 0.5 nm, or at most 1 nm, or at most 1.5 nm). For example, at least a section of the upper surface of the any of the interconnect features of the interconnect layer 132 is within a first horizontal plane, at least a section of the upper surface of another interconnect feature of the interconnect layer 132 is within a second horizontal plane, and wherein the first and second horizontal planes are vertically separated by at most 0.5 nm, or at most 1 nm, or at most 1.5 nm.
As illustrated, the upper surfaces of the interconnect features 112a, 120a, 112b, 120b, 112c are substantially coplanar (e.g., vertically separated by at most 0.5 nm, or at most 1 nm, or at most 1.5 nm). For example, at least a section of the upper surface of the any of the interconnect features of the interconnect layer 136 is within a third horizontal plane, at least a section of the upper surface of another interconnect feature of the interconnect layer 136 is within a fourth horizontal plane, and wherein the third and fourth horizontal planes are vertically separated by at most 0.5 nm, or at most 1 nm, or at most 1.5 nm. In one embodiment, a lateral separation between two laterally adjacent interconnect features (e.g., lateral distance between the interconnect features 104a and 108a, or lateral distance between the interconnect features 112a and 116a) is at most 30 nm, or at least 50 nm, or at least 80 nm, or at least 100 nm, or at least 150 nm, or at least 200 nm, or at least 300 nm, or at least 400 nm.
As illustrated, a height of each of the interconnect features 112a, 112b, 112c is substantially equal to (e.g., within 0.5 nm, or 1 nm) of a sum of heights of the interconnect features 116a, 120a (or interconnect features 116b, 120b). In an example, a height of each of the interconnect features 112a, 112b, 112c is h1, and a height of each of the interconnect features 116a, 116b is h2 (height h2 is labelled in
As discussed herein above, the interconnect feature 116a comprises a section 115al of a barrier layer on sidewalls of the conductive material 114a and another section 115a2 of the barrier layer on bottom surface of the conductive material 114a. In an example, the sections 115al and 115a2 of the barrier layer have different widths or thicknesses. For example, as illustrated in
In an example, the section 115al of the barrier layer on sidewalls of the interconnect feature 116a prevents, or reduces diffusion of the conductive material 114a within the adjacent dielectric material 134. On the other hand, the section 115a2 of the barrier layer is between the conductive materials 114a and 106a of the interconnect features 116a and 108a, respectively. Although the section 115a2 comprises conductive material, a relatively thick section 115a2 may increase an ohmic resistance between the conductive materials 114a and 106a. Accordingly, the section 115a2 is made relatively thinner (e.g., compared to the section 115a1), so as to reduce the ohmic resistance between the interconnect features 116a and 108a. Formation of the relatively thick section 115al and relatively thin section 115a2 of the barrier layer will be discussed herein below in further detail with respect to
In an example, a section 115b1 of a barrier layer of sidewalls of the interconnect feature 116b similarly has a width of w2 and a section 115b2 of the barrier layer on bottom surface of the interconnect feature 116b similarly has a width of w3, where the widths w2 and w3 have been discussed herein above with respect to the interconnect feature 116a.
In one embodiment, the interconnect feature 116a comprises the capping layer 115a3 and the interconnect feature 116b comprises the capping layer 115b3. In an example, each of the capping layers 115a3 and 115b3 has a maximum vertical height (which is also a maximum thickness) of w7 (thickness w7 is labelled for the capping layer 115a3 in
Also illustrated in
Referring now to
On the other hand, there are two (or can be even more, such as three or four) decks or levels of interconnect features between an interconnect feature 108 and the upper surface of the interconnect layer 136. For example, the interconnect feature 116a extends from an upper surface of the interconnect feature 108a to a plane that is lower than the upper surface of the interconnect layer 136, and the interconnect feature 120a extends from an upper surface of the interconnect feature 116a to the upper surface of the interconnect layer 136. Similarly, the interconnect feature 116b extends from an upper surface of the interconnect feature 108b to the plane that is lower than the upper surface of the interconnect layer 136, and the interconnect feature 120b extends from an upper surface of the interconnect feature 116b to the upper surface of the interconnect layer 136.
The wider interconnect features 108 and 116 offers lower resistance paths for some signals (e.g., BL and BLB, see
In an example, the interconnect features 104a, 108a, 104b, 108b, 104c form a lower or M0 metallization level of the structure 100. Note that “M0” implies a lowest metallization level in an example, but in another example, there may be further metallization levels below the M0 metallization level.
In an example, the interconnect features 116a and 116b may be considered as a metallization level for the interconnect features 108a, 108b, respectively. The metallization level comprising the interconnect features 116a, 116b may be referred to as an MD0 metallization level (where “M” stands for metallization level, “D” stands for “double-deck”, and “0” stands for a double-decked 0th metallization level).
As illustrated, the MD0 metallization level is for the wider interconnect features 108a, 108b. The interconnect features 104a, 104b, 104c lack any such metallization level.
Adding the MD0 metallization level and using wider interconnect features 108, 116 results in low resistance paths for some signals (e.g., BL and BLB, see
In an example, the interconnect layer 138 forms M1 metallization level of the structure 100. Thus, for example, the interconnect feature 112a couples the interconnect feature 104a of the M0 metallization level to the interconnect feature 142 of the M1 metallization level. On the other hand, the interconnect feature 120a couples the interconnect feature 116a of the MD0 metallization level to another interconnect feature (not illustrated in
Referring to
The method 300 then proceeds from 304 to 308, where the etch stop layer 133 and dielectric material 134 are deposited above the interconnect layer 132, e.g., as illustrated in
The method 300 then proceeds from 308 to 312, where interconnect features 116a, 116b are formed within the recesses 316a, 316b, respectively, e.g., as illustrated in
In an example, the sections 115al and 115a2 are deposited on side and bottom surfaces, respectively, of the recess 316a using any appropriate deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE), for example. In one example, a selective deposition technique is used, which deposits a relatively thicker section 115al on sidewalls of the recess 316a and relatively thinner section 115a2 on bottom surface of the recess 316a. Example thicknesses of these sections have been discussed herein previously with respect to
Subsequent to formation of the barrier layers, the conductive fill materials 114a and 114b are respectively deposited within the recesses 316a, 316b using any appropriate deposition techniques, such as electroplating, CVD, PVD, ALD, VPE, MBE, or LPE, for example. After that, the capping layers 115a3 and 115b3 are respectively formed for the interconnect features 116a, 116b, as illustrated in
The method 300 then proceeds from 312 to 316, where additional dielectric material 134 is deposited above the previously deposited dielectric material 134, such that the height of the dielectric material 134 is now h1, e.g., as illustrated in
The method 300 then proceeds from 316 to 320, where recesses 312a, 320a, 312b, 320b, 312c are formed within the dielectric material 134 (see
The method 300 then proceeds from 320 to 324, where interconnect features 112a, 120a, 112b, 120b, 112c are respectively formed within the recesses 312a, 320a, 312b, 320b, 312c, as illustrated in
The method 300 then proceeds from 324 to 328, where etch stop layer 137 is formed above the interconnect layer 136, and the interconnect layer 138 (e.g., comprising the interconnect feature 142 and one or more other interconnect features not illustrated in
Note that the processes in method 300 are shown in a particular order for ease of description. However, one or more of the processes may be performed in a different order or may not be performed at all (and thus be optional), in accordance with some embodiments. Numerous variations on method 300 and the techniques described herein will be apparent in light of this disclosure.
Example System
Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
The foregoing description of example embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.
