Claims
- 1. A depletion type DMOSFET device comprising a silicon wafer including a reverse size zone having a high impurity concentration and a top side zone having a low impurity concentration, a diffusion region in a surface area of said top side zone of said wager including well regions of a different conductivity type from the wager and source regions of the same conductivity type as the wafer, an insulating layer on said top size zone except for central area of said diffusion regions, said insulating layer outside said well regions on the wafer being thicker than that on the well regions, channel regions in a top surface area of said well regions and between said source regions and said top side zone, said channel regions being relatively lower in the carrier concentration than other parts in the well regions, gate electrodes above said channel regions with gate oxide layers interposed between said gate electrodes and said channel regions, source electrodes on said well regions and source regions, and a drain electrode on said reverse side high impurity concentration zone of the wafer.
- 2. A depletion type DMOSFET device comprising:
- a silicon wafer including a first layer of high impurity concentration and a second layer, formed in an adjacent parallel plane, with a low impurity concentration;
- a diffusion region in a surface area of said second layer of said wafer including well regions of a conductivity type different from said wafer and source regions of the same conductivity type as said wafer;
- an insulating layer provided on a side of said second layer opposite to said first layer, said insulating layer omitted at a central area of said diffusion region, and being thicker outside said well regions than on the well regions;
- channel regions defined in said second layer adjacent said well regions and between said source regions, said channel regions being relatively lower in carrier concentration than other parts of said well regions;
- gate electrodes formed above said channel regions with gate oxide layers interposed between said gate electrodes and said channel regions;
- source electrodes provided on said well regions and source regions; and
- a drain electrode provided on a side of said first layer opposite to said second layer of said wafer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-8993 |
Jan 1988 |
JPX |
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Parent Case Info
This application is a divisional, of application Ser. No. 07/294,787, filed Jan. 9, 1989 U.S. Pat. No. 4,902,630.
US Referenced Citations (13)
Foreign Referenced Citations (5)
Number |
Date |
Country |
55-50661 |
Apr 1980 |
JPX |
57-42164 |
Mar 1982 |
JPX |
59-231860 |
Dec 1984 |
JPX |
62-150769 |
Jul 1987 |
JPX |
8202981 |
Sep 1982 |
WOX |
Non-Patent Literature Citations (3)
Entry |
Article: New Channel-Doping Technique for High-Voltage Depletion Mode Power Mosfet's, Ueda et al. (s/86) pp. 311.varies.312. |
Article:Tradeoff Between Threshold Voltge & Breakdown in High-Voltage Double-Diffused Transistors, M. D. Pocha et al. (11/78) pp. 1325-1327. |
Article: Depletion-mode MOSFETS Open a Channel-in Power Switching, M. Alexander et al. (6/1984) pp. 281-285. |
Divisions (1)
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Number |
Date |
Country |
Parent |
294787 |
Jan 1989 |
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