Patent Application
20220238413
The present application relates to a double sided cooling module. More specifically, the present disclosure relates to a double sided cooling module that includes two or more power transistor submodules.
Conventional double sided cooling (DSC) modules can only be electrically tested after a full assembly. This is a problem, for example with MOSFETs such as Silicon Carbide (SiC) MOSFETs, because a number of SiC MOSFETs must be connected in parallel within a DSC module in order to achieve a required switching current rating. If electrical testing is performed on the DSC module and some of the SiC MOSFETs within the DSC module cause the DSC module to fail the electrical test, the DSC module is rejected. Rejecting a DSC module that includes SiC MOSFETs that individually pass the electrical test can significantly reduce the overall yield of the DSC modules being tested. Furthermore, because SiC MOSFETs are relatively expensive to manufacture compared to other types of MOSFETs, additional costs are incurred because the SiC MOSFETs that individually pass the electrical test cannot be reused. Another problem with conventional DSC modules is that all parts, including the SiC MOSFETs used in the DSC module, have to be designed specifically for the power class or required switching current rating that the DSC modules are intended to be used for. This can significantly increase the cost of the DSC module.
For these and other reasons, there is a need for the present invention.
According to an embodiment of a submodule for a double sided cooling module, the submodule includes a Direct Copper Bonded (DCB) substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer. The top metal layer has a first side, a second side and a center equidistant from the first side and the second side in a direction parallel with a plane of the top metal layer. The DCB substrate includes a spaced-apart row of first wires that each have a top end and a bottom end, where the bottom end of each of the first wires is attached to the top metal layer proximate to the first side of the top metal layer. The first wires extend in an upward direction from the first metal layer. A semiconductor die includes a top side load path contact, a top side control contact and a bottom side load path contact. The bottom side load path contact is attached to a top surface of a die pad portion of the top metal layer, and the top side control contact is electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer that is electrically isolated from the die pad portion. At least one of the first wires is attached to the control pad portion of the top metal layer, and other ones of the first wires are attached to the die pad portion of the top metal layer. An electrically conductive and thermally conductive spacer is over the semiconductor die and is attached to the top side load path contact of the semiconductor die. The top end of the first wires have a height perpendicular to the plane of the first metal layer that is greater than a height of a top side of the spacer from the plane of the first metal layer.
According to an embodiment of a double sided cooling module, the double sided cooling module includes a leadframe with a top Direct Copper Bonded (DCB) substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer. The leadframe is attached to the bottom metal layer. The double sided cooling module includes two or more power transistor submodules. Each one of the power transistor submodules includes a bottom DCB substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer. The top metal layer of the bottom DCB substrate has a first side, a second side and a center equidistant from the first side and the second side in a direction parallel with a plane of the top metal layer of the bottom DCB substrate. Each one of the power transistor submodules includes a spaced-apart row of first wires that each have a top end and a bottom end, where the bottom end of each of the first wires is attached to the top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer of the bottom DCB substrate. Each one of the power transistor submodules includes a semiconductor die that includes a top side load path contact, a top side control contact and a bottom side load path contact. The bottom side load path contact is attached to a top surface of a die pad portion of the top metal layer of the bottom DCB substrate, and the top side control contact electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer of the bottom DCB substrate that is electrically isolated from the die pad portion. At least one of the first wires is attached to the control pad portion of the top metal layer of the bottom DCB substrate and to the bottom metal layer of the top DCB substrate to conductively couple the top side control contact to the bottom metal layer of the top DCB substrate. Other ones of the first wires are attached to the die pad portion of the top metal layer of the bottom DCB substrate and to the bottom metal layer of the top DCB substrate to electrically couple the bottom side load path contact to the bottom metal layer of the top DCB substrate. An electrically conductive and thermally conductive spacer is over the semiconductor die and is attached to the top side load path contact of the semiconductor die. The spacer conductive couples the top side load path contact to the bottom metal layer of the top DCB substrate.
According to an embodiment of a method of forming a submodule, the method includes providing a Direct Copper Bonded (DCB) substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer. The top metal layer has a first side, a second side and a center equidistant from the first side and the second side in a direction parallel with a plane of the top metal layer. The top metal layer includes a die pad portion and a control pad portion that is electrically isolated from the die pad portion, where the control pad portion is proximate to the first side of the top metal layer. The method includes placing a first solder preform layer on a top surface of the die pad portion of the top metal layer. The method includes placing a semiconductor die on a top surface of the first solder preform layer, where the semiconductor die includes a top side load path contact, a top side control contact and a bottom side load path contact. The method includes placing a second solder preform layer on a top surface of the top side load path contact of the semiconductor die. The method includes placing an electrically conductive and thermally conductive spacer over the second solder preform layer. The method includes reflowing the first solder preform layer and the second solder preform layer to attach the bottom side load path contact of the semiconductor die to the die pad portion of the top metal layer and to attach the spacer to the top side load path contact of the semiconductor die. The method includes attaching at least one bond wire between the top side control contact of the semiconductor die and the control pad portion of the top metal layer. The method includes attaching a bottom end of each one of a spaced-apart row of first wires to the top metal layer proximate to the first side of the top metal layer such that each one of the first wires extends in an upward direction from the first metal layer and a top end of the first wires have a height perpendicular to the plane of the first metal layer that is greater than a height of a top side of the spacer from the plane of the first metal layer. At least one of the first wires is attached to the control pad portion of the top metal layer, and other ones of the first wires are attached to the die pad portion of the top metal layer.
According to an embodiment of a method of forming a double sided cooling module, the method includes providing a leadframe with a top Direct Copper Bonded (DCB) substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer, where the leadframe is attached to the bottom metal layer. The method includes providing two or more power transistor submodules, where each power transistor submodule includes a bottom DCB substrate that includes a top metal layer and a bottom metal layer separated by an insulation layer, where the top metal layer of the bottom DCB substrate has a first side, a second side and a center equidistant from the first side and the second side in a direction parallel with a plane of the top metal layer of the bottom DCB substrate. The two or more power transistor submodules each include a spaced-apart row of first wires that each have a top end and a bottom end, where the bottom end of each of the first wires is attached to the top metal layer of the bottom DCB substrate proximate to the first side of the top metal layer of the bottom DCB substrate. The two or more power transistor submodules each include a semiconductor die that includes a top side load path contact, a top side control contact and a bottom side load path contact. The bottom side load path contact is attached to a top surface of a die pad portion of the top metal layer of the bottom DCB substrate, the top side control contact is electrically coupled via at least one bond wire to a top surface of a control pad portion of the top metal layer of the bottom DCB substrate that is electrically isolated from the die pad portion. At least one of the first wires is attached to the control pad portion of the top metal layer of the bottom DCB substrate, and other ones of the first wires are attached to the die pad portion of the top metal layer of the bottom DCB substrate. The two or more power transistor submodules each include an electrically conductive and thermally conductive spacer over the semiconductor die that is attached to the top side load path contact of the semiconductor die. The method includes printing a solder on selected portions of the bottom metal layer of the top DCB substrate. The method includes placing a leadframe such that portions of the leadframe contact the solder. The method includes placing the two or more power transistor submodules such that a top side of the spacer, the top end of the one of the first wires and the top ends of the other ones of the first wires contact the solder. The method includes reflowing the solder under a pressure from a top metal piece and a bottom metal piece that are coplanar and have a distance between a lower surface of the top metal piece and an upper surface of the bottom metal piece that corresponds to a required thickness of the double sided cooling module, where the top metal piece apples a downward pressure against the top metal layer of the top DCB substrate, and where the bottom metal piece applies an upward pressure against the bottom metal layer of the bottom DBC substrate for each one of the two or more power transistor submodules, and where the reflowing of the solder attaches the top side of the spacer, the top end of the one of the first wires and the top ends of the other ones of the first wires to the bottom metal layer of the top DCB substrate.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing”, “upper,” “lower,” “right”, “left”, “vertical,” “horizontal” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting.
As employed in this specification, the terms “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e. that no intervening elements or layers are provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively.
Furthermore, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) indirectly on the implied surface with the part, element or material layer or layers being arranged between the implied surface and the part, element or material layer. However, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may optionally also have the specific meaning that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) directly on, e.g. in direct contact with, the implied surface.
The semiconductor die may be of different types, may be manufactured by different technologies and may include, for example, integrated electrical, electro-optical or electro-mechanical circuits and/or passive devices. The semiconductor die may, for example, be logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or passive devices. They may include control circuits, microprocessors or microelectromechanical components. The semiconductor die can include, but are not limited to, a power semiconductor die, a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) such as a Silicon Metal Oxide Semiconductor Field-effect Transistor (Si MOSFET) or a Silicon Carbide MOSFET (SiC MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) device, a Junction Gate Field Effect Transistor (JFET), as well as power bipolar transistors or power diodes.
The integrated circuit packages, lead frames and lead frame modules described herein may include packages such as a Transistor Outline (TO) package, a Quad Flat No Leads Package (QFN) package, a Small Outline (SO) package, a Small Outline Transistor (SOT) package, a Thin Small Outline Package (TSOP) package, a Dual Small Outline Package (DSO) and a Double Sided Cooling (DSC) package. The leadframe modules can include one or multiple semiconductor die on a same die pad or on different die pads of the leadframe module.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In the illustrated embodiment, a semiconductor die 140 includes a top side load path contact 142, a top side control contact 144 and a bottom side load path contact 146. The bottom side load path contact 146 is attached to a top surface 148 of a die pad portion 150 of the top metal layer 104. The top side control contact 144 is electrically coupled via at least one bond wire 152 to a top surface 154 of a control pad portion 156 of the top metal layer 104. The control pad portion 156 is proximate to the first side 110 of the top metal layer 104. The control pad portion 156 is electrically isolated from the die pad portion 150. At least one of the first wires 118 as illustrated at 118A is attached to the control pad portion 156 of the top metal layer 104, and other ones of the first wires 118 as illustrated at 118B are attached to the die pad portion 150 of the top metal layer 104. A first solder layer 158 is on a top surface 148 of the die pad portion 150 of the top metal layer 104. The first solder layer 158 attaches and electrically couples the semiconductor die 140 to the die pad portion 150 of the top metal layer 104. An electrically conductive and thermally conductive spacer 160 is over the semiconductor die 140 and is attached to the top side load path contact 142 of the semiconductor die 140. A second solder layer 162 is on a top surface of the top side load path contact 142 of the semiconductor die 140. The second solder layer 162 attaches and electrically couples the spacer 160 to the top side load path contact 142 of the semiconductor die 140.
In one embodiment, the top end 122 of the first wires 118 have a height 126 perpendicular to the plane 116 of the first metal layer 104 that is greater than a height 164 of a top side 166 of the spacer 160 from the plane 116 of the first metal layer 104. In one embodiment, the top end 132 of the second wires 128 have a height 138 perpendicular to the plane 116 of the first metal layer 104 that is greater than a height 164 of the top side 166 of the spacer 160 from the plane 116 of the first metal layer 104. In one embodiment, a first length between the top end 122 and the bottom end 124 of the first wires 118 is approximately the same. In one embodiment, each one of the first wires 118 are straight and parallel with every other one of the first wires 118. In one embodiment, each one of the second wires 128 are straight and parallel with every other one of the second wires 128. In one embodiment, the first wires 118 are copper (Cu) first wires 118 and the second wires 128 are Cu second wires 128. In one embodiment, a first length between the top end 122 and the bottom end 124 of the first wires 118 is approximately equal to a second length between the top end 132 and the bottom end 134 of the second wires 128.
In the illustrated embodiment, semiconductor die 140 can be a Silicon Metal Oxide Semiconductor Field-effect Transistor (Si MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) power transistor or a Silicon Carbide MOSFET (SiC MOSFET). In other embodiments, semiconductor die 140 can be other suitable types of power devices. In one embodiment, the semiconductor die 140 is a SiC MOSFET, and the top side load path contact 142 is a source contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a drain contact. In one embodiment, the semiconductor die 140 is an IGBT, and the top side load path contact 142 is an emitter contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a collector contact.
Referring to
In the illustrated embodiment, power transistor submodules 100A and 100B each include a bottom DCB substrate 102 that includes a top metal layer 104 and a bottom metal layer 106 that are separated by an insulation layer 108. The top metal layer 104 has a first side 110, a second side 112 and a center 114 equidistant from the first side 110 and the second side 112 in a direction parallel with a plane 116 of the top metal layer 104 (See also,
In the illustrated embodiment, for each power transistor submodule 100A and 100B, a first angle 168 of each of the first wires 118 in a first direction 170 from the center 114 to the first side 110 of the top metal layer 104 relative to the plane 116 of the top metal layer 104 is greater than 45 degrees and less than 90 degrees (See also,
In the illustrated embodiment, least one of the first wires 118 for each power transistor submodule 100A and 100B is attached to the control pad portion 156 of the top metal layer 104 of the bottom DCB substrate 102 and a top end 122 of the each one of the first wires 118 is conductively coupled and attached to the bottom metal layer 408 of the top DCB substrate 402 via respective solder connections 420A and 420E. Other ones of the first wires 118 for each power transistor submodule 100A and 100B are attached to the die pad portion 150 of the top metal layer 104 of the bottom DCB substrate 102 and to the bottom metal layer 408 of the top DCB substrate 404 to electrically couple the bottom side load path contact 146 of semiconductor die 140 to the bottom metal layer 408 of the top DCB substrate 404 via respective solder connections 420B and 420F. The second wires 128 for each power transistor submodule 100A and 100B are attached to the die pad portion 150 of the top metal layer 104 of the bottom DCB substrate 102 and to the bottom metal layer 408 of the top DCB substrate 404 to electrically couple the bottom side load path contact 146 of semiconductor die 140 to the bottom metal layer 408 of the top DCB substrate 404 via respective solder connections 420D and 420H. The spacer 160 for each power transistor submodule 100A and 100B is attached at a top end 166 to the bottom metal layer 408 of the top DCB substrate 404 to electrically couple the top side load path contact 142 of semiconductor die 140 to the bottom metal layer 408 of the top DCB substrate 404 via respective solder connections 420C and 420G. A mold compound 422 encapsulates a portion of the leadframe 402, the top DBC substrate 404 and power transistor submodules 100A and 100B such that a top surface 424 of the top metal layer 406 of the top DBC substrate 404 is exposed at a top surface 426 of the mold compound 422. A bottom surface 136 of the bottom metal layer 106 of the bottom DBC substrate 102 for each power transistor submodule 100A and 100B is exposed at a bottom surface 428 of the mold compound 422.
Although the different portions of bottom metal layer 408 of the top DCB substrate 404 are collectively referred to as bottom metal layer 408, it is understood that the top side load path contact 142, the top side control contact 144 and the bottom side load path contact 146 of semiconductor die 140 within each of the transistor submodules 100A and 100B are connected in a parallel arrangement. The one of the first wires 118 for each power transistor submodule 100A and 100B is conductively coupled to and attached to a first portion of bottom metal layer 408 of the top DCB substrate 404 and the other ones of the first wires 118 for each power transistor submodule 100A and 100B are conductively coupled to and attached to a second portion of the bottom metal layer 408 of the top DCB substrate 404 that is electrically isolated from the first portion of the bottom metal layer 408. The second wires 128 for each power transistor submodule 100A and 100B are conductively coupled to and attached to the second portion of bottom metal layer 408 of the top DCB substrate 404, and the spacer 160 is conductively coupled to and attached to a third portion of bottom metal layer 408 of the top DCB substrate 404 that is electrically isolated from both the first portion and the second portion of the bottom metal layer 408.
During formation or manufacturing of double sided cooling module 400, arrow 416 illustrates placement and attachment via solder connections 420A, 420B, 420C and 420D for power transistor submodule 100A against bottom metal layer 408 of top DCB substrate 404, and arrow 418 illustrates placement and attachment via solder connections 420E, 420F, 420G and 420H for power transistor submodule 100B against bottom metal layer 408 of top DCB substrate 404 via arrow 418. Each power transistor submodule 100A and 100B can be electrically tested before placement and attachment to ensure each power transistor submodule 100A and 100B meets a desired electrical specification. This increases a yield of double sided cooling module 400 because failure of one of the power transistor submodule 100A and 100B would result in the double sided cooling module 400 failing a final electrical test which would result in both power transistor submodules 100A and 100B being scrapped.
In the illustrated embodiment, two power transistor submodule 100A and 100B are illustrated. In one embodiment, each power transistor submodule 100A and 100B is designed for a particular power class or switching current rating. If double sided cooling module 400 requires a higher power class or an increased switching current rating, because the top side control contact 144 and the bottom side load path contact 146 of semiconductor die 140 within each of the power transistor submodules 100A and 100B are connected together in parallel, more power transistor submodules 100 can be added to double sided cooling module 400 to meet the higher power class rating or the increased switching current rating.
In the illustrated embodiment, semiconductor die 140 for each power transistor submodule 100A and 100B can be a Silicon Metal Oxide Semiconductor Field-effect Transistor (Si MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) power transistor or a Silicon Carbide MOSFET (SiC MOSFET). In other embodiments, semiconductor die 140 for each power transistor submodule 100A and 100B can be other suitable types of power devices. In one embodiment, semiconductor die 140 for each power transistor submodule 100A and 100B is a SiC MOSFET, and the top side load path contact 142 is a source contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a drain contact. In one embodiment, the semiconductor die 140 for each power transistor submodule 100A and 100B is an IGBT, and the top side load path contact 142 is an emitter contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a collector contact. In one embodiment, the first wires 118 are Cu first wires 118 and the second wires 128 are Cu second wires 128.
Double sided cooling module 500 includes a leadframe 502 with a top Direct Copper Bonded (DCB) substrate 504 that includes a top metal layer (not illustrated) and a bottom metal layer 506 that are separated by an insulation layer 508. The bottom metal layer 506 is illustrated in
Double sided cooling module 500 includes four power transistor submodules 300A that are described with respect to
Each power transistor submodule 300A-1, 300A-2, 300A-3 and 300A-4 includes a bottom Direct Copper Bonded (DCB) substrate 102 that includes a top metal layer 104 and a bottom metal layer 106 that are separated by an insulation layer 108 (See also,
The method includes printing a solder on selected portions of the bottom metal layer 608 of the top DCB substrate 604. The selection portions are illustrated as 616A, 616B, 616C, 616D, 616E, 616F, 616G, 616H, 616I and 616J. The method includes placing the leadframe 602 such that lead 612 contacts solder portion 616A and lead 614 contacts solder portion 616J. The method includes placing the power transistor submodules 100A and 100B such that a top side 166 of the spacer 160 for power transistor submodule 100A contacts solder portion 616D and a top side 166 of the spacer 160 for power transistor submodule 100B contacts solder portion 616H (See also,
The method includes reflowing the solder portions 616A, 616B, 616C, 616D, 616E, 616F, 616G, 616H, 616I and 616J under a pressure from a top metal piece 618 and a bottom metal piece 620 that are coplanar and have a distance between a lower surface 622 of the top metal piece 618 and an upper surface 624 of the bottom metal piece 620 that corresponds to a required thickness illustrated at 626 for double sided cooling module 600 and the double sided cooling module 400 illustrated in
In the illustrated embodiment, and referring to
In the illustrated embodiment, reflowing the solder portions 616A, 616B, 616C, 616D, 616E, 616F, 616G, 616H, 616I and 616J under a pressure from the top metal piece 618 and the bottom metal piece 620 includes the first wires 118 and the second wires 128 functioning as compression springs for the power transistor submodules 100A and 100B that provide a force between the bottom metal layer 608 of the top DCB substrate 604 and the top metal layer 104 of the bottom DCB substrate 102 for each one of the power transistor submodules 100A and 100B to press the top metal layer 606 of the top DBC substrate 604 against the lower surface 622 of the top metal piece 618 and to press the bottom metal layer 106 of the bottom DCB substrate 102 for power transistor submodules 100A and 100B against the upper surface 624 of the bottom metal piece 620 to provide the required thickness 626 of the double sided cooling module 400.
In one embodiment, providing the two or more power transistor submodules 100 which are illustrated as power transistor submodule 100A and power transistor submodule 100B further includes first electrically testing each one of a plurality of power transistor submodules 100 to identify the ones of the plurality of power transistor submodules 100 that meet a desired electrical specification for the power transistor submodules 100. The method includes providing the ones of the plurality of power transistor submodules 100 that meet the desired electrical specifications as the power transistor submodule 100A and power transistor submodule 100B.
The method includes encapsulation a portion of the leadframe 602/402, the top DBC substrate 604/404 and the two or more power modules 100 which are illustrated as power transistor submodule 100A and power transistor submodule 100B with a mold compound 422 such that a top surface 424 of the top metal layer 406 of the top DBC substrate 404 is exposed at a top surface 426 of the mold compound 422 and a bottom surface 136 of the bottom metal layer 106 of the bottom DBC substrate 102 for each power transistor submodule 100A and 100B is exposed at a bottom surface 428 of the mold compound 422 (See also,
Referring to
Referring to
In the illustrated embodiment, and referring also to
In the illustrated embodiment, least one of the first wires 118 for each power transistor submodule 700A and 700B is conductively coupled to and attached to the control pad portion 156 of the top metal layer 104 of the bottom DCB substrate 102 and a top end 122 of the each one of the first wires 118 is conductively coupled to and attached to the bottom metal layer 908 of the top DCB substrate 904 via respective solder connections 920A and 920D to electrically couple the top side control contact 144 of semiconductor die 140 to the bottom metal layer 908 of the top DCB substrate 904. Other ones of the first wires 118 for each power transistor submodule 700A and 700B are conductively coupled to and attached to the die pad portion 150 of the top metal layer 104 of the bottom DCB substrate 102 and a top end 122 of the each one of the first wires 118 is conductively coupled to and attached to the bottom metal layer 908 of the top DCB substrate 904 via respective solder connections 920B and 920E to electrically couple the bottom side load path contact 146 of semiconductor die 140 to the bottom metal layer 908 of the top DCB substrate 904. The spacer 160 for each power transistor submodule 700A and 700B is attached at a top side 166 to the bottom metal layer 908 of the top DCB substrate 904 to electrically couple the top side load path contact 142 of semiconductor die 140 to the bottom metal layer 908 of the top DCB substrate 904 via respective solder connections 920C and 920F. 15. Each one of the two power transistor submodules 700A and 700B includes a spring washer 930 between a top side of the spacer 160 and the bottom metal layer 908 of the top DCB substrate 904. Spring washer 930 is embedded within solder connections 920C and 920F for respective power transistor submodule 700A and 700B and are used during formation of double sided cooling module 900 where reflowing the solder by providing a force between the bottom metal layer 908 of the top DBC substrate 904 and the top side 166 of the spacer 160 for power transistor submodule 700A and 700B provides the required thickness of the double sided cooling module 900 (See also,
In the illustrated embodiment, a mold compound 922 encapsulates a portion of the leadframe 902, the top DBC substrate 904 and power transistor submodules 700A and 700B such that a top surface 924 of the top metal layer 906 of the top DBC substrate 904 is exposed at a top surface 926 of the mold compound 922. A bottom surface 136 of the bottom metal layer 106 of the bottom DBC substrate 102 for each power transistor submodule 700A and 700B is exposed at a bottom surface 928 of the mold compound 922.
Although the different portions of bottom metal layer 908 of the top DCB substrate 904 are collectively referred to as bottom metal layer 908, it is understood that in one embodiment, the top side load path contact 142, a top side control contact 144 and a bottom side load path contact 146 of semiconductor die 140 within each of the transistor submodules 700A and 700B are connected in a parallel arrangement. In one embodiment, the one of the first wires 118 for each power transistor submodule 700A and 700B are conductively coupled to and attached to a first portion of bottom metal layer 908 of the top DCB substrate 904, the other ones of the first wires 118 for each power transistor submodule 700A and 700B are conductively coupled to and attached to a second portion of bottom metal layer 908 of the top DCB substrate 904 that is electrically isolated from the first portion of the bottom metal layer 904, and the spacer 160 is conductively coupled to and attached to a third portion of bottom metal layer 908 of the top DCB substrate 904 that is electrically isolated from both the first portion and the second portion of the bottom metal layer 908.
In the illustrated embodiment, semiconductor die 140 for each power transistor submodule 700A and 700B can be a Silicon Metal Oxide Semiconductor Field-effect Transistor (Si MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) power transistor or a Silicon Carbide MOSFET (SiC MOSFET). In other embodiments, semiconductor die 140 for each power transistor submodule 700A and 700B can be other suitable types of power devices. In one embodiment, semiconductor die 140 for each power transistor submodule 700A and 700B is a SiC MOSFET, and the top side load path contact 142 is a source contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a drain contact. In one embodiment, the semiconductor die 140 for each power transistor submodule 700A and 700B is an IGBT, and the top side load path contact 142 is an emitter contact, the top side control contact 144 is a gate contact, and the bottom side load path contact 146 is a collector contact. In one embodiment, the first wires 118 are Cu first wires 118.
The method includes printing a solder on selected portions of the bottom metal layer 1108 of the top DCB substrate 1104. The selection portions are illustrated as 1116A, 1116B, 1116C, 1116D, 1116E, 1116F, 1116G and 1116H. The method includes placing the leadframe 1102 such that lead 1112 contacts solder portion 1116A and lead 1114 contacts solder portion 1116H. The method includes placing the power transistor submodules 700A and 700B such that a top side 166 of the spacer 160 for power transistor submodule 700A contacts solder portion 1116D and a top side 166 of the spacer 160 for power transistor submodule 700B contacts solder portion 1116G. Placing the power transistor submodules 700A and 700B further includes placing the top end 122 of a one of the first wires 118 for power transistor submodule 700A against solder portion 1116B and placing the top ends 122 of the other ones of the first wires 118 for power transistor submodule 700A against solder portion 1116C. Placing the power transistor submodules 700A and 700B further includes placing the top end 122 of a one of the first wires 118 for power transistor submodule 700B against solder portion 1116E and placing the top ends 122 of the other ones of the first wires 118 for power transistor submodule 700B against solder portion 1116F.
The method includes reflowing the solder portions 1116A, 1116B, 1116C, 1116D, 1116E, 1116F, 1116G and 1116H under a pressure from a top metal piece 1118 and a bottom metal piece 1120 that are coplanar and have a distance between a lower surface 1122 of the top metal piece 1118 and an upper surface 1124 of the bottom metal piece 1120 that corresponds to a required thickness illustrated at 1126 for the double sided cooling module 700 illustrated in
In the illustrated embodiment, placing the two power transistor submodules 700A and 700B such that the top side 166 of the spacer 160 contacts respective solder portions 1116D and 1116G includes placing a spring washer 1130 between the top side 166 of the spacer 160 and the bottom metal layer 1108 and within the respective solder portions 1116D and 1116G for the power transistor submodules 700A and 700B. Reflowing the respective solder portions 1116D and 1116G for the power transistor submodules 700A and 700B under the pressure from the top metal piece 1118 and the bottom metal piece 1120 includes the spring washer 1130 for the power transistor submodules 700A and 700B being compressed and providing a force between the bottom metal layer 1108 of the top DBC substrate 1104 and the top side 166 of the spacer 160 for each one of the power transistor submodules 700A and 700B to press the top metal layer 1106 of the top DBC substrate 1104 against the lower surface 1122 of the top metal piece 1118 and to press the bottom metal layer 106 of the bottom DCB substrate 102 for each one of the power transistor submodules 700A and 700B against the upper surface 1124 of the bottom metal piece 1120 to provide the required thickness 1126 of the double sided cooling module 900.
In one embodiment, providing the two or more power transistor submodules 100 which are illustrated as power transistor submodule 700A and power transistor submodule 700B further includes first electrically testing each one of a plurality of power transistor submodules 700 to identify the ones of the plurality of power transistor submodules 700 that meet a desired electrical specification. The method includes providing the ones of the plurality of power transistor submodules 700 that meet the desired electrical specifications as the power transistor submodule 700A and power transistor submodule 700B.
The method includes encapsulating a portion of the leadframe 1102/902, the top DBC substrate 1104/904 and the power transistor submodules 700A and 700B with a mold compound 922 such that a top surface 924 of the top metal layer 906 of the top DBC substrate 904 is exposed at a top surface 926 of the mold compound 922 and a bottom surface 136 of the bottom metal layer 106 of the bottom DBC substrate 102 for each one of the power transistor submodules 700A and 700B is exposed at a bottom surface 928 of the mold compound 922 (See also,
The double sided cooling module 1200 includes a leadframe 1202 with a top Direct Copper Bonded (DCB) substrate 1204 that includes a top metal layer (not illustrated) and a bottom metal layer 1208 that are separated by an insulation layer 1210. The bottom metal layer 1208 is illustrated in
Each power transistor submodule 800A-1, 800A-2, 800A-3 and 800A-4 includes a bottom Direct Copper Bonded (DCB) substrate 102 that includes a top metal layer 104 and a bottom metal layer 106 that are separated by an insulation layer 108 (See also,
At 1304, the method includes placing a first preform solder layer 158 on a top surface 148 of the die pad portion 150 of the top metal layer 104. At 1306, the method includes placing a semiconductor die 140 on a top surface of the first solder preform layer 158. The semiconductor die 140 includes a top side load path contact 142, a top side control contact 144 and a bottom side load path contact 146. At 1308, the method includes placing a second solder preform layer 162 on a top surface of the top side load path contact 142 of the semiconductor die 140. At 1310, the method includes placing an electrically conductive and thermally conductive spacer 160 over the second solder preform layer 162. At 1312, the method includes reflowing the first solder preform layer 158 and the second solder preform layer 162 to attach the bottom side load path contact 146 of the semiconductor die 140 to the die pad portion 150 of the top metal layer 104 and to attach the spacer 160 to the top side load path contact 142 of the semiconductor die 140. At 1314, the method includes attaching at least one bond wire 152 between the top side control contact 144 of the semiconductor die 140 and a top surface 154 of a control pad portion 156 of the top metal layer 104.
At 1316, the method includes attaching a bottom end 124 of each one of a spaced-apart row of first wires 118 to the top metal layer 104 proximate to the first side 110 of the top metal layer 104. Each one of the first wires 118 extend in an upward direction as illustrated at 126 from the first metal layer 104. The top end 132 of the second wires 128 have a height 138 perpendicular to the plane 116 of the first metal layer 104 that is greater than a height 164 of the top side 166 of the spacer 160 from the plane 116 of the first metal layer 104. At least one of the first wires 118 as illustrated at 118A is attached to the control pad portion 156 of the top metal layer 104. Other ones of the first wires 118 as illustrated at 118B are attached to the die pad portion 150 of the top metal layer 104.
In some embodiments, attaching the bottom end 124 of each of the first wires 118 to the top metal layer 104 proximate to the first side 110 of the top metal layer 104 includes each one of the first wires 118 having a first angle 168 relative to the plane 116 of the top metal layer 104 that is approximately equal to 90 degrees.
In some embodiments, the method includes attaching a bottom end 134 of each one of a spaced-apart row of second wires 128 to the top metal layer 104 proximate to the second side 112 of the top metal layer 104 such that each one of the second wires 128 have a second angle 172 in a second direction 174 from the center 114 to the second side 112 of the top metal layer 104 relative to the plane 116 of the top metal layer 104 that is greater than 45 degrees and less than 90 degrees. In some embodiments, attaching a bottom end 124 of each one of a spaced-apart row of first wires 118 to the top metal layer 104 proximate to the first side 110 of the top metal layer 104 includes each one of the first wires 118 having a first angle 168 in a first direction 170 from the center 114 to the first side 110 of the top metal layer 104 relative to the plane 116 of the top metal layer 104 that is greater than 45 degrees and less than 90 degrees.
