Patent Application
20130155636
1. Field of the Disclosure
The present disclosure generally relates to integrated circuit devices and more particularly to through-silicon vias of integrated circuit devices.
2. Description of the Related Art
An integrated circuit device is typically formed in layers, whereby the layers form the electronic components, such as transistors and capacitors, of the integrated circuit device. After formation, the integrated circuit can be stacked or otherwise physically arranged with one or more additional integrated circuits in an integrated circuit package. Through-silicon vias (TSVs) are sometimes used to connect layers of one or more integrated circuits in an integrated circuit package, thereby providing an electrical connection between the layers.
The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
As used herein, an active TSV refers to a TSV that provides an electrical connection between components, such as transistors, of the integrated circuit device. An active TSV thus provides an electrical function for a circuit of the device. As used herein, a dummy TSV does not provide a connection between components of the integrated circuit device. The dummy TSV can affect the electrical properties of the integrated circuit device, such as a decoupling capacitance, but do not provide an electrical connection for a circuit of the device.
In the illustrated embodiment, the integrated circuit device includes a substrate 102. In an embodiment, the substrate 102 is a silicon substrate upon which electronic circuits, each including a number of circuit elements are formed. For example, the integrated circuit device 100 includes circuit elements 104-107 formed on the substrate 102. Examples of circuit elements include transistors, passive elements such as capacitors, and the like. In an embodiment, the circuit elements 104-107 are formed by placing integrated circuit layers over the substrate 102.
In an embodiment, different integrated circuit dies are mounted on different sides of the substrate 102. Thus, for example, circuit elements 104 and 106 can be formed at one integrated circuit die on one side of the substrate 102 (illustrated in
Active TSVs can be placed in the substrate 102 to provide electrical connections between circuit elements of different integrated circuit dies. Thus, in the illustrated embodiment, active TSV 110 provides an electrical connection between the circuit element 104 and the circuit element 105.
In addition, dummy TSVs can be placed in the substrate 102. For example, in the embodiment of
Because the dummy TSVs are formed of a size such that they cannot form connections between circuit elements, they can be widely distributed through an integrated circuit device. This can be better understood with reference to
In the illustrated example of
The integrated circuit 200 can be designed and formed in order to achieve the substantially uniform spatial distribution, or other desired distribution, of TSVs. For example, in one embodiment the integrated circuit 200 is designed by determining the spatial locations of each of the active TSVs. Based on the spatial distribution of the active TSVs, the spatial distribution of the dummy TSVs is determined in order to achieve the desired overall distribution of TSVs. The active and dummy TSVs are then placed at the substrate 202.
In an embodiment, the dummy TSVs can be connected to one or more reference voltages in order to set a decoupling capacitance for an integrated circuit device. This can be better understood with reference to
In the illustrated embodiment, approximately half of the dummy TSVs are connected to VDD and approximately half are connected to VSS. As used herein, approximately refers to being at a value within a tolerance of 2%. This connectivity of the dummy TSVs can increase the capacitance associated with the substrate 302, thereby reducing noise associated with particular circuit types such as power regulators, without requiring the formation of additional capacitors at the integrated circuit device 300. The dummy TSVs can thus be used to increase a decoupling capacitance associated with the integrated circuit device 300. In other embodiments, other ratios of dummy TSVs connected to VDD and VSS can be implemented in order to achieve a desired capacitance.
In another embodiment, the capacitance can be achieved by connecting a set of dummy TSVs to one voltage reference and connecting the substrate itself to another voltage reference. This can be better understood with reference to
In the illustrated embodiment, approximately half of the dummy TSVs are connected to VDD and approximately half not connected to a reference voltage. Further, the substrate 402 is connected to the VSS. This connectivity of the dummy TSVs and the substrate can increase the capacitance associated with the substrate 402, In other embodiments, a different number of dummy TSVs can be connected to VDD can be in order to achieve a desired capacitance.
At block 502 a distribution of active TSVs for an integrated circuit device are determined. This includes determining the relative spatial position of each active TSV at a substrate of the integrated circuit device. At block 504, a distribution of dummy TSVs is determined based on the distribution of active TSVs. The distribution of dummy TSVs is also based on a desired overall distribution of both active and dummy TSVs at the substrate, such as a substantially uniform distribution. At block 506, the integrated circuit device is formed, whereby the dummy and active TSVs are each located according to the determined distribution. At block 508, the dummy TSVs, a substrate of the integrated circuit device, or a combination thereof are coupled to one or more voltage references in order to set a capacitance, such as a decoupling capacitance, associated with the integrated circuit device.
As disclosed herein, in one embodiment a method includes coupling a first plurality of dummy through-silicon vias (TSVs) of an integrated circuit device to a first voltage reference to set a capacitance associated with the integrated circuit device. In one aspect, the method includes coupling a second plurality of dummy TSVs of the integrated circuit device to a second voltage reference to set the capacitance. In another aspect, the number of dummy TSVs of the first plurality of dummy TSVs is substantially the same as the number of TSVs of the second plurality of dummy TSVs. In yet another aspect, the method includes coupling a substrate of the integrated circuit device to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate. In still another aspect, the method includes spatially distributing the first plurality of dummy TSVs based on a spatial distribution of a plurality of active TSVs of the integrated circuit device. In another aspect, the first plurality of dummy TSVs have a different depth than the plurality of active TSVs. In another aspect spatially distributing the plurality of dummy TSVs includes spatially distributing the plurality of dummy TSVs such that the plurality of dummy TSVs and the plurality of active TSVs are together distributed in a substantially uniform distribution at a substrate of the integrated circuit device.
In another embodiment a method of forming an integrated circuit device includes forming the device to have a plurality of active TSVs and a plurality of dummy TSVs, and coupling a first subset of the plurality of dummy TSVs to a first voltage reference to set a capacitance associated with the integrated circuit device. In one aspect, the method includes coupling a second subset of the plurality of dummy TSVs to a second voltage reference to set the capacitance. In another aspect, the first subset consists of approximately half of the plurality of dummy TSVs. In yet another aspect, the second subset consists of approximately half of the plurality of dummy TSVs. In still another aspect, the method includes coupling a substrate of the integrated circuit device to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate. In another aspect, the plurality of dummy TSVs have a different depth than the plurality of active TSVs.
In an embodiment, an integrated circuit device includes a plurality of active TSVs and a plurality of dummy TSVs, a first subset of the plurality of dummy TSVs coupled to a first voltage reference to set a capacitance associated with the integrated circuit device. In one aspect, a second subset of the plurality of dummy TSVs is coupled to a second voltage reference to set the capacitance. In another aspect, the first subset consists of approximately half of the plurality of dummy TSVs. In still another aspect, the second subset consists of approximately half of the plurality of dummy TSVs. In yet another aspect, a substrate of the integrated circuit device is coupled to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate. In another aspect, the plurality of dummy TSVs have a different depth than the plurality of active TSVs. In still another aspect the capacitance is a decoupling capacitance of the integrated circuit device.
Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device may not be required, and that one or more further activities may be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed.
Also, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.
| Number | Date | Country | |
|---|---|---|---|
| 61576525 | Dec 2011 | US |
