Patent Application
20130015552
III-nitride materials, particularly binary, ternary, quaternary, and quinary alloys of gallium, boron, aluminum, indium, and nitrogen, have been used to produce semiconductor light emitting devices such as light emitting diodes and laser diodes. III-nitride materials may also have advantages for power electronics, particularly in applications requiring high voltage, high power, high temperature, or high frequency operation.
III-nitride materials are typically fabricated by epitaxial growth on a substrate such as sapphire, silicon, silicon carbide, or GaN. N-type layers are typically doped with Si and p-type layers are typically doped with Mg. Examples of suitable epitaxial techniques include metal organic chemical vapor deposition and molecular beam epitaxy. III-nitride devices are often grown on non-III-nitride substrates such as sapphire or silicon due to the low cost and wide availability of sapphire and silicon substrates.
High densities of defects such as dislocations, for example on the order of 109 cm−2, are produced at the interface between a GaN layer and a sapphire or other non-III-nitride substrates on which the GaN layer is grown, due to the large mismatch between the crystal lattices of the GaN layer and the substrate. The defects tend to propagate throughout the as-grown layers. Because dislocations are not desirable within the active device layer, it is preferable to grow GaN on a GaN substrate, in order to reduce the density of dislocations. III-V substrates besides GaN, such as GaAs and InP, may be formed by melt growth, where the III-V material is melted at high temperature and cooled and solidified below the melting point so that a solid single crystal ingot grows from a small seed crystal. It is not practical to form GaN substrates by melt growth because extremely high temperature and pressure are required to prevent decomposition of the GaN at the melting point. Accordingly, current commercially-available GaN substrates are generally formed by growing a thick GaN layer at a high growth rate on a non-III-nitride substrate by hydride vapor phase epitaxy, then removing the non-III-nitride substrate. A patterned thin layer of a different material from GaN is formed on the non-III-nitride substrate before growth of the thick GaN layer. As the thick GaN layer grows, pits form over the areas of different material on the patterned layer. Dislocations and other defects are concentrated in the pits, leaving the areas between the pits with dislocations densities of 105 cm−2 or lower. The concentrations of dislocations are referred to herein as defect centers. The patterned layer may be formed such that the defect centers are points or lines.
In some devices including defect centers, the defect centers must be electrically isolated from metal contacts or conducting regions in order to avoid shorting.
Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion.
A method according to embodiments of the invention includes growing a III-nitride semiconductor structure on a GaN substrate. The GaN substrate includes a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. At least part of the III-nitride semiconductor structure grown over the first portion is electrically isolated from part of the III-nitride semiconductor structure grown over the second portion.
Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An electrical isolation element is disposed in the III-nitride semiconductor layer in the first portion, wherein the electrical isolation element electrically isolates the first portion from at least part of the second portion.
GaN substrates 10 including point defect centers 12 are commercially available. The spacing between neighboring defect centers 12 is controlled by the substrate manufacturer. Typical spacing is on the order of 1 mm. The layers in the device structure 13 grown over substrate 10 replicate the material quality in different regions of substrate 10. Accordingly, in device structure 13, material grown over defect centers 12 has a high concentration of defects, for example 106 cm−2 or more. Material 15 grown between defect centers 12 has a much lower concentration of defects, for example 104 cm−2 or less. In some embodiments, the material 15 between defect centers 12 has a concentration of defects at least two orders of magnitude less than defect centers 12.
Ideally, devices are confined to the spaces 15 between defect centers 12. However, the size of devices in some embodiments necessarily includes at least one defect center 12. For example, devices may be at least 3 mm in length in some embodiments, at least 4 mm in length in some embodiments, and at least 10 mm in length in some embodiments. Such devices cannot be confined to the spaces 15 between defect centers 12, when the defect centers are spaced 1 mm apart.
In devices that include a defect center 12, due to the high concentration of defects at defect center, forming a metal contact or other conductive region in direct contact with defect center 12 can cause a short. Embodiments of the invention are directed to structures and methods that electrically isolate defect centers 12 such that metal contacts can be formed over defect centers 12.
In some embodiments, a device structure 13 is first grown over a substrate 10 including defect centers 12. Though in the examples below, the device structure 13 is a diode, embodiments of the invention may be applied to any suitable device structure including but not limited to other electronic and optoelectronic devices including field effect transistors, high electron mobility transistors, light emitting diodes, and lasers. The device structure 13 often includes different layers of different composition, dopant type, and dopant concentration. For example, device structure 13 generally includes both p- and n-type layers, and may include, for example, GaN, InGaN, and/or AlGaN layers.
As described above, in the structure illustrated in
In the structure illustrated in
Covers 20 may be formed by depositing a dielectric layer over the entire surface of device structure 13 by any suitable technique including deposition, plasma-enhanced chemical vapor deposition, and sputtering. The dielectric layer is then patterned by masking and etching the layer with conventional photolithography. Since the spacing between defect centers is known (because it is determined during manufacture of the substrate), the mask used to pattern the dielectric layer can be aligned with all the defect centers by aligning the mask with a single defect center, for example by simple visual alignment of the mask with the wafer. Covers 20 may be aligned with defect centers 12 to within 10 μm.
In some embodiments, covers 20 are formed with fine alignment features to aid in the alignment of later photolithography masks, as illustrated in
Etched regions 28 may be as wide as or wider than defect centers 12 in order to avoid shorting. Etched regions 28 may be 50% wider than the defect centers in some embodiments, 20% wider than the defect centers in some embodiments, and 10% wider than the defect centers in some embodiments. Etched regions 28 may be between 100 Å and 100 μm deep in some embodiments, between 50 nm and 30 μm deep in some embodiments, and between 0.1 and 0.3 μm deep in some embodiments.
In
The implant depth depends on the implant conditions, including, for example, the implant species, the implant dose, and the implant energy. The implant regions may extend from the surface of the wafer to a depth of 10 nm in some embodiments, from the surface of the wafer to a depth of 100 nm in some embodiments, and from the surface of the wafer to a depth of 500 nm in some embodiments. Examples of suitable implant species include any suitable p-type species which may act as electrical blocking layers, including, for example, Mg and Be; any suitable inert species including, for example, Ar, N2, H2, O2; any suitable deep acceptor which may act as a traps, including, for example, Fe, Zn, Ni, and Co.
In some embodiments, implanting is combined with other methods of electrical isolation, such as the insulating covers described above. In some embodiments, defect centers on both the top surface and the bottom surface of the wafer may be implanted, as necessary for the particular device grown on the wafer.
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.
