The invention relates to the field of integrated circuit design and manufacturing. More particularly, various implementations of the invention are applicable to simulating the proximity effects of electron beam exposure in optical lithography and correcting corner rounding resulting there from.
Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, a design may start at a high level of abstraction, by a designer creating a specification that describes particular desired functionality. This specification, typically implemented by a programming language, such as the C or C++ programming language for example, describes at a high level the desired behavior of the device. Designers will then often take this specification for the design and create a logical design, often implemented in a netlist, through a synthesis process. The logical design is often referred to as a “register transfer level” (RTL) description or register transfer level design.
A register transfer level design is often implemented by a hardware description language (HDL) such as Verilog, SystemVerilog, or Very High speed hardware description language (VHDL), and describes the operation of the device by defining the flow of signals or the transfer of data between various hardware components within the design. More particularly, a register transfer level design describes the interconnection and exchange of signals between hardware registers and the logical operations that are performed on those signals.
The design process includes another transformation, this time the register transfer level design is transformed into a gate level design. Gate level designs describe the actual physical components such as transistors, capacitors, and resistors as well as the interconnections between these physical components. Often, gate level designs are also implemented by a netlist, such as a mapped netlist. Lastly, the gate-level design is taken and another transformation is carried out. First by place and route tools that arrange the components described by the gate-level netlist and route connections between the arranged components; and second, by layout tools that generate a layout description having layout “shapes” or “patterns” that may then used to fabricate the electronic device, through for example, an optical lithographic process.
Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is popular for transferring and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in integrated circuit layout designs that are employed to manufacture integrated circuits. Once the microcircuit device design is finalized, the layout portion of the design can be used by fabrication tools to manufacturer the device using a photolithographic process.
There are many variations of the fabrication processes used to manufacture a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design data, after which the mask can be used in a photolithographic process.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. Various common techniques exist for increasing the fidelity of the optical lithographic process. For example, optical process correction (OPC), phase shift masks (PSM) or other resolution enhancement techniques (RET) are commonly employed to prepare a physical layout designs for manufacturing.
These various resolution enhancement techniques are commonly applied at different stages of device development. Many of these techniques make adjustments to the layout design, or the mask, based upon simulations of the optical lithographic process. More particularly, the mask is typically adjusted in such a manner that a simulation of the printed layout based upon the adjusted mask more closely resembles the intended layout. Functions that account for the various component of the optical lithographic process exist. However, some of these functions, such as the function for simulating the proximity effects of electron beam exposure, create troublesome corner rounding.
The present invention provides methods and apparatuses for correcting corner rounding resulting from simulating the proximity effects of electron beam exposure in optical lithography. In various implementations, a printed layout pattern is simulated based upon an intended layout pattern and a function that approximates the printing process. With some implementations, the function incorporates a Gaussian proximity kernel to approximate the electron beam exposure effects. Subsequently, one or more corners of the simulated layout may be approximated by two or more straight edges. In various implementations, the number of straight edges used to approximate the corner as well as the orientation of the one or more straight edges is determined based upon the characteristics of the corner, such as, the corner having an obtuse angle larger than 135 degrees for example. With various implementations, two straight edges are used to approximate the corner, the orientation of the two straight edges being determined by a first point, a second point, and a shared corner point.
The present invention will be described by way of illustrative embodiments shown in the accompanying drawings in which like references denote similar elements, and in which:
The operations of the disclosed implementations may be described herein in a particular sequential order. However, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the illustrated flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods.
It should also be noted that the detailed description sometimes uses terms like “determine” to describe the disclosed methods. Such terms are often high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will often vary depending on the particular implementation, and will be readily discernible by one of ordinary skill in the art.
Furthermore, in various implementations of the invention, a mathematical function may be employed to approximate a real world process. With some implementations, functions describing an optical lithographic process, or portion of an optical lithographic process is employed. Those of skill in the art will appreciate that these functions represent real world physical processes. Accordingly, simulations based upon these functions are a representation of the tangible results, should the process be carried out under the simulated conditions.
Some of the methods described herein can be implemented by software stored on a computer readable storage medium, or executed on a computer. Accordingly, some of the disclosed methods may be implemented as part of a computer implemented electronic design automation (EDA) tool. The selected methods could be executed on a single computer or a computer networked with another computer or computers. For clarity, only those aspects of the software germane to these disclosed methods are described; product details well known in the art may be omitted.
As the techniques of the present invention may be implemented using software instructions, the components and operation of a generic programmable computer system on which various implementations of the invention may be employed is described. Accordingly,
The processing unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional devices, such as; a fixed memory storage device 115, for example, a magnetic disk drive; a removable memory storage device 117, for example, a removable solid state disk drive; an optical media device 119, for example, a digital video disk drive; or a removable media device 121, for example, a removable floppy drive. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 123 and one or more output devices 125. The input devices 123 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 125 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-125 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-125 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.
With some implementations, the computing unit 103 may be directly or indirectly connected to one or more network interfaces 127 for communicating with other devices making up a network. The network interface 127 translates data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 127 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection.
It should be appreciated that the computing device 101 is shown here for illustrative purposes only, and it is not intended to be limiting. Various embodiments of the invention may be implemented using one or more computers that include the components of the computing device 101 illustrated in
In a photolithographic process, as explained above, electromagnetic radiation is transmitted through selectively transparent areas of a mask. The radiation passing through these transparent areas then irradiates desired portions of a photoresistive material on a layer of semiconductor substrate. The mask in turn is created from layout design data describing the geometric features that should be manufactured on the semiconductor substrate, by way of the photolithographic process, in order to create the desired circuit. For example, if a transistor should have a rectangular gate region, then the layout design data will include a rectangle defining that gate region. This rectangle in the layout design data is then implemented in a mask for “printing” the rectangular gate region onto the substrate.
Additionally, as discussed modern integrated circuit design and manufacturing flows typically include various layout design adjustment steps, occasionally referred to as pattern correction steps. In order to more fully understand the corner approximation techniques discussed herein, an illustrative shape based correction process is discussed. As stated, an optical lithographic process seeking to reproduce the rectangular mask feature 201 illustrated in
To correct for these optical distortions, many circuit designers will attempt to modify the layout design data, producing modified mask features, to enhance the resolution of the images that will be produced by the modified mask during the photolithographic process. One resolution enhancement technique often employed by designers is called optical process correction (OPC) or optical proximity correction. In a typical optical proximity correction process, the edges of the geometric elements in the design are fragmented and adjusted in such a manner as to produce a printed image that more closely resembles the target image.
As indicated, resolution enhancement techniques are iterative in nature. More specifically, a printed image is simulated, the printed image is then compared to the target image, and the mask features are fragmented and adjusted based upon the comparison between the simulated image and the target image. Subsequent iterations of simulation, compare, and adjust are performed until the simulated image sufficiently matches the target image. Accordingly, accurate methods of simulating an image printed through an optical lithographic process are needed.
Various functions to approximate an optical lithographic process are used. For example, the VTR model is described in detail in U.S. Pat. No. 6,643,616, entitled “Integrated Device Structure Prediction Based On Model Curvature,” filed Nov. 4, 2003, and naming Yuri Granik et al. as inventors, which patent is incorporated entirely herein by reference. Additionally, lithographic modeling based upon the Hopkins Equation is discussed in detail in Process Variation Aware OPC with Variation Lithography Modeling, by Peng Yu et al., Proceeding of the 43rd Annual Conference on Design Automation, 24-28 Jul. 2006, which article is incorporated entirely herein by reference. Often, modern lithographic models utilize kernels to approximate the various components or “effects” of the optical lithographic process.
One such kernel is the electron beam kernel, which models the electron beam effects inherent in the optical lithographic process. Electron beam effects are often modeled with double-Gaussian kernels. Use of double-Gaussian kernels to model the effects of electron beam exposure, and particularly the proximity effects of electron beam exposure, is discussed in detail in Limitations of Proximity—Effects Corrections for Electron-Beam Patterning of Planar Photonic Crystals, by Robert Wüest et al., Optical Engineering Vol. 44, 043401 (2005), which article is incorporated entirely herein by reference. In various implementations of the invention, the electron beam exposure is modeled with narrow kernels. Diffusion length (i.e. α) is typically around 15-55 nanometers. A second kernel, which is typically much wider, models electron back-scattering. Its diffusion length (i.e. β) is typically around 1.6 micrometers. Accordingly, with various implementations of the invention, the proximity kernel may be represented by Equation (1) shown below.
As those of skill in the art can appreciate, electron beam exposure effects include “long range” and “short range” effects. The short range effects are often referred to herein as the proximity effects. In various implementations of the invention, the long range component of the electron beam exposure is compensated for by the Variable Etch Bias (VEB) kernel. Variable etch bias kernels are discussed in greater detail in Correction for Etch Proximity: New Models and Applications, by Yuri Granik, Proceeding of SPIE Vol. 4346 (2001), which article is incorporated entirely herein by reference. Alternatively, the long range effects of the electron beam exposure may be compensated for directly in the hardware of the optical lithographic process, by modulating the dose for example. Accordingly, in various implementations of the invention, the long range component of the electron beam exposure effects is ignored herein by setting it to zero (i.e. letting η=0).
As a result, a single-Guassian kernel remains, as shown in Equation (2), which is used in various implementations to approximate the proximity effects of the electron beam exposure.
However, use of the above described method for modeling the electron beam proximity effects of an optical lithographic process generates rounded corners. As those of skill in the art can appreciate, the tools used to manufacture optical lithographic masks, often referred to as mask writers are incapable of printing rounded features. Instead mask writers must print various geometric polygons. As a result, the rounded corners generated by simulating the proximity effects of electron beam cannot be realized in a mask.
As can be seen from this figure, the method 501 includes an operation 503 for identifying a simulated printed image 505. In various implementations of the invention, the simulated printed image 505 is simulated in part by a function, which may be kernel based, that accounts for the electron beam exposure effects of an optical lithographic process.
With alternative implementations, the operation 503 may identify a mask, or a portion of a mask, and derive the simulated printed image 505 on a computing device. In further implementations, the mask, or portion thereof, is represented by a plurality of pixels, wherein each pixel corresponds to a level of transparency. For example, areas where it is intended that radiation pass through may have a transparency of 1, while areas where it is intended that radiation not pass through may have a transparency of 0. Accordingly, a printed image (i.e. the intensity of radiation incident upon a substrate) may be derived by Equation (3), where m represents a mask. More particularly, m(x, y) may represent a characteristic mask function, with transparency values of 0 outside the shapes or polygons and 1 inside the shapes or polygons.
I(x,y)=Km (3)
As shown, the energy deposited on the substrate is proportional to the Image I, which is a convolution of the kernel and the mask. Subsequently, the final printed image, often referred to as the resist contour, may be approximated by a constant threshold resist model (CTR), for example by selecting a threshold T, and letting I(x, y)=T. In various implementations, the printed image depends upon derivation of the energy incedent on a semi-infinite plane.
The intensity for a semi-infinite plane (i.e. y≧0) may be given by Equation (4) shown below, where H is the Heaviside characteristic function.
The solution for a semi-infinite plane, may often be simplified to that shown in Equation (5), where “err” is the Gaussian error function. It is important to note that independently on the diffusion length α, the contour I=0.5 always stays on the boundary y=0 of the semi-infinite plane.
Returning to
As can be seen from
In various implementations, the operations 605 through 609 may derive the line ends P1 and P2, and the apex C based upon the type or corner identified by the operation 603. Accordingly, derivation of the line ends P1 and P2, and the apex C for various illustrative corner types, such as an isolated straight (i.e. 90 degree) corner for example is described herein.
Consider a convolution of the straight corner x>0, y>0:
Which may be reduced as follows:
As the pullback d is the hypotenuse of a triangle, d may be found by solving the following.
d=√{square root over (2)}xc=0.5449523α (9)
Assuming that the simulated contour 701f merges into the line at the distance l from the corner, one may set x=0, T=0.5-5%=0.475, represented by the following.
Subsequently, the operation 611 may replace the corner of the simulated contour 701f with straight edges based upon the derived values of d and l, as shown in
m(x,y)=H(x)H(y)+H(b−x)H(y)−H(y) (11)
As shown by Equation (11), a mask may be defined as a semi-infinite strip, with the mask value equaling 1 inside the strip and 0 outside the strip. Using the properties of linearity of convolution, the solution for I may be written as a combination of Equation (5) and Equation (7), as shown below.
The width of the line end should be determined based in part upon the requirement that the corners do not interact, which could result in line end pullback. The line end pullback p may be derived from x=b/2, y=p, which is shown below.
In various implementations, it is desirable to keep the line end pullback p less that y=0.05α. Accordingly, Equation (14) may be reduced to
which states that the corners of the line end do not interact if b≧2.73α. Accordingly, the corners may be corrected separately as shown in
The line end pullback for corners that interact are a function of b/α as stated above, and may be found through Equation (14) and approximated as shown below. The approximation is valid for the interval 1<b/α<4. It is important to note, that a maximum error for this approximation is estimated at 0.002.
In various implementations of the invention, the location for the point P1 is determined based upon the condition for a line end that does not interact. More particularly, P1=(0,l), where l is derived based upon Equation (10).
When line ends begin interacting, the location of the corner C is no longer on the diagonal. Instead, the corner location may be derived as follows.
A Lagrangian may be constructed using dimensionless variables (i.e. all variables divided by α) as follows:
L(x,y,λ)=x2+(y−p)2+λ[(erf(x)+erf(b−x))(1+erf(y))−2·erf(b)]→min (18)
Taking the derivatives of Equation (18) yields the following:
λ may be eliminated from the first and second derivatives from Equation (19), by substituting p from Equation (14). This results in two equations (i.e. curves) in the x, y plane that depend upon b as shown below.
One may solve for y in the third derivative from Equation (19) and substitute the solution into the first curve from Equation (20), as shown.
As can be seen from Equation (21), the curves depend upon b and x. Accordingly, the x and y coordinates for point C, may be approximated by the following Equations.
In various implementations of the invention, the coordinates for the point P2 may be derived as follows.
P
2=(xp2,p) (23)
In various implementations the x coordinate is found heuristically as being 7/12 from the corner C to the middle of the line, as shown.
The y coordinate may be found as follows.
For isolated corners of angle θ, the intensity I may be represented as follows.
Which in dimensionless coordinates may be written as:
Transforming the power of the exponent yields:
(ρ·cos φ−x)2+(ρ·sin φ−y)2=ρ2·cos2φ−2ρx cos φ+x2+ρ2·sin2φ−2ρy sin φ+y2=ρ2−2ρ(x cos φ+y sin φ)+r2=ρ2−2ρ(r cos γ cos φ+r sin γ sin φ)+r2=ρ2=2ρr(cos γ cos φ+sin γ sin φ)+r2=ρ2−2ρr cos(γ−φ)+r2=ρ2−2ρr cos(γ−φ)+(r cos(γ−φ))2−(r cos(γ−φ)2=(ρ−r cos(γ−φ))2+r2(1+cos2(γ−φ))=(ρ−a)2+r2−a2, a=r cos(γ−φ) (28)
As a result:
Simplifying the equations even further:
Substituting Equation (30) into Equation (29) yields:
Considering the last integral:
One may use the above simplifications to solve for the intensity I, as shown:
Acute Angles Less than or Equal to 45 Degrees
For acute angles less than or equal for 45 degrees, the corner may be approximated by replacing erf (r cos φ) by its average value (i.e. θ/2−γ), which yields the following in dimensional coordinates.
Which can be simplified by removing the polar angle γ:
It should be noted that Equation (35) has an accuracy of 10−3 for angles less than 45 degrees. In various implementations of the present invention, a simulated acute angled corner of less than 45 degrees may be approximated by deriving the offset of line ends P1 and P2 from a simulated contour having the condition that the threshold T=0.475 and the contour intersects y=0, which is the same conditions described with reference to Equation (10) above. Solving Equation (35) for these conditions, one may derive x coordinates by solving the following Equation for x.
Which may be approximated as follows:
For the case of an angle equaling 45 degrees:
xp,45=1.956α (38)
Acute Angles Greater than 45 Degrees
For acute angles greater than 45 degrees, the corner may be approximated by subtracting the solution for acute angels less than or equal to 45 degrees (i.e. as shown by Equation (33) or Equation (35) and subsequently “flipping” the axes, as shown here:
Flipping the axes and simplifying yields:
In various implementations, the offset of the line ends P1 and P2 may be derived by solving for the condition that T=0.475 intersects y=0, which is the same conditions described with reference to Equation (10) above. Accordingly, one may derive:
Which may be approximated as:
In various implementations, the apex C may be derived by letting γ=θ/2, which yields:
Which may be approximated as follows:
Obtuse Angles Less than or Equal to 135 Degrees
For obtuse angles less than or equal for 135 degrees, the corner may be approximated by adding the solution for an isolated straight corner and the solution for an acute angle of less than 45 degrees that has been rotated counterclockwise by 90 degrees. More particularly, x→y, y →−x, θ→θ−π/2, which yields:
In various implementations, the offset of the line ends P1 and P2 may be derived by solving for the condition that T=0.475 and intersects y=0, which is the same conditions described with reference to Equation (10) above. Solving Equation (45) for these conditions, one may derive x coordinates by solving the following Equation for x.
Which may be approximated as follows:
x
p/α=1.798−0.839√{square root over (θ−1)} (47)
With various implementations, the apex C may be solved for by letting γ=θ/2, T=0.5, which yields:
Which may be further approximated by:
Obtuse Angles Greater than 135 Degrees
For obtuse angle greater than 135 degrees, the corner may be approximated by subtracting from the solution for an acute angle of less than 45 degrees that has been flipped along the y axis. More particularly, x →−x, y→y, θ→π−θ. Accordingly, one may derive:
In various implementations, the offset of the line ends P1 and P2 may be derived by finding a critical angle (i.e. θcritical) for which the contour having a threshold of T=0.475 and being located as coordinates x=0 and y=0. Substituting the given conditions into Equation (50) yields:
Accordingly, the line ends P1 and P2 may be found by solving for the condition that T=0.475 intersects y=0, which is the same conditions described with reference to Equation (10) above and shown below:
For angles θ<θcritical, the line ends P1 and P2 may be approximated by the following:
x
p/α=0.9+0.45·ln(π−θ−0.02) (53)
Various implementation of the invention may derive the apex C by letting γ=θ/2, T=0.5, which yields:
Which may be approximated as follows:
The results of solving Equation (56) are shown in
Small jogs, which in some implementations are where b≦0.4664, may be approximated by a by straight edges as shown in
Substituting x=0, y=b/2 yields:
The equation for the tangent through the middle point (i.e. x=0, y=b/2) is then:
Intersecting with the coordinates y=0 and y=b yields the coordinates for the line ends P1=(−xp, 0), P2=(xp, b), which may be represented by the following Equation.
Which alternatively may be expressed in dimensional coordinates as follows:
As stated above, in various implementations, a job is considered “small” the distance between the line end P1 and the apex C as shown in
L(x,y,λ)=(x+xp)2+y2+λ((1=erf(x))(1−erf(y))+(1+erf(x))(1+erf(b−y))−2)→min (62)
Which may be simplified as:
Solving for A from the first derivative in Equation (63) yields:
Substituting into the second derivative in Equation (63) yields:
Equation (65) yields two equations that define coordinates for the apex C, namely Equations (66) and Equation (67).
y(erf(b−y)+erf(y))+(x+xp)[ex
(1−erf(x))(1−erf(y))+(1+erf(x))(1+erf(b−y))−2=0 (67)
Solving for erf (x) yields:
Substituting Equation (68) into Equation (66) yields:
It is important to note, that Equation (69) shows a dependence of the y coordinate of the apex C (i.e. yc) upon b. As a result, yc may be approximated by Equation (70) while xc may be derived from Equation (68).
In various implementations, jogs are considered to be large when b>0.4664. In various implementations, in the case of a large jog, the line end P1 may be derived using Equation (10). More particularly:
P
1=(xp1,0)
xp1−1.163α (71)
Subsequently, the apex C may be derived by using Equation (70) and Equation (71). More particularly:
C=(xc,yc) (72)
Finally, the line end P2 may be derived as follows:
Various methods for approximating the corners of a simulated contour have been disclosed herein. In various implementations, the simulated contours are generated based in part upon a model accounting for the electron beam exposure effects of an optical lithographic process. In further implementation, a printed layout pattern is simulated based upon an intended layout pattern and a function that approximates the printing process. With some implementations, the function incorporates a Gaussian proximity kernel to approximate the electron beam exposure effects. Subsequently, one or more corners of the simulated layout may be approximated by two or more straight edges. In various implementations, the number of straight edges used to approximate the corner as well as the orientation of the one or more straight edges is determined based upon the characteristics of the corner, such as, the corner having an obtuse angle larger than 135 degrees for example. With various implementations, two straight edges are used to approximate the corner, the orientation of the two straight edges being determined by a first point, a second point, and a shared corner point.
Although certain devices and methods have been described above in terms of the illustrative embodiments, the person of ordinary skill in the art will recognize that other embodiments, examples, substitutions, modification and alterations are possible. It is intended that the following claims cover such other embodiments, examples, substitutions, modifications and alterations within the spirit and scope of the claims.
This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/117,286 entitled “Electron Beam Simulator,” filed on Nov. 24, 2008, and naming Yuri Granik as inventor, which application is incorporated entirely herein by reference.
Number | Date | Country | |
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61117286 | Nov 2008 | US |