Claims
- 1. A virtual mirror cross over chip carrier, comprising:a first multiplicity of pairs of connection points, each pair of connection points of the first multiplicity of connection points pairs comprising electrically interconnected first and second connection points, the set of first connection points being arranged in a first pattern along a first edge of the chip carrier, and the set of second connection points being arranged in a second pattern along a second edge of the chip carrier, such that the second pattern is the virtual mirror of the first pattern; and a second multiplicity of pairs of connection points, each pair of connection points of the second multiplicity of connection point pairs comprising electrically interconnected third and fourth connection points, the set of third connection points being arranged in a third pattern along a third edge of the chip carrier, and the set of fourth connection points being arranged in a fourth pattern along a second edge of the chip carrier.
- 2. The virtual mirror cross over package of claim 1, wherein the third pattern is the virtual mirror of the fourth pattern.
- 3. The virtual mirror cross over package of claim 2, wherein:the first and second sets of connection points are symmetrical about an imaginary axis that perpendicularly bisects each of the imaginary lines that connect the first and second connection points of each pair of connection points of the first multiplicity of connection point pairs; and the third and fourth sets of connection points are symmetrical about an imaginary axis that perpendicularly bisects each of the imaginary lines that connect the third and fourth connection points of each pair of connection points of the second multiplicity of connection point pairs.
- 4. The virtual mirror cross over chip carrier of claim 3, wherein:each pair of connection points of the first multiplicity of connection point pairs is equally spaced apart from the adjacent pair of connection points; and each pair of connection points of the second multiplicity of connection point pairs is equally spaced apart from the adjacent pair of connection points.
- 5. The virtual mirror cross over chip carrier of claim 4, wherein the first edge of the chip carrier is substantially parallel to the second edge, and the third edge of the chip carrier is substantially parallel to the fourth edge.
- 6. The virtual mirror cross over chip carrier of claim 1, wherein the first and second sets of connection points are symmetrical about an imaginary axis that perpendicularly bisects each of the imaginary lines that connect the first and second connection points of each pair of connection points of the first multiplicity of connection point pairs.
- 7. The virtual mirror cross over chip carrier of claim 6, wherein each pair of connection points of the first multiplicity of connection point pairs is equally space apart from the adjacent pair of connection points.
- 8. The virtual mirror cross over chip carrier of claim 7, wherein the first edge of the chip carrier is substantially parallel to the second edge, and the third edge of the chip carrier is substantially parallel to the fourth edge.
CROSS REFERENCE TO OTHER APPLICATIONS
This is a divisional application of application Ser. No. 09/280,025 filed Mar. 26, 1999, U.S. Pat. No. 6,418,980, which is a continuation-in-part of co-pending application Ser. No. 09/223,135 filed Dec. 30, 1998. These co-pending applications are incorporated herein by reference.
US Referenced Citations (8)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09/223135 |
Dec 1998 |
US |
Child |
09/280025 |
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US |