Patent Application
20250118659
The present disclosure relates to an electronic component including a helical coil inductor and a planar conductor.
A coil component in which a helical coil is provided at a substrate is configured as an inductor.
Japanese Unexamined Patent Application Publication No. 2004-103756 (hereinafter the “'756 Application”) discloses a coil component that is produced by cutting a core substrate into chips, the core substrate having a plurality of beltlike conductors on both the top and reverse surfaces and insulating layers covering the beltlike conductors. Specifically, this coil component, on both the right and left side surfaces of a rectangular parallelepiped insulator of which the material is the core substrate, has a plurality of side conductors composed of the beltlike conductors, and an insulating layer covering the side conductors. In addition, the side conductors, and bridging conductors each connecting the side conductors on the top and bottom surfaces of the insulator configure a rectangle helical coil.
Moreover, Japanese Unexamined Patent Application Publication No. 2021-197454 (hereinafter the “'454 Application”) discloses a wiring substrate that includes a first insulating layer including no core material, a first conductor layer and a second conductor layer provided so as to face each other via the first insulating layer, and a plurality of via conductors passing through the first insulating layer and connecting the first conductor layer and the second conductor layer. The first conductor layer and the second conductor layer are adjacent through the first insulating layer. In addition, a magnetic material having a predetermined shape is embedded in the first insulating layer so as not to be in contact with any of the first conductor layer, the second conductor layer, and the plurality of via conductors. Wiring patterns contained in each of the first conductor layer and the second conductor layer, and the plurality of via conductors configure a coil around the magnetic material. The coil extends in a direction that intersects a stacked direction of the wiring substrate.
When an inductor is configured on a conductive substrate, such as a doped silicon substrate, it is effective to place an aperture direction of a magnetic flux of a helical coil parallel to the substrate so as not to deteriorate the Q value. In other words, the magnetic flux generated by the coil does not penetrate the substrate, which is able to reduce loss due to an eddy current. However, when the inductor is made into a component and is placed on a circuit board, together with an element, such as a conductive material or another electronic component, when an LC composite component, such as an LC filter or an impedance matching circuit, is provided by combining the inductor with a capacitor, problems to be described below arise.
When a helical coil is produced like the coil component disclosed in the '756 Application and the '454 Application, the helical coil is provided along a surface parallel to a surface of the substrate. However, when other electronic components are adjacently provided near an aperture of the helical coil, an eddy current due to a magnetic field of the helical coil is generated at a conductor portion of this electronic component, which deteriorates the electrical characteristics of the composite component.
In addition, when an LC composite component, such as an LC filter or an impedance matching circuit, is provided by combining the inductor with a capacitor, problems described below arise.
When a helical coil is produced like the coil component disclosed in the '756 Application and the '454 Application, either the top surface or the bottom surface parallel to the surface of the substrate is a start end or a termination end. However, when internal wiring electrically connected to a terminal or another element is provided near the aperture of the helical coil, the eddy current due to the magnetic field is generated in the internal wiring, which deteriorates the electrical characteristics of the composite component.
In view of the foregoing, exemplary embodiments of the present disclosure, in an electronic component having a helical coil in which an aperture direction of a magnetic flux of the helical coil is placed parallel to a substrate, provide an electronic component configured to reduce a size of an electronic device on which the electronic component having the helical coil and other elements are mounted even when being mounted together with an element, such as another conductive material or an electronic component.
In addition, exemplary embodiments of the present disclosure are directed to provide a small electronic component including internal wiring together with an inductor having a predetermined inductance.
An electronic component as one example of the present disclosure includes a substrate, an insulator layer on at least a portion of a surface of the substrate, an inductor in the insulator layer, one or more planar conductors at the substrate or in the insulator layer and extending along the substrate, and one or more connecting conductors electrically connected to the one or more planar conductors. In this aspect, the inductor includes a plurality of surface direction conductors each extending in a plurality of layers along the surface of the substrate, and a plurality of inductor via conductors to connect the plurality of surface direction conductors extending in different layers among the plurality of layers. The inductor is provided by a helical coil having a winding axis along the surface of the substrate, and a direction of a current flowing through an inductor via conductor among the plurality of inductor via conductors that is adjacent to the one or more connecting conductors and a direction of a current flowing through the one or more connecting conductors are opposite to each other.
According to the exemplary aspects of the present disclosure, in an electronic component having a helical coil in which an aperture direction of a magnetic flux of the helical coil is placed parallel to a substrate, an electronic component is provided that is configured to reduce a size of an electronic device on which the electronic component having the helical coil and other elements are mounted when being mounted together with an element such as another conductive material or an electronic component. Moreover, a small electronic component including internal wiring together with an inductor having a predetermined inductance is also provided.
Hereinafter, a plurality of exemplary embodiments will be described with reference to the attached drawings and several specific examples. In the drawings, components and elements assigned with the same reference numerals or symbols will represent identical components and elements. While an exemplary embodiment is divided and described into a plurality of exemplary aspects for the sake of convenience in consideration of ease of description or understanding of main points, elements described in different exemplary embodiments can be partially replaced or combined with each other as would be appreciated to one skilled in the art. In the second and subsequent exemplary embodiments, a description of features common to the first exemplary embodiment will be omitted, and only different features will be described. In particular, the the same same advantageous functions and effects by configurations will not be described one by one for each exemplary embodiment.
As shown, the electronic component 101 includes a substrate 1, an insulator layer 2 provided along at least a portion of a surface of the substrate 1, and an inductor provided in the insulator layer 2. In addition, the electronic component 101 includes planar conductor connecting conductors 7A, 7B, and 7C electrically connected to a planar conductor 3 provided on the substrate 1 and extending along the substrate 1, and a planar conductor connecting conductor 8 electrically connected to a planar conductor 4 extending along the substrate 1. For purposes of this disclosure, the planar conductor connecting conductor 7A, 7B, 7C, and 8 corresponds to a “connecting conductor”.
The inductor includes a plurality of surface direction conductors 5A and 5B each extending in a plurality of layers (two layers in this example) along the surface of the substrate 1 (e.g., parallel to the surface of substrate 1), and a plurality of inductor via conductors 6 that connect the surface direction conductors 5A and 5B extending in different layers among the plurality of layers. The inductor is formed as an inductor by a helical coil having a winding axis WA along the surface of the substrate 1. That is, the winding axis WA extends in a direction parallel to the surface of substrate 1.
The planar conductor connecting conductors 7A, 7B, 7C, and 8 are positioned at an end portion (e.g., a coil aperture of a helical coil) in a direction of the winding axis of the helical coil.
In the exemplary aspect, the planar conductors 3 and 4 are configured as capacitor electrodes. In short, the planar conductors 3 and 4, and the dielectric layer 11 interposed between these planar conductors 3 and 4 configure a capacitor.
In such a manner, the planar conductors 3 and 4 are provided at positions closer to the substrate 1 than to the plurality of surface direction conductors 5A and 5B. According to this structure, the inductor by the helical coil configured by the plurality of surface direction conductors 5A and 5B and the plurality of inductor via conductors 6 is positioned near terminal electrodes 9A and 9B. Therefore, a path from a circuit to the inductor is minimized, and the Q value of the inductor is kept high. In addition, the capacitor electrodes are able to be placed so as to overlap in an area in which the coil is provided, which also saves space.
A direction of a current flowing through an inductor via conductor 6 among the plurality of inductor via conductors 6 that is adjacent to the planar conductor connecting conductors 7A, 7B, and 7C and a direction of a current flowing through the planar conductor connecting conductors 7A, 7B, and 7C are opposite to each other. In addition, a direction of a current flowing through an inductor via conductor 6 adjacent to the planar conductor connecting conductor 8 and a direction of a current flowing through the planar conductor connecting conductor 8 are opposite to each other. This will be described below with reference to
In an exemplary aspect, the substrate 1 is a silicon substrate, for example, and the planar conductor 3 of a thin film such as polysilicon or Al is provided on the surface of this substrate 1. The dielectric layer 11 that can be formed by SiO2, SiN, or the like, is provided in a predetermined region of an upper surface of the planar conductor 3. The planar conductor 4 of a thin film such as polysilicon or Al is provided on a surface of this dielectric layer 11.
The surface direction conductor 5A and the terminal electrodes 9A and 9B are provided on the surface of the insulator layer 2. The planar conductor 3 is electrically connected to the terminal electrode 9B through the planar conductor connecting conductors 7A, 7B, and 7C. In addition, the planar conductor 4 is electrically connected to the surface direction conductor 5B through the planar conductor connecting conductor 8.
In such a manner, the planar conductor connecting conductor is configured by three portions of the planar conductor connecting conductors 7A, 7B, and 7C. The planar conductor connecting conductor 7B among the planar conductor connecting conductors 7A, 7B, and 7C is provided on the same layer as a layer in which the surface direction conductor 5B is provided. The planar conductor connecting conductor 7B is provided during a step of forming this surface direction conductor 5B. Therefore, a step of forming a special conductor pattern is unnecessary, the special conductor pattern reversing to each other the direction of a current flowing through the inductor via conductor 6 adjacent to the surface direction conductors 5A and 5B among the plurality of inductor via conductors 6 and the direction of a current flowing through the planar conductor connecting conductor 7C.
This electronic component 101, as shown in
It is noted that, when the planar conductors 3 and 4 shown in
In such a manner, the electronic component in which the inductor and the capacitor are connected in series can be configured to be used as a frequency filter or an impedance matching circuit.
First, a comparative example of the electronic component 101 is according to the present exemplary embodiment.
On the other hand,
In the electronic component 101, among the plurality of inductor via conductors 6, the direction of a current flowing through the inductor via conductor (i.e., the inductor via conductor 6 at a right end among the three inductor via conductors 6 at the upper portion in the direction shown in FIG. 3A) adjacent to the planar conductor connecting conductors 7A, 7B, and 7C and the direction of a current flowing through the planar conductor connecting conductors 7A, 7B, and 7C are opposite to each other. Accordingly, in comparison with the example shown in
It is noted that, in the electronic component 101 according to the present exemplary embodiment, the direction of a current flowing through the inductor via conductor (i.e., the inductor via conductor 6 at the right end of the two inductor via conductors 6 at the lower portion in the direction shown in
Although the expansion of the magnetic flux φ is large in the electronic component 301 as a comparative example, the expansion of the magnetic flux φ is significantly reduced in the electronic component 101 according to the present exemplary embodiment. This configuration enables a distance d1 between the electronic component 101 and the different member 201 to be smaller than a distance d2 shown in
On the other hand,
Although the expansion of the magnetic flux φ is large in the electronic component 311 as a comparative example, the expansion of the magnetic flux φ is significantly reduced in the electronic component 1 according to the present exemplary embodiment. This configuration enables a distance d1 between the helical coil and the different member 21 to be smaller than the distance d2 of the comparative example, which makes it possible to provide a small electronic component 111.
Although the first exemplary embodiment shows an example in which the inductor via conductors 6 are arranged in two rows, the planar conductor connecting conductors 7A, 7B, and 7C are positioned along with the end portion of one of the two rows of the inductor via conductors 6, and the planar conductor connecting conductor 8 is positioned along with the end portion of the other row, the number of rows of the inductor via conductors 6 is not limited to two in alternative exemplary aspects. In addition, even when the planar conductor connecting conductor 8 is not positioned along with the end portion of all rows, the expansion of the magnetic flux φ can be significantly reduced.
Although, in the example shown in
In the example shown in
It is noted that a high-frequency magnetic field generated by the helical coil may generate an eddy current in the planar conductors 3 and 4. However, as shown in
In addition, in the electronic component shown in the first exemplary embodiment, the planar conductor 3 is provided not only in a portion in which a capacitor is provided, but it is also provided over substantially the entire surface of the substrate 1. Therefore, the electromagnetic shielding property of a member below the substrate 1 or a circuit is also provided.
In a second exemplary embodiment, an electronic component different in the configuration of the terminal electrode from the example shown in the first exemplary embodiment will be described.
As shown, the electronic component 102 includes a substrate 1, an insulator layer 2 provided along a surface of the substrate 1, an inductor provided in the insulator layer 2, planar conductors 3 and 4 provided on the substrate 1 and extending along the substrate 1, planar conductor connecting conductors 7A, 7B, and 7C electrically connected to the planar conductor 3, and a planar conductor connecting conductor 8 electrically connected to a planar conductor 4.
Terminal electrodes 10A and 10B are provided on the surface of the insulator layer 2. The terminal electrodes 10A and 10B are electrically connected to the terminal electrodes 9A and 9B. Although, in the electronic component 101 shown in the first exemplary embodiment, as shown in
Subsequently, method of manufacturing the electronic component 102 will be described.
It is noted that, in this second exemplary embodiment, even when the terminal electrodes 9B and 10B are large, the high-frequency magnetic field generated by the helical coil effectively avoids the terminal electrodes 9B and 10B. Accordingly, the loss due to the eddy current is significantly reduced, and the deterioration of the Q value of the inductor by the helical coil is significantly reduced. The same applies to the other exemplary embodiments to be described below.
In a third exemplary embodiment, an electronic component different in the configuration of the planar conductor from the example shown in the first and second exemplary embodiments will be described.
As shown, the electronic component 103 includes a substrate 1, an insulator layer 2 provided along a surface of the substrate 1, an inductor provided in the insulator layer 2, a planar conductor 4 provided on the substrate 1 and extending along the substrate 1, planar conductor connecting conductors 7A, 7B, and 7C electrically connected to the planar conductor 4, and a planar conductor connecting conductor 8 electrically connected to the planar conductor 4.
As further shown in the X2 cross-sectional view, the dielectric layer 11 is provided on the surface of the substrate 1. The planar conductor 4 is provided on the surface of the dielectric layer 11. In addition, as shown in the X1 cross-sectional view, a substrate conduction electrode 12 is formed at a predetermined position on the surface of the substrate 1. According to an exemplary aspect, the substrate 1 is a highly conductive semiconductor substrate, or a semiconductor substrate at which a highly conductive layer is provided on the surface on which each layer is provided. It should be appreciated that other configurations are preferably the same or substantially the same as the configurations shown in the second exemplary embodiment.
Subsequently, a method of manufacturing the electronic component 103 will be described.
It is noted that each process step shown from
As described above, the present disclosure is also applicable when the substrate is used as a portion of the planar conductor for a capacitor.
A fourth exemplary embodiment illustrates an electronic component in which the planar conductor configures a semiconductor element, together with a semiconductor substrate.
In an exemplary aspect, the substrate 1 is a P-type silicon semiconductor substrate, an N-well 13 is provided in a predetermined place of this substrate 1, and a P+ region 14 is provided in a predetermined region in the N-well.
The substrate conduction electrode 12 is provided on a surface of a region of the N-well 13. In addition, a substrate conduction electrode 15 is provided on a surface of the P+ region. According to this structure, the N-well 13, the substrate conduction electrode 12 electrically connected to the N-well 13, the P+ region 14, and the substrate conduction electrode 15 electrically connected to the P+ region 14 configure a diode.
With the above configuration, the electronic component 104 is configured to function as an electronic component in which the diode is connected in series to the inductor by the helical coil. For example, the electronic component 104 can be configured as an ESD protection element.
It is noted that, although the diode is configured on the substrate 1 in the example shown in
Finally, it is noted that the exemplary aspects of the present disclosure are not limited to the foregoing exemplary embodiments. Various modifications or changes can be appropriately made by those skilled in the art. Furthermore, the scope of the present invention is intended to include all possible modifications or changes from the exemplary embodiments.
The configuration of the electronic component of the present disclosure will be described below.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-105968 | Jun 2022 | JP | national |
The present application is a continuation of International Application No. PCT/JP2023/023730, filed Jun. 27, 2023, which claims priority to Japanese Patent Application No. 2022-105968, filed Jun. 30, 2022, the entire contents of each of which are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/023730 | Jun 2023 | WO |
| Child | 18987891 | US |
