Patent Grant
9673311
The present disclosure relates to electronic devices, and more particularly to, electronic devices that include high-electron mobility transistors having at least two channel layers.
High electron mobility transistors (HEMTs) can have a two dimensional electron gas (2DEG) with a relatively low resistivity, and such resistivity can be affected by the amount of aluminum within and AlGaN barrier layer. As the Al content increases, the resistivity becomes lower. However, when the Al content is too high, more strain can result, thus increasing the risk of wafer breakage and inverse piezo-electric effect. Alternatively, an AlN spacer has been proposed, but obtaining a good ohmic contact can be difficult to obtain.
Embodiments are illustrated by way of example and are not limited in the accompanying figures.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.
The following description in combination with the figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other embodiments can be used based on the teachings as disclosed in this application.
The term “compound semiconductor” is intended to mean a semiconductor material that includes at least two different elements. Examples include SiC, SiGe, GaN, InP, AlvGa(1-v)N, CdTe, and the like. A III-V semiconductor material is intended to mean a semiconductor material that includes at least one trivalent metal element and at least one Group 15 element. A III-N semiconductor material is intended to mean a semiconductor material that includes at least one trivalent metal element and nitrogen. A Group 13-Group 15 semiconductor material is intended to mean a semiconductor material that includes at least one Group 13 element and at least one Group 15 element.
The term “carrier impurity” is intended to mean (1) when an acceptor, an impurity within a compound having a different valence state as compared to at least 90% of all cations within the compound, or (2) when a donor, an impurity within a compound having a different valence as compared to at least 90% of all anions within the compound. For example, C, Mg, and Si are acceptors with respect to GaN because they can trap electrons. As used herein, Al is not a carrier impurity with respect to GaN because Al and Ga have a 3+ valence. A carrier impurity may be intentionally added or may be present as a naturally occurring impurity or as a consequence of forming a layer that includes the impurity. Acceptors and donors are carrier impurities of opposite carrier types.
Although a layer or a region may be described herein as a donor impurity type or an acceptor impurity type, skilled artisans understand that the impurity types can be reversed and are also possible in accordance with the present description.
Unless stated explicitly to the contrary, the terms “carrier impurity concentration” or “concentration of a carrier impurity”, when referring to a layer, a film, or a region, is intended to mean an average concentration for such layer, film, or region.
For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles.
The terms “on,” “overlying,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. However, “over” may also mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is above another element but the elements do not contact each other and may have another element or elements in between the two elements.
Group numbers corresponding to columns within the Periodic Table of Elements based on the IUPAC Periodic Table of Elements, version dated Jan. 21, 2011.
The term “normal operation” and “normal operating state” refer to conditions under which an electronic component or device is designed to operate. The conditions may be obtained from a data sheet or other information regarding voltages, currents, capacitances, resistances, or other electrical parameters. Thus, normal operation does not include operating an electrical component or device well beyond its design limits.
The term “high voltage,” with reference to a layer, a structure, or a device, means that such layer, structure, or device can withstand at least 150 V difference across such layer, structure, or device (e.g., between a source and a drain of a transistor when in an off-state) without exhibiting dielectric breakdown, avalanche breakdown, or the like.
The terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited only to those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive-or and not to an exclusive-or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
Also, the use of “a” or “an” is employed to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one, at least one, or the singular as also including the plural, or vice versa, unless it is clear that it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for that more than one item.
The use of the word “about”, “approximately”, or “substantially” is intended to mean that a value of a parameter is close to a stated value or position. However, minor differences may prevent the values or positions from being exactly as stated. Thus, differences of up to ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) for the value are reasonable differences from the ideal goal of exactly as described.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.
An electronic device can include a HEMT include a first channel layer and a second channel layer overlying the first channel layer. In an embodiment, a first semiconductor layer overlies the first channel layer, wherein the first semiconductor layer has a first aluminum content that is at least 10% of a total metal content of the first semiconductor layer. A second semiconductor layer overlies the second channel layer, wherein the second semiconductor layer has a second aluminum content that is greater than the first aluminum content. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, the first channel layer has a first pinch-off voltage, and the second channel layer has a second pinch-off voltage. An absolute value of a difference between the first and second pinch-off voltages is greater than 1 V. The difference in pinch-off voltage can allow a HEMT to have current for at least one channel layer can be turned off or turned on without significantly affecting current flow for an adjacent channel layer.
The concepts and design considerations are better understood after reading the embodiments that follow. Much of the description below will address GaN as the material of the channel layer as a specific example in order to simplify understanding of the concepts and design considerations. Clearly, embodiments of the present invention are not limited to a GaN channel layer. After reading the specification in its entirety, skilled artisans will appreciate that the embodiments are merely for illustrative purposes and do not limit scope of the appended claims.
A first set of embodiments are directed to an electronic device that includes a HEMT having two channel layers. Embodiments with more than two channel layers can be used and will be addressed later in this specification. After reading the specification, skilled artisans will be able to use the concepts described with respect to two channel layers and apply such concepts to HEMTs having more than two channel layers.
The buffer layer 106 can help to epitaxially grow the overlying layers 122, 124, 142, and 144. The composition of the buffer layer 106 may depend on the composition of the lower channel layer 122. In an embodiment, the lower channel layer 122 includes GaN, and the buffer layer 106 includes AlGaN. The composition of the buffer layer 106 can be changed as a function of thickness, such that the buffer layer 106 has a relatively greater aluminum content closer to the substrate 102 and a relatively greater gallium content closer to the lower channel layer 122. In a particular embodiment, the cation (metal atoms) content in the buffer layer 106 near the substrate 102 can be 10% to 100% Al with the remainder Ga, and the cation content in the buffer layer 106 near the lower channel layer 122 can be 0% to 50% Al with the remainder Ga. The buffer layer 106 can have a thickness in a range of approximately 1 micron to 10 microns.
The lower and upper channel layers 122 and 142 can include a monocrystalline compound semiconductor material. The lower channel layer 122 may include a compound semiconductor material that is the same or different from the upper channel layer 142. In an embodiment, the upper channel layer 142 may allow for a higher Al content if needed or desired as compared to the lower channel layer 122. The lower channel layer 122 can include AlaGa(1-a)N, wherein 0≦a≦0.1, and the upper channel layer 142 can include AlcGa(1-c)N, wherein 0≦c≦0.15. In a particular embodiment, either or both of the lower and upper channel layers 122 and 142 include GaN (in the prior formulas, a=0 and c=0).
The lower channel layer 122 may have a sufficient thickness to reduce the likelihood that electrons from the 2DEG would become trapped in the buffer layer 106. The lower channel layer 122 can have a thickness in a range of 11 nm to 1000 nm, and in a particular embodiment, is in a range of 120 nm to 250 nm. A two dimensional hole gas (2DHG) can form along the interface between the upper channel layer 142 and the lower semiconductor layer 124. The upper channel layer 142 is further from the buffer layer 106, and therefore, the upper channel layer 142 can be thinner than the lower channel layer 122. The upper channel layer may have a thickness in a range of 10 nm to 200 nm, and in a particular embodiment, is in a range of 20 nm to 80 nm.
In an embodiment, current flowing along the upper channel layer 142 may be higher than current flowing along the lower channel layer 122. The current associated with each of the channel layers 122 and 142 can be affected by the Al content within the semiconductor layers 124 and 144. The lower semiconductor layer 124 may have a lower Al content as compared to the upper semiconductor layer 144, so that more current flows along the upper channel layer 142, as compared to the lower channel layer 122. In an embodiment, the lower semiconductor layer 124 may include at least 10% Al to allow for sufficient current. In an embodiment, the lower semiconductor layer 124 includes AlbGa(1-b)N, wherein 0.10≦b≦0.30. More Al content in the upper semiconductor layer 144 allows for higher current; however, too much Al content may cause too much strain within the device. In an embodiment, the upper semiconductor 144 includes AldGa(1-d)N, wherein 0.15≦d≦0.35. The semiconductor layers 124 and 144 can have a thickness in a range of 10 nm to 40 nm. The semiconductor layers 124 and 144 can have the same or different thicknesses.
The layers 122, 124, 142, and 144 can be formed using an epitaxial growth technique, and thus the layers 122, 124, 142, and 144, and at least a portion of the buffer layer 106 can be monocrystalline. In a particular embodiment, the layers 122, 124, 142, and 144 can be formed using metalorganic chemical vapor deposition.
The passivation layer 160 allows for better surface passivation of the upper semiconductor layer 144 and limits the amount of charge trapped at the interface. In an embodiment, the passivation layer is formed before the upper semiconductor layer 144 is exposed to air, O2, H2O, or another reactive gas. The passivation layer can include a gate dielectric film 162, an intermediate film 164, and a capping film 166. In an embodiment, the gate dielectric film 162 can include a silicon nitride, an aluminum oxide, a zirconium oxide, a hafnium oxide, a niobium oxide, another suitable gate dielectric material, or any combination thereof and have a thickness in a range of 5 nm to 40 nm. The intermediate film 164 can act as an etch-stop layer when etching the capping film 166. In an embodiment, the intermediate film 164 can include AlN and have a thickness in a range of 2 nm to 20 nm. The capping film 166 can protect the gate dielectric film 162. In an embodiment, the capping film 166 can include silicon nitride and have a thickness in a range of 20 nm to 500 nm. In another embodiment, the passivation layer 160 can include fewer or more films that may have the same or different compositions as described. When the intermediate film 164 includes AlN, an optional Al2O3 film (not illustrated) can be formed by oxidizing a portion of the intermediate film 164 in an oxidizing ambient, such as O2, N2O, or the like. The passivation layer 160 or any films of the passivation layer 160 can be formed using a chemical or physical vapor technique.
In an embodiment, a first patterned resist layer can be used in patterning layers 162, 164, and 166 to form the portions 2224 and 2244 for the upper channel layer 142, and a second patterned resist layer can be used in patterning layers 142, 144, 162, 164, and 166 to form the portions 2222 and 2242 for the lower channel layer 122. In another embodiment, the sequence may be reversed. In a further embodiment, a patterned resist layer can be used in patterning layers 162, 164, and 166 to form the portions 2224 and 2244 for the upper channel layer 142. A sacrificial sidewall spacer (not illustrated) may be formed within the partially formed contact openings 222 and 224, and the layers 142 and 144 can be patterned within the opening as defined by the base of the sacrificial sidewall spacer.
The sacrificial sidewall spacers can then be removed. In the embodiment illustrated in
Another patterned resist layer can be used to etch a portion of the passivation layer 160 to form the gate electrode opening 226. The gate electrode opening 226 can extend through the capping film 166 to the intermediate film 164. In another embodiment, the gate electrode opening 226 can extend through the capping film 166 and the intermediate film 164. In another embodiment, the passivation layer 160 can be a single layer, effectively corresponding to a combination of the gate dielectric film 162 and the capping film 166. The etch can be performed to extend the opening such that a portion of the single film remains below the gate electrode opening 226 and has a thickness as previously described with respect to the gate dielectric film 162.
The openings 222, 224, and 226 can be formed by etching. When etching a layer or film that includes Al, the etching can be performed using reactive ion etching with a chlorine-containing gas, such as Cl2, BCl3, HCl, or the like. When etching a layer of film that includes silicon nitride, the etching can be performed using reactive ion etching with a fluorine-containing gas, such as SF6, CHF3, CF4, or the like. The etching can be performed as a timed etch, using endpoint detection, or a combination of endpoint detection along with a timed overetch.
In
The source and drain electrodes 322 and 324 and the gate electrode 326 can be formed by depositing conductive layer over the workpiece. The conductive layer can have a composition selected to provide a proper work function for the transistor being formed. The conductive layer can include Ti, TiN, Al, Pd, Pt, W, Au, Ni, or a stack or any combination thereof. In another embodiment, the conductive layer is typically at least 50 wt % aluminum, copper, a noble metal, or an alloy of any of the foregoing. The conductive layer has a thickness in a range of 50 nm to 500 nm. The conductive layer is patterned to form the source electrode 322, the drain electrode 324, and the gate electrode 326.
In an alternative embodiment, the source and drain contact openings 222 and 224 and source and drain electrodes 322 and 324 can be formed before forming the gate electrode opening 226 and gate electrode 326.
In
In
Processing is continued to form a substantially completed device. One or more insulating layers and levels of interconnects can be formed if needed or desired. The source, gate, and drain shielding plates control better electrical fields within the layers 122, 124, 142, and 144, provide a higher blocking voltage when the HEMT is off, reduce parasitic drain-to-gate capacitance, or other similar electronic properties. A passivation layer (not illustrated) may be formed over the uppermost level of interconnects.
The HEMT as illustrated in
At Vgs of 0 V, Id is approximately 0.11 A/mm to approximately 0.13 A/mm. The pinch-off of 2DEG for the upper channel layer 142 occurs at approximately −7 V to approximately −8V, as noted by oval 620 in
ΔVPO=|VPOUC−VPOLC| Equation 1
where,
ΔVPO is the absolute value of difference in pinch-off voltages;
ΔVPOUC is the pinch-off voltage of 2DEG for the upper channel layer 142; and
ΔVPOLC is the pinch-off voltage of 2DEG for the lower channel layer 122.
Such a difference in pinch-off voltages between the 2DEGs for the channel layers 122 and 142 allow current flow along the upper channel layer 142 to be pinched off and still allow current flow along the lower channel layer 122 with reasonable control. The ΔVPO can be greater than 1 V. In an embodiment, ΔVPO is at least 2 V, 3 V, 4 V, or even higher. Conventional double channel HEMTs have ΔVPO not greater than 1 V, and typically is significantly lower. Accordingly, conventional double channel HEMTs do not allow for the ability to control the device, such that current for the upper channel layer can be turned off separate from the lower channel layer.
An electronic device can include a HEMT having more than two channel layers. The amount of current that can flow through the HEMT can increase as the number of channel layers increases. The semiconductor layers between the channel layers of the HEMT can have an Al content that increases with the distance from the substrate. Vgs will have a magnitude further from 0 V as the number of channels increase. For a depletion-mode transistor, a more negative Vgs is needed to turn off all channel layers within the HEMT. The ability to turn off current to individual channel layers may become more difficult as ΔVPO between two adjacent channel layers may be less than 1 V.
In another embodiment, a HEMT can be an enhancement-mode transistor with at least two channel layers. The previous description of pinch-off voltages with respect to a depletion-mode transistor can apply to threshold voltages for the enhancement-mode transistor. When the HEMT is an enhancement-mode transistor, when Vgs is between the threshold voltage of an upper channel layer and the threshold voltage for a lower channel layer, current can flow along the upper channel layer without significant current flowing along the lower channel layer.
Embodiments as described herein can help to form a HEMT with at least two channel layers wherein current for at least one channel layer can be turned off or turned on without significantly affecting current flow for an adjacent channel layer. In an embodiment, the proper selection of Al content of semiconductor layers adjacent to channel layers can allow ΔVPO of greater than 1 V, and in many embodiments, higher can allow for the ability to selectively pinch-off 2DEG for different channel layers.
The stepped source and drain electrodes allow the contact resistance for each of the channel layers to be relatively low, as compared to source and drain electrodes that contact only a side of a particular channel layer. For example, if the source and drain electrodes only included the deeper portions, contact to the upper channel layer would be only along a side of the upper channel layer, and the contact resistance may be too high and adversely affect on-state resistance RDSON. The stepped source and drain electrodes help to reduce RDSON.
Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are only illustrative and do not limit the scope of the present invention. Embodiments may be in accordance with any one or more of the embodiments as listed below.
An electronic device comprising:
The electronic device of Embodiment 1, wherein the first channel layer has a first pinch-off voltage; the second channel layer has a second pinch-off voltage; and an absolute value of a difference between the first and second pinch-off voltages is greater than 1 V.
The electronic device of Embodiment 1, wherein the first channel layer includes AlaGa(1-a)N, wherein 0≦a≦0.1; the first semiconductor layer includes AlbGa(1-b)N, wherein 0.10≦b≦0.30; the second channel layer includes AlcGa(1-c)N, wherein 0≦c≦0.15; and the second semiconductor layer includes AldGa(1-d)N, wherein 0.15≦d≦0.35;
The electronic device of Embodiment 3, wherein a=0, and c=0.
The electronic device of Embodiment 1, further comprising a substrate and a buffer layer overlying the substrate, wherein the buffer layer is disposed between the substrate and the first channel layer.
The electronic device of Embodiment 5, wherein the first channel layer is thicker than the second channel layer and has a thickness of at most 1000 nm.
The electronic device of Embodiment 1, wherein the electronic device comprises a high voltage transistor that includes the first and second channel layers.
The electronic device of Embodiment 7, further comprising:
The electronic device of Embodiment 8, wherein the passivation layer comprises a first insulating nitride layer overlying the second semiconductor layer; a III-N layer overlying the first insulating nitride layer; and a second insulating nitride layer overlying the III-N layer.
The electronic device of Embodiment 1, wherein each of the first and second channel layers and the first and second semiconductor layers has a dopant concentration of at most 1×1015 atoms/cm3.
The electronic device of Embodiment 1, further comprising:
An electronic device comprising:
The electronic device of Embodiment 12, further comprising a first semiconductor layer disposed between the first and second channel layers; and a second semiconductor layer overlying the second channel, wherein the first portion extends through the second channel layer and the second semiconductor layer, and the second portion does not extend through the second channel layer or to the first channel and first semiconductor layers.
A process of forming an electronic device comprising a HEMT, comprising:
The process of Embodiment 14, further comprising forming a first semiconductor layer overlying the first channel layer, wherein the first semiconductor layer has a first aluminum content that is at least 10% of a total metal content of the first semiconductor layer; and forming a second semiconductor layer overlying the second channel layer, wherein the second semiconductor layer has a second aluminum content that is greater than the first aluminum content.
The process of Embodiment 14, wherein each of the first and second channel layers has a dopant concentration of at most 1×1015 atoms/cm3.
The process of Embodiment 14, further comprising:
The process of Embodiment 17, further comprising forming a source electrode and a drain electrode, wherein:
The process of Embodiment 14, further comprising forming a passivation layer overlying the second semiconductor layer; and forming a gate electrode over at least a portion of the passivation layer, wherein the gate electrode that is configured to control current flow within the first and second channel layers.
The process of Embodiment 14, further comprising:
Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.
The specification and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The specification and illustrations are not intended to serve as an exhaustive and comprehensive description of all of the elements and features of apparatus and systems that use the structures or methods described herein. Separate embodiments may also be provided in combination in a single embodiment, and conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges includes each and every value within that range. Many other embodiments may be apparent to skilled artisans only after reading this specification. Other embodiments may be used and derived from the disclosure, such that a structural substitution, logical substitution, or another change may be made without departing from the scope of the disclosure. Accordingly, the disclosure is to be regarded as illustrative rather than restrictive.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6028328 | Riechert et al. | Feb 2000 | A |
| 7642567 | Amasuga | Jan 2010 | B2 |
| 7663161 | Kaibara | Feb 2010 | B2 |
| 7906417 | Makiyama | Mar 2011 | B2 |
| 8164115 | Hikita | Apr 2012 | B2 |
| 20060065908 | Beach | Mar 2006 | A1 |
| 20070077745 | He et al. | Apr 2007 | A1 |
| 20090065810 | Honea et al. | Mar 2009 | A1 |
| 20130240911 | Beach | Sep 2013 | A1 |
| 20140264369 | Padmanabhan | Sep 2014 | A1 |
| 20140266324 | Teo et al. | Sep 2014 | A1 |
| 20150263104 | Saito | Sep 2015 | A1 |
| 20150303292 | Shibata | Oct 2015 | A1 |
| 20160043181 | Liu et al. | Feb 2016 | A1 |
| Entry |
|---|
| Arch, D.K. et al., “Superlattice Conduction in Superlattice Modulation-Doped Field-Effect Transistors,” Journal of Applied Physics vol. 61, No. 4, dated Feb. 15, 1987, pp. 1503-1509. |
| Baba, Toshio et al., “High Performance (AlAx/n-GaAs Superlattice)/GaAs 2DEGFETs with Stabilized Threshold Voltage,” Japanese Journal of Applied Physics, vol. 23, No. 8, dated Aug. 1984, pp. L654-L656. |
| Chu, Rongming et al., “AlGaN—GaN Double-Channel HEMTs,” IEEE Transactions on Electron Devices, vol. 52, No. 4, dated Apr. 2005, pp. 438-446. |
| Guo, Jia et al., “Ultra-Scaled AlN/GaN Enhancement-&, Depletion-Mode Nanoribbon HEMTs,” ISDRS, dated Dec. 9-11, 2009, 2 pages. |
| Howell, Robert S. et al, “The Super-Lattice Castellated Field Effect Transistor (SLCFET): A Novel High Performance Transistor Topology Ideal for RF Switching,” IEDM Technical Digest, dated 2014, pp. 291-294. |
| Palacios, Tomás et al., “Use of Double-Channel Heterostructures to Improve the Access Resistance and Linearity in GaN-Based HEMTs,” IEEE Transactions on Electron Deviced, vol. 53, No. 3, dated Mar. 2006, pp. 562-565. |
| Si, Quan et al., “AlGaN/GaN Double-Channel HEMT,” Journal of Semiconductors, vol. 31, No. 4, dated Apr. 2010, pp. 044003-1-044003-3. |
