Microelectronic devices, such as semiconductor devices, are fabricated on and/or in wafers or workpieces. A typical wafer plating process involves depositing a metal seed layer onto the surface of the wafer via vapor deposition. A photoresist may be deposited and patterned to expose the seed layer. The wafer is then moved into the vessel of an electroplating processor where electric current is conducted through an electrolyte to the wafer, to apply a blanket layer or patterned layer of a metal or other conductive material onto the seed layer. Examples of conductive materials include permalloy, gold, silver, copper, cobalt, tin, nickel, and alloys of these metals. Subsequent processing steps form components, contacts and/or conductive lines on the wafer.
In many or most applications, it is important that the plated film or layer(s) of metal have a uniform thickness across the wafer or workpiece. Some electroplating processors use a current thief, which is an electrode having the same polarity as the wafer. The current thief operates by drawing current away from the edge of the wafer. This helps to keep the plating thickness at the edge of the wafer more uniform with the plating thickness over the rest of the wafer. The current thief may be a physical electrode close to the edge of the wafer. Alternatively the current thief may be a virtual current thief, where the physical electrode is remote from the wafer. In this design, current from the remote physical electrode is conducted through electrolyte to positions near the wafer.
Electroplating processes in wafer level packaging and other applications are diverse with variations in process and wafer patterns. Significant plating non-uniformities often occur along the edge of the wafer pattern. Nonuniformities can be causes by irregularities in the electric field due to pattern variations or by mass-transfer non-uniformities near the wafer edge.
Some electroplating processors use a paddle or an agitator to agitate the electrolyte and increase mass transfer of metal ions in the electrolyte onto the wafer, which can also improve plating uniformity. However, electric field shields in the vessel can protrude between the wafer and the paddle, which can reduce agitation of the electrolyte and degrade plating uniformity near the edges of the wafer. Electric field shields may also have to be removed and replaced with alternative field shields of different sizes to meet the requirements of electroplating different types of wafers. This is time consuming and also requires keeping an inventory of multiple field shields.
Accordingly, engineering challenges remain in designing electroplating processors.
An electroplating system has a vessel assembly holding an electrolyte. A weir thief electrode assembly in the vessel assembly includes a plenum divided into at least a first and a second virtual thief electrode segment. The plenum has a plurality of spaced apart openings through which thief currents flow to improve the electric field around the edge of the wafer. A weir ring on the weir thief electrode assembly guides the current flow. First and second physical thief electrodes are electrically connected to separate power sources, and are in electrical continuity with the first and second virtual thief electrode segments, respectively.
In the drawings, the same reference number indicates the same element in each of the views.
As shown in
Turning to
Referring still to
An upper cup 60, also made of a dielectric material, is positioned on top of the lower cup. The upper cup 60 has rings and chambers corresponding to, and aligned over the rings and chambers of the lower cup 68. A vessel membrane 62 between the lower cup 68 and the upper cup 60 passes electric current while preventing movement of electrolyte or particles. The upper cup 60 and the membrane 62 form a vessel or bowl for holding an electrolyte, specifically catholyte. The lower cup 68 holds a second electrolyte, specifically anolyte, separated from the catholyte by the membrane 62.
During processing, the paddle actuator 56 moves the paddle 54 to agitate the catholyte contained in the upper cup 60. The paddle moves back and forth within a paddle travel dimension, with an oscillating motion. For some applications the paddle may use other movements, such as start/stop, stagger, etc. The tiered drain rings in the rinse assembly 28, if used, are connected to drain and vacuum facilities via one or more the drain fittings 42 and aspiration fittings 44 shown in
Referring to
Turning to
Referring still to
Segments AA and CC may both subtend a sector of 130 to 150 degrees and nominally 140 degrees. Segment BB may subtend a sector of 70 to 90 degrees and nominally 80 degrees. Segment DD is a local narrow sector subtending 1 to 15 degrees and nominally 10 degrees, and may be fit in between the ends of the two adjacent segments AA and CC.
Holes 145 through the plane section 106 are aligned on a diameter of the plenum which is greater than the inner diameter of the weir ring. The openings 145 allow the virtual thief electrode segments to influence the electric field in the vessel assembly primarily near the edges of the wafer, by providing a current flow pathway from the catholyte in the plenum 146 into the upper cup 60. Alternatively, slots 147 adjoining the weir ring 104 as shown in dotted lines in
For processing 300 mm wafers with plated areas extending out to 297 or 298 mm (i.e., within 1 or 1.5 mm of the wafer edge) the weir ring 104 may have an inside diameter of 298 mm. In the example shown, the seal on the contact ring in the head is at least two millimeters from the edge of the wafer and the first plated feature often begins even further in from the seal. Thus, the weir ring 104 does not reside beneath the plated film. It therefore does not interfere with the range of paddle movement or block mass transfer to the edge of the plated film. The weir ring 104 operates to direct flow rather than act as an electric field shield. For smaller wafers, or for wafers with all plated areas further in from the wafer edge, a weir ring 104 having a smaller inside diameter may be used.
Referring to
As also shown in
Second and fourth thief electrolytes (second and fourth thiefolytes) are similarly contained in second and fourth chambers 127 and 131 in second and fourth electrode cups by second and fourth membranes 133 and 135 shown in
The cross sections of the thief electrode channels 120-123 may also vary based on the current flow requirements of each segment. The diameter of the holes 145 or size of the slots 147 may increase with their distance from catholyte-filled channel providing current to the segment, so that the all of the holes or slots have largely equal influence on the electric field around the edge of pattern or plated metal 200A on the wafer 200, shown in
All four thiefolytes may be the same. The vessel assembly 36 then contains three electrolytes: anolyte in the lower cup 68 of the anode assembly, catholyte in the upper cup 60, the plenum and the thief electrode channels 120-123, and thiefolyte in the thiefolyte chambers 124-127. In some embodiments the thiefolyte may be omitted and replaced with the catholyte. In this case the thiefolyte chambers 124-127 and channel membranes 130-133 may also be omitted. In some embodiments, the theifolyte may be replaced with anolyte.
In addition to the number and configuration of the segments shown in
Turning to
In use, a wafer having a metal seed layer is loaded into the rotor of the head 30. The lift/rotate 34 flips over and lowers the wafer into the vessel assembly 36 until at least the seed layer contacts the catholyte in the upper cup. The head 30 may rotate the wafer to even out uneven plating factors. The paddle actuator 56 moves the paddle 54 underneath the wafer. The power supply 98 provides specified time varying direct (positive) current independently to the first, second and third anodes, 82, 84 and 86 according to a preprogrammed schedule adapted to the specific wafer to be electroplated.
The power supply 98 also provides specified time varying direct (negative) current independently to the first, second, third and fourth physical current thief electrodes, which current flows through the thiefolytes and the catholyte in thief channels of the first, second, third and fourth virtual electrodes. Each virtual thief segment distributes the current circumferentially through a set of variable-sized openings, which may be holes or slots 144 or 145. Catholyte from inlets into the thief channels 120-123, above the thief membranes, flows into the plenum 146 and out the holes 145 in the top of the plenum. Use of the up-facing holes 145 allows trapped bubbles in the catholyte to escape from the plenum 146.
Since current density across the wafer may be controlled by adjusting the current of the anodes and the virtual current thieves, the system 20 can better process wafers over a range of parameters, without the need to replacing fixed shields in the vessel assembly 36, which is a time consuming process. The system 20 can also provide good performance of the entire process via current control.
The design of the virtual thief electrodes forces thief current to pass between lower surfaces of the contact ring in the head and the top surface of the weir ring 104. This causes the effect of the segments AA, BB, CC and DD to be focused near the edge 200A of the wafer 200 shown in
Radial current density control and circumferential current density control may be achieved by adjusting anode and thief currents. Measurements of plating thickness of prior wafer can be used to adjust these currents. Initial currents can be set from a model that uses process conditions as inputs (e.g., bath conductivity of anolyte and catholyte, wafer current, seed resistance, pattern open area, pattern edge exclusion, pattern feature sizes, and intended plating thickness).
The current or voltage supplied by the power supply 98 to each thief segment is independently controlled, for example with a current in the range of 10 mA to 5 A, a current rise time of 100 mS or less, and voltages of −0V to −60V. Current and/or voltage control may be synchronized with wafer position (via control of the motor in the head spinning the rotor) to enable precise circumferential uniformity control of the electroplating at the edge of the wafer. The wafer position may vary with a continuous wafer rotation. The wafer position may include pauses at fixed wafer angular positions or include changes in wafer rotational speed. The current and/or voltage may increase or decrease in time according to wafer position and angular rotation speed. The current and/or voltage may increase or decrease in time according to wafer position and angular rotation speed and based upon deposition thickness measurements of a prior wafer (i.e. feedback control). The current and/or voltage may increase or decrease in time according to wafer position and angular rotation speed and based upon a model or measurements of the local edge pattern density.
The virtual anode channels 120, 121, 122 and 123 extend across the membrane 62, which separates the anolyte from the catholyte. This design is more tolerant of anode current leaks between channels because the anode currents do not approach zero for expected process conditions. This allows introduction of gaps below the membrane 62 at each dividing wall to allow bubbles to pass. Gaps allow current to pass between channels, but these current leaks are small enough that the anode currents can be adjusted to compensate.
The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of the invention. However, other embodiments of the invention may be directed to specific embodiments relating to each individual aspect, or specific combinations of these individual aspects.
The above description of example embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. Numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.
Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention. Additionally, details of any specific embodiment may not always be present in variations of that embodiment or may be added to other embodiments.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
The term “wafer” includes silicon wafers as well as other substrates on which micro-scale features are formed. As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. The terms above or below refer to the direction of gravity with the apparatus in its customary orientation. The invention has now been described in detail for the purposes of clarity and understanding. However, it will be appreciated that certain changes and modifications may be practice within the scope of the appended claims.
This application is a continuation of U.S. application Ser. No. 17/583,004, filed Jan. 24, 2022 and now pending, which is a continuation of U.S. application Ser. No. 16/870,290, filed May 8, 2020, now U.S. Pat. No. 11,268,208. These applications are incorporated herein by reference.
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Number | Date | Country | |
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Parent | 17583004 | Jan 2022 | US |
Child | 18159041 | US | |
Parent | 16870290 | May 2020 | US |
Child | 17583004 | US |