Patent Grant
10306753
Many activities require secure electronic communications. To facilitate secure electronic communications, an encryption/decryption system may be implemented on an electronic assembly or printed circuit board assembly that is included in equipment connected to a communications network. Such an electronic assembly is an enticing target for malefactors since it may contain codes or keys to decrypt intercepted messages, or to encode fraudulent messages. To prevent this, an electronic assembly may be mounted in an enclosure, which is then wrapped in a security sensor and encapsulated with polyurethane resin. A security sensor may be, in one or more embodiments, a web or sheet of insulating material with circuit elements, such as closely-spaced, conductive lines fabricated on it. The circuit elements are disrupted if the sensor is torn, and the tear can be sensed in order to generate an alarm signal. The alarm signal may be conveyed to a monitor circuit in order to reveal an attack on the integrity of the assembly. The alarm signal may also trigger an erasure of encryption/decryption keys stored within the electronic assembly.
Provided herein, in one or more aspects, is a tamper-respondent assembly which includes a circuit board and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure, along with a tamper-respondent electronic circuit structure, facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. The tamper-respondent electronic circuit structure includes one or more tamper-detect circuits, including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The at least one conductive trace includes stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface. An adhesive facilitates securing the enclosure to the circuit board. The adhesive contacts, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.
In another aspect, a tamper-respondent assembly is provided which includes: a circuit board; at least one electronic component to be protected; an enclosure mounted to the circuit board along an enclosure-to-board interface; a tamper-respondent electronic circuit structure; and an adhesive. The at least one electronic component is associated with the circuit board, and the enclosure facilitates enclosing the at least one electronic component within a secure volume. The tamper-respondent electronic circuit structure assists in defining the secure volume, and includes one or more tamper-detect circuits, including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The at least one conductive trace includes stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface. The adhesive secures the enclosure to the circuit board, and contacts, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.
In a further aspect, a fabrication method is disclosed which includes fabricating a tamper-respondent assembly. Fabricating the tamper-respondent assembly includes providing a circuit board, and providing an enclosure mounted to the circuit board along an enclosure-to-board interface, the enclosure facilitating enclosing at least one electronic component coupled to the circuit board within a secure volume. The method further includes providing a tamper-respondent electronic circuit structure that facilitates defining the secure volume. The tamper-respondent electronic circuit structure includes one or more tamper-detect circuits, including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface, and the at least one conductive trace includes stress rise regions to facilitate detecting a tamper event at the enclosure-to-board interface. Further, the method includes securing the enclosure to the circuit board using an adhesive, the adhesive contacting, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure to board interface, including at the stress rise regions of the at least one conductive trace.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting example(s) illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific example(s), while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art for this disclosure. Note further that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components. Also, note that numerous inventive aspects and features are disclosed herein, and unless otherwise inconsistent, each disclosed aspect or feature is combinable with any other disclosed aspect or feature as desired for a particular application, for instance, for establishing a tamper-proof enclosure-to-board interface for a tamper-respondent assembly.
Reference is first made to
In one or more implementations, a tamper-proof electronic package or tamper-respondent assembly, such as depicted, is configured or arranged to detect attempts to tamper with or penetrate into electronic assembly enclosure 110. Accordingly, electronic assembly enclosure 110 also includes, for instance, a monitor circuit which, if tampering is detected, activates an erase circuit to erase information stored within the associated memory, as well as the encryption and/or decryption module within the communications card. These components may be mounted on, and interconnected by, a multilayer circuit board, such as a printed circuit board or other multilayer substrate, and be internally or externally powered via a power supply provided within the electronic assembly enclosure.
In the embodiment illustrated, and as one example only, electronic assembly enclosure 110 may be surrounded by a tamper-detection sensor 120, an encapsulant 130, and an outer, thermally conductive enclosure 140. In one or more implementations, tamper-detection sensor 120 may include a tamper-detection laminate that is folded around electronic assembly enclosure 110, and encapsulant 130 may be provided in the form of a molding. Tamper-detection sensor 120 may include various detection layers, which are monitored through, for instance, a ribbon cable by the enclosure monitor, against attempts to penetrate enclosure 110 and damage the enclosure monitor or erase circuit, before information can be erased from the encryption module. The tamper-detection sensor may be, for example, any such article commercially available or described in various publications and issued patents, or any enhanced article such as disclosed herein.
By way of example, tamper-detection sensor 120 may be formed as a tamper-detection laminate comprising a number of separate layers with, for instance, an outermost lamination-detection layer including a matrix of, for example, diagonally-extending or sinusoidally-extending, conductive or semi-conductive lines printed onto a regular, thin insulating film. The matrix of lines forms a number of continuous conductors which would be broken if attempts are made to penetrate the film. The lines may be formed, for instance, by printing conductive traces onto the film and selectively connecting the lines on each side, by conductive vias, near the edges of the film. Connections between the lines and an enclosure monitor of the communications card may be provided via, for instance, one or more ribbon cables. The ribbon cable itself may be formed of lines of conductive material printed onto an extension of the film, if desired. Connections between the matrix and the ribbon cable may be made via connectors formed on one edge of the film. As noted, the laminate may be wrapped around the electronic assembly enclosure to define the tamper-detection sensor 120 surrounding enclosure 110.
In one or more implementations, the various elements of the laminate may be adhered together and wrapped around enclosure 110, in a similar manner to gift-wrapping a parcel, to define the tamper-detection sensor shape 120. The assembly may be placed in a mold which is then filled with, for instance, cold-pour polyurethane, and the polyurethane may be cured and hardened to form an encapsulant 130. The encapsulant may, in one or more embodiments, completely surround the tamper-detection sensor 120 and enclosure 110, and thus form a complete environmental seal, protecting the interior of the enclosure. The hardened polyurethane is resilient and increases robustness of the electronic package in normal use. Outer, thermally conductive enclosure 140 may optionally be provided over encapsulant 130 to, for instance, provide further structural rigidity to the electronic package.
When considering tamper-proof packaging, the electronic package needs to maintain defined tamper-proof requirements, such as those set forth in the National Institutes of Standards and Technology (NIST) Publication FIPS 140-2, which is a U.S. Government Computer Security Standard, used to accredit cryptographic modules. The NIST FIPS 140-2 defines four levels of security, named Level 1 to Level 4, with Security Level 1 providing the lowest level of security, and Security Level 4 providing the highest level of security. At Security Level 4, physical security mechanisms are provided to establish a complete envelope of protection around the cryptographic module, with the intent of detecting and responding to any unauthorized attempt at physical access. Penetration of the cryptographic module enclosure from any direction has a very high probability of being detected, resulting in the immediate zeroization of all plain text critical security parameters (CSPs).
To address the demands for ever-improving anti-intrusion technology, and the higher-performance encryption/decryption functions being provided, enhancements to a tamper-proof, tamper-evident packaging for one or more electronic components or assemblies are desired.
Numerous enhancements are described herein to, for instance, tamper-proof electronic packages or tamper-respondent assemblies. As noted, the numerous inventive aspects described herein may be used singly, or in any desired combination. Additionally, in one or more implementations, the enhancements described herein may be provided to work within defined space limitations for existing packages.
Disclosed hereinbelow with reference to
As noted, as intrusion technology continues to evolve, anti-intrusion technology needs to continue to improve to stay ahead. In one or more implementations, as noted, the above-summarized tamper-respondent sensor 200 of
In one or more aspects, disclosed herein is a tamper-respondent sensor 200 with circuit lines 201 having reduced line widths Wl of, for instance, 200 μm, or less, such as less than or equal to 100 μm, or even more particularly, in the range of 30-70 μm. This is contrasted with conventional trace widths, which are typically on the order of 250 μm or larger. Commensurate with reducing the circuit line width Wl, line-to-line spacing width Ws 203 is also reduced to less than or equal to 200 μm, such as less than or equal to 100 μm, or for instance, in a range of 30-70 μm. Advantageously, by reducing the line width Wl and line-to-line spacing Ws of circuit lines 201 within tamper-respondent sensor 200, the circuit line width and pitch is on the same order of magnitude as the smallest intrusion instruments currently available, and therefore, any intrusion attempt will necessarily remove a sufficient amount of a circuit line(s) to cause resistance to change, and thereby the tamper intrusion to be detected. Note that, by making the circuit line width of the smaller dimensions disclosed herein, any cutting or damage to the smaller-dimensioned circuit line will also be more likely to be detected, that is, due to a greater change in resistance. For instance, if an intrusion attempt cuts a 100 μm width line, it is more likely to reduce the line width sufficiently to detect the intrusion by a change in resistance. A change in a narrower line width is more likely to result in a detectable change in resistance, compared with, for instance, a 50% reduction in a more conventional line width of 350 μm to, for instance, 175 μm. The smaller the conductive circuit line width becomes, the more likely that a tampering of that line will be detected.
Note also that a variety of materials may advantageously be employed to form the circuit lines when implemented using resistance monitoring. For instance, the circuit lines may be formed of a conductive ink (such as a carbon-loaded conductive ink) printed onto one or both opposite sides of one or more of the flexible layers 202 in a stack of such layers. Alternatively, a metal or metal alloy could be used to form the circuit lines, such as copper, silver, intrinsically conductive polymers, carbon ink, or nickel-phosphorus (NiP), such as Omega-Ply®, offered by Omega Technologies, Inc. of Culver City, Calif. (USA), or nickel-chrome, such as Ticer™ offered by Ticer Technologies, Chandler, Ariz. (USA). Note that the process employed to form the fine circuit lines or traces on the order described herein is dependent, in part, on the choice of material used for the circuit lines. For instance, if copper circuit lines are being fabricated, then additive processing, such as plating up copper traces, or subtractive processing, such as etching away unwanted copper between trace lines, may be employed. By way of further example, if conductive ink is employed as the circuit line material, fine circuit lines on the order disclosed herein can be achieved by focusing on the rheological properties of the conductive ink formulation. Further, rather than simple pneumatics of pushing conductive ink through an aperture in a stencil with a squeegee, the screen emulsion may be characterized as very thin (for instance, 150 to 200 μm), and a squeegee angle may be used such that the ink is sheared to achieve conductive ink breakaway rather than pumping the conductive ink through the screen apertures. Note that the screen for fine line width printing such as described herein may have the following characteristics in one specific embodiment: a fine polyester thread for both warp and weave on the order of 75 micrometers; a thread count between 250-320 threads per inch; a mesh thickness of, for instance, 150 micrometers; an open area between threads that is at least 1.5× to 2.0× the conductive ink particle size; and to maintain dimensional stability of the print, the screen snap-off is kept to a minimum due the screen strain during squeegee passage.
In a further aspect, the flexible layer 202 itself may be further reduced in thickness from a typical polyester layer by selecting a crystalline polymer to form the flexible layer or substrate. By way of example, the crystalline polymer could include polyvinylidene difluoride (PVDF), or Kapton, or other crystalline polymer material. Advantageously, use of a crystalline polymer as the substrate film may reduce thickness of the flexible layer 202 to, for instance, 2 mils thick from a more conventional amorphous polyester layer of, for instance, 5-6 mils. A crystalline polymer can be made much thinner, while still maintaining structural integrity of the flexible substrate, which advantageously allows for far more folding, and greater reliability of the sensor after folding. Note that the radius of any fold or curvature of the sensor is necessarily constrained by the thickness of the layers comprising the sensor. Thus, by reducing the flexible layer thickness to, for instance, 2 mils, then in a four tamper-detection layer stack, the stack thickness can be reduced from, for instance, 20 mils in the case of a typical polyester film, to 10 mils or less with the use of crystalline polymer films.
Referring collectively to
Tamper-proof electronic package 300 further includes an enclosure 320, such as a pedestal-type enclosure, mounted to multilayer circuit board 310 within, for instance, a continuous groove (or trench) 312 formed within an upper surface of multilayer circuit board 310, and secured to the multilayer circuit board 310 via, for instance, a structural adhesive disposed within continuous groove 312. In one or more embodiments, enclosure 320 may include a thermally conductive material and operate as a heat sink for facilitating cooling of the one or more electronic components 302 within the secure volume. A security mesh or tamper-respondent sensor 321 may be associated with enclosure 320, for example, wrapping around the inner surface of enclosure 320, to facilitate defining, in combination with tamper-respondent sensor 311 embedded within multilayer circuit board 310, secure volume 301. In one or more implementations, tamper-respondent sensor 321 may extend down into continuous groove 312 in multilayer circuit board 310 and may, for instance, even wrap partially or fully around the lower edge of enclosure 320 within continuous groove 312 to provide enhanced tamper detection where enclosure 320 couples to multilayer circuit board 310. In one or more implementations, enclosure 320 may be securely affixed to multilayer circuit board 310 using, for instance, a bonding material such as an epoxy or other adhesive.
Briefly described, tamper-respondent sensor 321 may include, in one or more examples, one or more tamper-detection layers which include circuit lines or traces provided on one or both sides of a flexible layer, which in one or more implementations, may be a flexible insulating layer or film. The circuit lines on one or both sides of the flexible layer may be of a line width and have a pitch or line-to-line spacing such that piercing of the layer at any point results in damage to one or more of the circuit lines or traces. In one or more implementations, the circuit lines may define one or more conductors which may be electrically connected in a network to an enclosure monitor or detector 303, which monitors, for instance, resistance on the lines, or as described below, in the case of conductors, may monitor for a nonlinearity, or non-linear conductivity change, on the conductive lines. Detection of a change in resistance or a nonlinearity caused by cutting or damaging one or more of the lines, will cause information within the secure volume to be automatically erased. The conductive lines of the tamper-respondent sensor may be in any desired pattern, such as a sinusoidal pattern, to make it more difficult to breach the tamper-detection layer without detection.
For resistive monitoring, a variety of materials may be employed to form the circuit lines. For instance, the circuit lines may be formed of a metal or metal alloy, such as copper, or silver, or could be formed, for example, of an intrinsically-conductive polymer, carbon ink, or nickel phosphorous (NiP), or Omega-ply®, offered by Omega Technologies, Inc., of Culver City, Calif. (USA), or Ticer™, offered by Ticer Technologies, Chandler, Ariz. (USA). The process employed to form the fine circuit lines or traces is dependent, in part, on the choice of materials used for the circuit lines. For instance, if copper circuit lines are fabricated, then additive processing, such as plating of copper traces, or subtractive processing, such as etching away unwanted copper between trace lines, may be employed.
As noted, in one or more implementations, the circuit lines of the tamper-respondent sensor(s) lining the inner surface(s) of enclosure 320, or even printed directly onto one or more layers formed over the inner surface of enclosure 320, may be connected to define one or more detect networks.
If a flexible layer is used over the inner surface of enclosure 320, then the flexible layer may be formed of a crystalline polymer material. For instance, the crystalline polymer could include polyvinylidene difluoride (PVDF), or Kapton, or other crystalline polymer material. Advantageously, a crystalline polymer may be made much thinner, while still maintaining structural integrity of the flexible substrate, which also allows for enhanced folding, and greater reliability of the sensor after folding.
As depicted in
As noted, secure volume 301 may be sized to house one or more electronic components to be protected, and may be constructed to extend into multilayer circuit board 310. In one or more implementations, multilayer circuit board 310 includes electrical interconnect within the secure volume 301 defined in the board, for instance, for electrically connecting one or more tamper-detection layers of the embedded tamper-respondent sensor 311 to associated monitor circuitry also disposed within secure volume 301, along with, for instance, one or more daughter cards, such as memory DIMMs, PCIe cards, processor cards, etc.
Note that the packaging embodiment depicted in
By way of further example,
As illustrated, one or more external signal lines or planes 405 may enter secure volume 301 between, in one embodiment, two tamper-detection mat layers 400, and then electrically connect upwards into the secure volume 301 through one or more conductive vias, arranged in any desired location and pattern. In the configuration depicted, the one or more tamper-detection frames 401 are disposed at least inside of the area defined by continuous groove 312 accommodating the base of enclosure 320. Together with the tamper-respondent sensor(s) 321 associated with enclosure 320, tamper-detection frames 401, and tamper-detection mat layers 400, define secure volume 301, which may extend, in part, into multilayer circuit board 310. With secure volume 301 defined, in part, within multilayer circuit board 310, the external signal line(s) 405 may be securely electrically connected to, for instance, the one or more electronic components mounted to, or of, multilayer circuit board 310 within secure volume 301. In addition, secure volume 301 may accommodate electrical interconnection of the conductive traces of the multiple tamper-detection layers 400, 401, for instance, via appropriate monitor circuitry.
Added security may be provided by extending tamper-detection mat layers 400 (and if desired, tamper-detection frames 401) outward past the periphery of enclosure 320. In this manner, a line of attack may be made more difficult at the interface between enclosure 320 and multilayer circuit board 310 since the attack would need to clear, for instance, tamper-detection mat layers 400, the enclosure 320, as well as the tamper-detection frames 401 of the embedded tamper-detect circuit.
Numerous variations on multilayer circuit board 310 of
Note also that, once the secure volume is defined in part within multilayer circuit board 310, conductive vias within the secure volume between layers of multilayer circuit board 310 may be either aligned, or offset, as desired, dependent upon the implementation. Alignment of conductive vias may facilitate, for instance, providing a shortest connection path, while offsetting conductive vias between layers may further enhance security of the tamper-proof electronic package by making an attack into the secure volume through or around one or more tamper-detection layers of the multiple tamper-detection layers more difficult.
The tamper-detection layers of the embedded tamper-detect circuit formed within the multilayer circuit board of the electronic circuit or electronic package may include multiple conductive traces or lines formed between, for instance, respective sets of input and output contacts or vias at the trace termination points. Any pattern and any number of conductive traces or circuits may be employed in defining a tamper-detection layer or a tamper-detection circuit zone within a tamper-detection layer. For instance, 4, 6, 8, etc., conductive traces may be formed in parallel (or otherwise) within a given tamper-detection layer or circuit zone between the respective sets of input and output contacts to those conductive traces.
In one or more implementations, the multilayer circuit board may be a multilayer wiring board or printed circuit board formed, for instance, by building up the multiple layers of the board.
As illustrated in
A first photoresist 504 is provided over build-up 500, and patterned with one or more openings 505, through which the overlying conductive layer 503 may be etched. Depending on the materials employed, and the etch processes used, a second etch process may be desired to remove portions of trace material layer 502 to define the conductive traces of the subject tamper-detection layer. First photoresist 504 may then be removed, and a second photoresist 504′ is provided over the conductive layer 503 features to remain, such as the input and output contacts. Exposed portions of conductive layer 503 are then etched, and the second photoresist 504′ may be removed, with any opening in the layer being filled, for instance, with an adhesive (or pre-preg) 506 and a next build-up layer is provided, as shown. Note that in this implementation, most of overlying conductive layer 503 is etched away, with only the conductive contacts or vias remaining where desired, for instance, at the terminal points of the traces formed within the layer by the patterning of the trace material layer 502. Note that any of a variety of materials may be employed to form the conductive lines or traces within a tamper-detection layer. Nickel-phosphorous (NiP) is particularly advantageous as a material since it is resistant to contact by solder, or use of a conductive adhesive to bond to it, making it harder to bridge from one circuit or trace to the next during an attempt to penetrate into the protected secure volume of the electronic circuit. Other materials which could be employed include OhmegaPly®, offered by Ohmega Technologies, Inc., of Culver City, Calif. (USA), or Ticer™, offered by Ticer Technologies of Chandler, Ariz. (USA).
The trace lines or circuits within the tamper-detection layers, and in particular, the tamper-detection circuit zones, of the embedded tamper-detect circuit, along with the tamper detector monitoring the enclosure, may be electrically connected to detect or compare circuitry provided, for instance, within secure volume 301 (
Note that advantageously, different tamper-detection circuit zones on different tamper-detection layers may be electrically interconnected into, for instance, the same detect circuitry. Thus, any of a large number of interconnect configurations may be possible. For instance, if each of two tamper-detection mat layers contains 30 tamper-detection circuit zones, and each of two tamper-detection frames contains 4 tamper-detection circuit zones, then, for instance, the resultant 68 tamper-detection circuit zones may be connected in any configuration within the secure volume to create the desired arrangement of circuit networks within the secure volume being monitored for changes in resistance or tampering. Note in this regard, that the power supply or battery for the tamper-respondent sensor(s) may be located internal or external to the secure volume, with the sensor being configured to trip and destroy any protected or critical data if the power supply or battery is tampered with.
By way of further example, an isometric view of one embodiment of a tamper-proof electronic package is depicted in
As illustrated, in one or more implementations, the tamper-respondent electronic circuit structure associated with enclosure 600 may include an inner-sidewall tamper-respondent (or tamper-detect) sensor 710 and an inner main surface tamper-respondent (or tamper-detect) sensor 720, along with a security band or element 730. In the illustrated example, inner-sidewall tamper-respondent sensor 710 may be formed with an integrated flex ribbon cable or extension 711 to facilitate electrical connection of the at least one resistive network within inner-sidewall tamper-respondent sensor 710 to appropriate monitor circuitry (not shown) disposed within, for instance, the secure volume defined, at least in part, by the tamper-respondent assembly of
Note that, in the example provided in
By way of further enhancement, increased protection against and/or sensitivity to a tamper event may be desired at or adjacent to, the enclosure-to-board interface. Any attempt to remove the enclosure from the board needs to be detected by the circuitry monitoring the tamper-respondent assembly. In particular, enhancements are provided herein to protect against an attack at the enclosure-to-board interface, and/or to facilitate detection of such an attack by the tamper-respondent electronic circuit structure providing, or defining, the secure volume of the tamper-respondent assembly.
By way of example,
As depicted in
Note that the surface-mount components within tamper-detect circuit 800 may include the same or different types of surface-mount components. Any component which provides structure for adhesive 900 to affix to, and which may be broken away from respective contact pads of tamper-detect circuit 800, may potentially be used, with zero-ohm resistors or wire segments being one type of component, presented by way of example only.
Advantageously, in one or more aspects, tamper-detect circuit 800 may be electrically connected in-series between a power source and the monitor circuitry of the tamper-respondent assembly. In such a configuration, no additional power is required for monitoring tamper-detect circuit 800 since the monitor circuitry already monitor for loss of power from the power source. Thus, any intrusion attempt which results in breaking or open-circuiting tamper-detect circuit 800 is automatically detected as an intrusion event by the monitor circuitry through the loss of power. Thus, tamper intrusion detection is achieved without adding an additional sensing device, power comparator, etc., to the monitor circuitry, thereby further saving power. In one or more implementations, tamper-detect circuit 800 may be disposed adjacent to continuous groove 312 in multilayer circuit board 310, as depicted in
Note that the further embodiment of
The secure volume within which electronic components 1002 reside is defined, in part, within the region encircled by enclosure-to-board interface 1100. This may be achieved, at least in part, by using a tamper-respondent electronic circuit structure such as disclosed herein. For instance, inner sidewall tamper-respondent sensor 710 (
By way of enhancement, increased protection against and/or sensitivity to a tamper event is disclosed herein for, for instance, a tamper-respondent assembly which includes one or more enclosures that mount directly to an upper and/or lower surface or side of a circuit board. As explained further below, the assembly may include a circuit board, an enclosure mounted to the circuit board along an enclosure-to-board interface, a tamper-respondent electronic circuit structure facilitating defining a secure volume, and an adhesive securing the enclosure to the circuit board. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume, and the tamper-respondent electronic circuit structure includes one or more tamper-detect circuits, including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The at least one conductive trace, such as a serpentine trace, includes stress rise regions that facilitate detecting a tamper event at the enclosure-to-board interface. The adhesive contacts, at least in part, the at least one conductive trace of the one or more tamper-detect circuits within the enclosure-to-board interface, including at the stress rise regions of the at least one conductive trace.
As explained herein, in one or more implementations, the at least one conductive trace may include unexposed regions and exposed regions within the enclosure-to-board interface, and with the at least one conductive trace being exposed to the adhesive in the exposed regions and unexposed to the adhesive to the unexposed regions to facilitate defining the stress rise regions. For instance, a solder mask may be employed to partially cover the at least one conductive trace, and define the unexposed regions of the at least one conductive trace within the enclosure-to-board interface. In one or more embodiments, the at least one conductive trace may be or include a serpentine conductive trace with angle bends within the enclosure-to-board interface. The angle bends may be, for instance, right angle bends and/or acute angle bends to further define the stress rise regions.
In one or more embodiments, the serpentine conductive trace, either with or without the solder mask, may include multiple conductive vias that intersect the serpentine conductive trace and extend into the circuit board. The multiple conductive vias may facilitate defining, at least in part, the stress rise regions of the at least one conductive trace. In one implementation, the multiple conductive vias may extend through the circuit board and contact the serpentine conductive trace at respective angle bends.
In one or more embodiments, the serpentine conductive trace may reside on a surface of the circuit board, and be disposed in part within an area of the enclosure-to-board interface and in part within the secure volume, for instance, at an inner periphery of the enclosure-to-board interface. In one or more implementations, the angle bends of the serpentine conductive trace, when present, may include a first set of angle bends within the enclosure-to-board interface, and a second side of angle bends disposed within the secure volume, for instance, at the inner periphery of the enclosure-to-board interface. By way of example, the conductive trace may be a conductive circuit that resides, in part, on one side of the circuit board, and includes the multiple conductive vias that extend into the circuit board. In one or more embodiments, the conductive circuit may also reside on another side of the circuit board, where the one side and the other side are opposite sides of the circuit board, and be stitched together by the multiple conductive vias.
The above and other embodiments, are described below in greater detail with reference to
In one or more embodiments, an additional level of tamper protection is provided using one or more conductive traces and related structures on one or both surfaces of the circuit board depending on whether there are one or two enclosures, or more, to mount to the circuit board. Note in this regard that various aspects disclosed herein may be used in combination with any enclosure-to-board interface from one to many enclosures mounted to the circuit board. In one or more embodiments, the enclosure is adhesively bonded to the surface of the board directly over, at least in part, these conductive traces. When a tamper event occurs, for instance, by an attempted separation of an enclosure from the circuit board, one or more of the conductive traces, through predesign, break leading to tamper detection. Enhanced tamper detection capability is provided by configuring the conductive trace(s) with discrete stress concentration points, referred to herein as stress rise regions. These stress rise regions (or stress risers) may be achieved by a variety of techniques, which may be used alone, or in combination, as discussed further below.
In the embodiment of
As a further example,
By way of further example, conductive vias 1503 are shown on multiple sides of the enclosure-to-board interface 1100. These conductive vias 1503 serve as anchor points and may extend into and/or through circuit board 1000 as noted above, and may be provided in any pattern desired to intersect the tamper-detect circuit 1500. In the example shown, the conductive vias are located at the angle bends 1501, 1502. Alternatively, the conductive vias could intersect straight line portions of the tamper-detect circuit 1500, and/or could be located only within the enclosure-to-board interface 1100, or only outside of the enclosure-to-board interface within the secure volume 1001. As shown, tamper-detect circuit 1500 further includes terminal leads 1511 which connect to monitor circuitry (not shown) within secure volume 1001, such as within one or more electronic components 1002. Also, note that the stress rise regions could be further defined or enhanced by providing a mask such as a solder mask, over the tamper-detect circuit in any desired pattern, such as described above.
In
As noted herein, numerous inventive aspects and features are disclosed, and unless otherwise inconsistent, each disclosed aspect or feature may be combined with any other disclosed aspect or feature as desired to achieve a particular application, for instance, to achieve a particular tamper-detect circuit at an enclosure-to-board interface with the desired stress rise region characteristics to, for instance, enhance tamper proof enclosure-to-board interface protection.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.
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