An exemplary embodiment of the present disclosure relates to an etching method.
In order to realize further miniaturization of a device such as, for example, a semiconductor device, it is necessary to form a pattern with a dimension smaller than the critical dimension obtained by a fine processing using a photolithography technique so far achieved. As a method of forming a pattern with such a dimension, development of extreme ultraviolet (EUV), which is a next-generation exposure technique, is promoted. In the EUV, a light having a remarkably short wavelength (e.g., 13.5 nm) is used, as compared with a wavelength of a conventional UV light source. Therefore, in the EUV, there is a technical barrier against mass production. For example, the EUV has a problem such as a long exposure time. Thus, what is demanded is to develop an alternative manufacturing method which can provide a further miniaturized device.
As an alternative to the conventional lithography technique, attention has been paid to a technique of forming a pattern using a self-assembled block copolymer (BCP) which is one of self-assembled materials that spontaneously assemble an order pattern. Such a technique is described in Patent Documents 1 and 2.
In the technique described in Patent Document 1, a block copolymer layer is coated on a base layer. The block copolymer layer contains a block copolymer containing two or more polymer block components A and B which are immiscible with each other. Then, a heat treatment (annealing) is performed to cause the polymer block components A and B to spontaneously phase-separate from each other. Thus, an ordered pattern having a first region containing the polymer block component A and a second region containing the polymer block component B, is obtained. Further, in Patent Document 2, a patterning processing of block copolymers has been suggested as a method of forming a via. In the patterning processing described in Patent Document 2, a pattern is obtained by removing the second region among the first region and the second region of the phase-separated block copolymer layer.
In the techniques described in Patent Documents 1 and 2, when an etching target layer is etched using a mask obtained by the patterning of the block copolymer, the pattern of the mask may be deformed.
Accordingly, it is required to suppress the mask obtained by the patterning of the block copolymer from being deformed due to the etching of the etching target layer.
According to an aspect, provided is a method of etching an etching target layer of a workpiece. The method includes a step (a) of forming a self-assemblable block copolymer layer containing a first polymer and a second polymer on an intermediate layer formed on the etching target layer; a step (b) of processing the workpiece to form a first region containing the first polymer and a second region containing the second polymer, from the block copolymer layer; after the step (b), a step (c) of forming a mask by etching the second region and the intermediate layer just below the second region; after the step (c), a step (d) of forming a protective film on the mask by generating plasma of a processing gas containing silicon tetrachloride gas and oxygen gas within a processing container of a plasma processing apparatus that accommodates the workpiece; and after the step (d), a step (e) of etching the etching target layer.
In the method according to the above-described aspect, a protective film is formed on the mask. The protective film contains silicon oxide based on oxygen and silicon in the plasma generated in the step (d). Owing to the protective film, the mask is protected from the etching in the step (e). Accordingly, it is possible to suppress the mask from being deformed due to the etching of the etching target layer.
In an exemplary embodiment, the etching target layer is a silicon-containing layer. In the step (e), plasma of a processing gas containing at least one of fluorocarbon gas and fluorohydrocarbon gas may be generated within the processing container. According to the exemplary embodiment, it is possible to etch the etching target layer by active species of fluorine. In addition, it is also possible to remove the protective film deposited by the step (d), on the surface of the etching target layer exposed from the mask.
In another aspect, provided is another method of etching an etching target layer of a workpiece. The method includes a step (a) of forming a self-assemblable block copolymer layer containing a first polymer and a second polymer on an intermediate layer formed on the etching target layer; a step (b) of processing the workpiece to form a first region containing the first polymer and a second region containing the second polymer, from the block copolymer layer; after the step (b), a step (c) of forming a mask by etching the second region and the intermediate layer just below the second region; after the forming the mask, a step (f) of etching the etching target layer. The etching target layer, which is a subject to be etched in this method, is a layer containing silicon oxide or silicon nitride. In the step (f), plasma of a processing gas containing at least one of fluorocarbon gas and fluorohydrocarbon gas, and hydrogen bromide gas, is generated within the processing container.
In the method according to the above-described aspect, a protective layer is formed, which contains components such as SiBrO derived from active species of atoms or molecules contained in hydrogen bromide gas contained in the gas used in the step (f). Further, the mask is modified, that is, cured by the active species of Br. As a result, it is possible to suppress the mask from being deformed due to the etching of the etching target layer.
In an exemplary embodiment of the above-described method, the first polymer may be polystyrene, and the second polymer may be poly(methyl methacrylate).
As described above, according to the aspects and various exemplary embodiments, the mask obtained by the patterning of the block copolymer may be suppressed from being deformed due to the etching of the etching target layer.
Hereinafter, an exemplary embodiment of the present disclosure will be described with reference to drawings. Same or corresponding portions in the drawings will be denoted by the same symbols.
As illustrated in
As illustrated in
Subsequently, as illustrated in
In method MT1, step ST2 is subsequently performed. In step ST2, a block copolymer is coated on the surface of the wafer W, that is, the surface of the intermediate layer NL. The block copolymer may be coated by various methods such as, for example, a spin coat method. Therefore, as illustrated in
The block copolymer is a self-assembled block copolymer, and includes a first polymer and a second polymer. In an exemplary embodiment, the block copolymer is polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA). PS-b-PMMA includes polystyrene (PS) as the first polymer, and poly(methyl methacrylate) (PMMA) as the second polymer.
Here, the block copolymer and its self-assembly will be described using PS-b-PMMA by way of an example with reference to
When the polymer length of each polymer is short, the interaction (repulsive force) becomes weaker and the hydrophilicity becomes stronger. On the other hand, when the polymer length is long, the interaction (repulsive force) becomes stronger and the hydrophobicity becomes stronger. Using such a polymer property, a phase-separated structure of PS and PMMA may be prepared, for example, as illustrated in
Further,
Reference is made back to
Prior to the subsequent step ST4, the wafer W is conveyed into a plasma processing apparatus.
In the bottom portion of the chamber 10, a cylindrical susceptor support 14 is disposed via an insulating plate 12 made of, for example, ceramic. A susceptor 16 made of, for example, aluminum is provided on the susceptor support 14.
On the top surface of the susceptor 16, an electrostatic chuck 18 is provided to hold the wafer W by electrostatic attraction force. The electrostatic chuck 18 has a structure where a chuck electrode 20 made of a conductive film is interposed between a pair of insulating layers or insulating sheets. The electrode 20 is electrically connected with a DC power source 22 via a switch 24. In the plasma processing apparatus 1, the wafer W is able to be attracted and held on the electrostatic chuck 19 by electrostatic attraction force generated by a DC voltage from the DC power source 22. A focus ring 26 is disposed around the electrostatic chuck 18 on the susceptor 16 to enhance in-plane uniformity of the etching. The focus ring 26 is made of, for example, silicon. Further, a cylindrical inner wall member 28 made of, for example, quartz is attached on the side of the susceptor 16 and the susceptor support 14.
A coolant chamber 30 is formed inside the susceptor support 14. The coolant chamber 30 extends, for example, annularly within the susceptor support 14. A coolant, for example, cooling water cw of a predetermined temperature is circulated and supplied from an external chiller unit to the coolant chamber through pipes 32a, 32b. In the plasma processing apparatus 1, the temperature of the wafer W on the susceptor 16 is controlled by controlling the temperature of the coolant cw. Further, a heat transfer gas such as, for example, helium (He) gas from a heat transfer gas supply mechanism (not illustrated) is supplied between the top surface of the electrostatic chuck 18 and the rear surface of the wafer W through a gas supply line 34.
Further, the susceptor 16 is electrically connected with a first high frequency power source 36 for plasma generation and a second high frequency power source 38 for ion attraction via matchers 40, 42 and power feeding rods 44, 46, respectively.
The first high frequency power source 36 generates a first frequency power of a frequency suitable for plasma generation, for example, 40 MHz. Further, the first frequency may be a frequency of 60 MHz or 100 MHz. Meanwhile, the second high frequency power source 38 generates a second frequency power of a relatively low frequency suitable for attracting ions of plasma to the wafer W on the susceptor 16, for example, 13 MHz.
An upper electrode 48 is provided above the susceptor 16 to face the susceptor in parallel. The upper electrode 48 is constituted by an electrode plate 50 and an electrode support 52 that detachably supports the electrode plate 50. The electrode plate 50 includes a plurality of gas holes 50a formed therein. The electrode plate 50 may be made of a semiconductor material such as, for example, Si or SiC. The electrode support 52 is made of, for example, aluminum, of which the surface is subjected to an anodizing treatment. The electrode plate 50 and the electrode support 52 are attached to an upper portion of the chamber 10 via a ring-shaped insulator 54. The ring-shaped insulator 54 is made of, for example, alumina. A plasma generating space, that is, a processing space S is defined between the upper electrode 48 and the susceptor 16.
A gas buffer chamber 56 is formed in the electrode support 52. In addition, the electrode support 52 includes a plurality of gas vent holes 52a formed to communicate the gas buffer chamber 56 and the gas holes 50a of the electrode plate 50. The gas buffer chamber 56 is connected with a gas source 60 through a gas supply pipe 58. The gas supply pipe 58 is provided with a mass flow controller (MFC) 62 and an opening/closing valve 64. When a processing gas is introduced into the gas buffer chamber 56 from the gas source 60, the processing gas is injected from the gas holes 50a of the electrode plate 50 toward the wafer W on the susceptor 16, in a shower form in the processing space S. As such, the upper electrode 48 also serves as a shower head configured to supply the processing gas to the processing space S.
An annular space formed between the susceptor 16 and the susceptor support 14, and the sidewall of the chamber 10 serves as an exhaust space. An exhaust port 72 of the chamber 10 is formed on the bottom of the exhaust space. The exhaust port 72 is connected with an exhaust device 76. The exhaust device 76 is provided with a vacuum pump such as, for example, a turbo molecular pump, and is configured to decompress the inside of the chamber, particularly, the processing space S to a desired degree of vacuum. Further, a gate valve 80 is attached to the sidewall of the chamber 10 to open/close a carry-in/out port 78 of the wafer W.
A controller 88 includes a central processing unit (CPU), a read only memory (ROM), and a random access memory (RAM), and the CPU controls the execution of the process, for example, according to various recipes stored in the RAM.
When the wafer W is processed in the plasma processing apparatus 1, the gate valve 80 is first opened, and the wafer W held on a conveyance arm is then carried into the chamber 10. Then, the wafer W is placed on the electrostatic chuck 18. After the carry-in of the wafer W, the gate valve 80 is closed, and the processing gas is introduced from the gas source 60 into the chamber 10 at a predetermined flow rate and in a predetermined flow rate ratio. Then, the pressure in the chamber 10 is decreased to a set value by the exhaust device 76. In addition, a high frequency power is supplied from the first high frequency power source 36 to the susceptor 16, and optionally, a high frequency bias power is also supplied from the second high frequency power source 38 to the susceptor 16. Thus, the processing gas introduced in a shower form from the shower head is excited to generate plasma. The wafer W is processed by active species such as radicals and ions in the plasma.
Reference is made back to
In step ST4, the block copolymer layer BCL composed of an organic material is etched from its surface by active species of the oxygen. Here, the etching rate of the second region R2 composed of the second polymer is higher than that of the first region R1 composed of the first polymer. Therefore, by step ST4, the second region R2 is selectively etched. Further, when the second region R2 is removed, a part of the exposed intermediate layer NL is etched. By step ST4, the wafer W comes to a state illustrated in
Subsequently, as illustrated in
When step ST5 is performed by the plasma processing apparatus 1, the processing gas containing silicon tetrachloride gas and oxygen gas is supplied from the gas source 60 into the chamber 10, and the pressure in the chamber 10 is decompressed to a set value by the exhaust device 76. Further, a high frequency power is supplied from the first high frequency power source 36 to the susceptor 16. In step ST5, a high frequency bias power may be supplied from the second high frequency power source 38 to the susceptor 16 as necessary.
Subsequently, in method MT1, step ST6 is performed. In step ST6, an etching target layer EL exposed by the opening of the mask MK is etched. Thus, in step ST6, plasma of a processing gas containing fluorocarbon gas is generated within the plasma processing apparatus, and the wafer W is exposed to the plasma. Since the plasma contains active species of fluorine, the protective film PF on the etching target layer EL exposed by the opening of the mask MK, and the etching target layer EL just therebelow are etched by step ST6. By step ST6, the wafer W comes to a state illustrated in
When step ST6 is performed by the plasma processing apparatus 1, the processing gas containing fluorocarbon gas is supplied from the gas source 60 into the chamber 10, and the pressure in the chamber 10 is decompressed to a set value by the exhaust device 76. Further, a high frequency power is supplied from the first high frequency power source 36 to the susceptor 16. In step ST6, a high frequency bias power may be supplied from the second high frequency power source 38 to the susceptor 16 as necessary.
In method MT1 described above, the protective film PF is formed on the mask MK prior to the etching of the etching target layer EL. By the protective film PF, the mask MK may be protected from the etching in step ST6. That is, it is possible to suppress deformation such as twisting of the mask MK due to the etching in step ST6.
Hereinafter, an etching method according to another exemplary embodiment.
In step ST62, the wafer W in a state after step ST4 is exposed to the generated plasma. In step ST62, a protective layer, which contains components such as SiBrO derived from active species of atoms or molecules contained in hydrogen bromide gas, is formed on the mask MK. Further, the mask is modified, that is, cured by the active species of Br. Further, since the plasma generated in step ST62 contains the active species of fluorine, the etching target layer EL is etched as in step ST6. Therefore, according to step ST62, the etching target layer EL may be etched while protecting the mask MK. Thus, according to step ST62, it is possible to suppress deformation such as twisting of the mask MK due to the etching.
As such, exemplary embodiments have been described, but without being limited thereto, various modifications may be available. For example, the plasma processing apparatus which may be used in steps ST4, ST5, ST6, and ST62 is not limited to the capacitively coupled plasma processing apparatus. In the steps, for example, an inductively coupled plasma processing apparatus, or a plasma processing apparatus using surface waves such as microwaves as a plasma source may be used.
Number | Date | Country | Kind |
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2013-194285 | Sep 2013 | JP | national |
2014-020628 | Feb 2014 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP2014/073042 | 9/2/2014 | WO | 00 |