Patent Application
20230236495
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-009549, filed Jan. 25, 2022, and No. 2022-124977, filed Aug. 4, 2022, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to an exposure apparatus and a method for manufacturing a semiconductor device.
A three-dimensional stacking technique for three-dimensionally stacking semiconductor circuit substrates is known.
In general, according to one embodiment, an exposure apparatus is configured to implement an exposure process for exposing a substrate to light. The exposure apparatus includes a stage, a storage device, and a controller. The stage is configured to hold the substrate. The storage device is configured to store a plurality of correction maps each having an alignment correction value that differs from each other. The controller is configured to control in the exposure process an exposure position relative to the substrate by selecting a correction map from the correction maps based on measurement results of a plurality of alignment marks arranged on the substrate or an amount of warpage of the substrate and moving the stage based on the selected correction map.
Hereinafter, embodiments will be described with reference to the drawings. Each embodiment exemplifies an apparatus and a method for embodying the technical concepts of the invention. The drawings are schematic or conceptual. Dimensions, ratios, and the like of each drawing are not necessarily the same as the actual dimensions, ratios, and the like. Where appropriate, illustrations of configurations are omitted. The hatching added to the drawings is not necessarily related to the materials or characteristics of constituent elements. In the present specification, constituent elements having substantially the same functions and configurations have the same reference signs assigned thereto. Numerals and the like appended to the reference signs are referred to using the same reference signs and are used to distinguish between similar elements.
The semiconductor device of the present specification is formed by bonding two semiconductor circuit substrates each having a semiconductor circuit formed thereon, and by dividing the bonded semiconductor circuit substrates into chips. Hereinafter, a semiconductor circuit substrate is referred to as a “wafer”. A manufacturing process for bonding two wafers is referred to as the “bonding process”. An apparatus that performs the bonding process is referred to as a “bonding apparatus”. The wafer disposed on the upper side during the bonding process is referred to as the “upper wafer UW”. The wafer disposed on the lower side during the bonding process is referred to as the “lower wafer LW”. A set of two bonded wafers, that is, the upper wafer UW and the lower wafer LW is referred to as a “bonded wafer BW”. In the present specification, the X direction and the Y direction are directions that intersect each other and that run parallel to the surface of the wafer. The Z direction is a direction that intersects the X direction and the Y direction, respectively, and that is perpendicular to the surface of the wafer. The “wafer surface” is a surface on the side where a semiconductor circuit is formed by a pre-process that will be described subsequently. The “wafer rear surface” is a surface opposite to the surface of the wafer. “Up and down” in the present specification is defined based on a direction along the Z direction.
First, a wafer is allocated to a lot (“lot allocation”). A lot may include a plurality of wafers. Lots may be categorized into lots including the upper wafer UW and lots including the lower wafer LW, for example. Thereafter, a pre-process is performed on each of the lots including the upper wafer UW and the lots including the lower wafer LW, and a semiconductor circuit is formed on the upper wafer UW and the lower wafer LW, respectively. A pre-process includes a combination of an “exposure process”, “exposure OL (overlay) measurement”, and a “etching process”.
The exposure process is, for example, a process for transferring a mask pattern to a wafer by irradiating the wafer, which is coated with a resist, with light that is transmitted through the mask. A region to which the mask pattern is transferred through one exposure corresponds to “one shot”. The “shot” corresponds to a segregated region of exposure in the exposure process. In the exposure process, one-shot exposure is repeatedly executed with the exposure position shifted. That is, the exposure process is executed using a step-and-repeat method. In the exposure process, the arrangement and shape of each shot are corrected based on measurement results for the alignment marks, which will be described subsequently, and of various correction values, and the like, and the position of overlay with the substrate pattern formed on the wafer is adjusted (aligned). The arrangement (layout) of the plurality of shots in the upper wafer UW and the arrangement (layout) of the plurality of shots in the lower wafer LW are set to be identical. Hereinafter, an apparatus that executes an exposure process is referred to as an “exposure apparatus”. The correction values used in the alignment of the overlay position, that is, the control parameters of the exposure apparatus for suppressing the overlay deviation, are referred to as the “alignment correction values”. When a polynomial is used to correct the alignment, the coefficient of each term is referred to as an “alignment correction coefficient”. That is, the alignment correction values can be calculated based on the alignment correction coefficient for each term, and the exposure position.
The exposure OL measurement is a manufacturing process for measuring overlay deviation amounts between a pattern formed by the exposure process, and a pattern serving as the substrate in the exposure process. The measurement results of the overlay deviation amounts obtained through exposure OL measurement can be used in a determination to rework the exposure process, or to calculate alignment correction values that are to be applied to the subsequent lot, and the like. The etching process is a manufacturing process of etching the wafer by using a mask formed by the exposure process. When the machining process is complete, the used mask is removed and the next process is performed.
When the pre-process is complete (pre-processing completion), a bonding process is performed. In the bonding process, the bonding apparatus arranges the surface of the upper wafer UW and the surface of the lower wafer LW to face each other. Further, in the bonding process, the position of overlay between the pattern formed on the surface of the upper wafer UW and the pattern formed on the surface of the lower wafer LW is adjusted (aligned). Thereafter, the bonding apparatus bonds the surfaces of the upper wafer UW and the lower wafer LW to form a bonded wafer BW.
Bond OL (overlay) measurement is performed on the bonded wafer BW formed by the bonding process. The bond OL measurement is a manufacturing process for measuring overlay deviation amounts between a pattern formed on the surface of the upper wafer UW and a pattern formed on the surface of the lower wafer LW. The measurement results of the overlay deviation amounts obtained through bond OL measurement can be used to calculate alignment correction values that are applied to the exposure process of the subsequent lot, and the like.
The overlay deviation amounts generated in the exposure process or the bonding process can be expressed by a combination of various components.
Formulae corresponding to each of the components (A) to (J) of
(A) An offset (shift) component in the X direction is “dx = K1”. The offset (shift) component in the Y direction is “dy = K2”.
(B) The magnification component in the X direction is “dx = K3·x”. The magnification component in the Y direction is “dy = K4·y”.
(C) A rhombus (orthogonality) component in the X direction is “dx = K5·y”. A rhombus (orthogonality) component in the Y direction is “dy = K6·x” .
(D) The eccentricity magnification component in the X direction is “dx = K7·x2” . The eccentricity magnification component in the Y direction is “dy = K8·y2”.
(E) The trapezoidal component in the X direction is “dx = K9·x·y”. The trapezoidal component in the Y direction is “dy = K10·x·y”.
(F) The fan shaped component in the X direction is “dx = K11·y2”. The fan shaped component in the Y direction is “dy = K12·x2”.
(G) The C-shaped magnification component in the X direction is “dx = K13·x3”. The C-shaped magnification component in the Y direction is “dy = K14·y3”.
(H) The accordion shaped portion in the X direction is “dx = K15·x2·y”. (H) The accordion shaped portion in the Y direction is “dy = K16·x·y2”.
(I) The C-shaped distortion component in the X direction is “dx = K17·x·y2”. The C-shaped distortion component in the Y direction is “dy = K18·x2·y”.
(J) The stream flow shaped component in the X direction is “dx = K19·y3”. The stream flow shaped component in the Y direction is “dy = K20·x3”.
That is, in the present example, the overlay deviation amount Ex in the X direction is calculated by “Ex=K1+K3·x+dy+K5·y+K7·x2+K9·x·y+K11·y2+K13·x3+K15·x2·y+K17 ·x·y2+K19·y3”. The overlay deviation amount Ey in the Y direction is calculated by “Ey = K2+K4·y+K6·x+K8·y2+K10·x·y+K12·x2+K14·y3+ K16·x·y2+K18·x2·y+K 20·x3”. When the overlay deviation component is expressed by polynomial regression, not only K1 to K20 but also a coefficient assigned to a higher-order overlay component may be used as the polynomial regression coefficient. In the present specification, K1 to K20 are each referred to as a “K value”. That is, the overlay measurement results can be broken down for each K value using polynomial regression.
Note that, although overlay deviation components of shot units are illustrated in
As illustrated in (A) of
Furthermore, the exposure apparatus is capable of setting, for each shot, the correction amount of the shift component, the correction amount of the magnification component, and the correction amount of the orthogonality component, for example. In the present specification, an alignment correction method in which alignment correction values, which are set for each shot, are used is referred to as “exposure map correction”. A set of alignment correction values for each shot used in the exposure map correction is referred to as the “map correction values”. The map correction values can be created based on exposure OL measurement results, bond OL measurement results, or the like. “The map correction values” may also be referred to as the “exposure position correction map” or the “correction map”. As the alignment correction values for each shot applied in the exposure map correction, it suffices that at least any of a shift component, a magnification component, and an orthogonality component is used. Thus, the exposure apparatus is capable of correcting complex overlay deviation components.
As illustrated in (B) and (C) of
In addition, the bonding apparatus is capable of correcting the wafer magnification by deforming the stage holding the wafer. When correcting the wafer magnification, the bonding apparatus is capable of using, for example, the wafer magnification alignment correction value used in the exposure process, or a wafer magnification value that is calculated based on the exposure OL measurement results, or the like. Note that the bonding apparatus is capable of measuring the respective alignment marks AM of the upper wafer UW and the lower wafer LW in parallel. For example, because the alignment marks AM_C of the upper wafer UW and the lower wafer LW are simultaneously measured under constraints on the arrangement of the alignment marks AM, the respective alignment marks AM_C of the upper wafer UW and the lower wafer LW are arranged so as to be shifted from the center of the wafer in opposite directions.
In the exposure process, the exposure apparatus 1 according to the first embodiment selects map correction values, which enable random component generation in the bond OL to be suppressed, based on the wafer magnification. Hereinafter, details of the exposure apparatus 1 according to the first embodiment will be described.
The exposure apparatus 1, the bonding apparatus 2, and the server 3 are configured to be capable of communicating via a network NW. Wired communication or wireless communication may be used for the network NW. The bonding apparatus 2 uses the upper wafer UW and the lower wafer LW, for which the exposure apparatus 1 was used in the pre-process, to execute a bonding process and create the bonded wafer BW. The server 3 is, for example, a computer or the like that controls the overall semiconductor device manufacturing process. The server 3 manages correction values that are used in each manufacturing process, and the like. Note that the semiconductor manufacturing system PS can also include an overlay measurement device or the like.
The control device 10 is a computer or the like that controls the overall operation of the exposure apparatus 1. The control device 10 controls the storage device 11, the carrier device 12, the communication device 13, and the exposure unit 14, respectively. Although not illustrated, the control device 10 is equipped with a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), and the like. The CPU is a processor that executes various programs relating to the control of devices. The ROM is a non-volatile storage medium that stores a device control program. The RAM is a volatile storage medium that is used as a work area of the CPU.
The storage device 11 is a storage medium that is used for storing data, programs, and the like. The storage device 11 stores, for example, an exposure recipe 110, correction value information 111, and a map correction value set 112. The exposure recipe 110 includes the setting of the exposure process. The exposure recipe 110 includes information such as the shot shape and layout, an exposure amount, a focus setting, and an alignment setting. The exposure recipe 110 can be prepared for each manufacturing process or each lot. The correction value information 111 is a log that records alignment correction values (that is, alignment results) that are used when an exposure process is executed. The map correction value set 112 includes a plurality of map correction values. A map correction value includes an alignment correction value for each shot. A method for creating the map correction values will be described subsequently.
The carrier device 12 is a device that is equipped with a carrier arm capable of carrying a wafer, a transition for temporarily placing a plurality of wafers, and the like. For example, the carrier device 12 carries the wafer WF received from an external coating-development device to the exposure unit 14, for example. In addition, after the exposure process, the carrier device 12 carries the wafer WF received from the exposure unit 14 to outside the exposure apparatus 1. Note that the “coating-development device” is a device that executes a pre-process and a post-process of the exposure process. The pre-process of the exposure process includes a process for using a resist material (photosensitive material) to coat the wafer. The post-process of the exposure process includes a process for developing a pattern with which the wafer is exposed. Note that a plurality of semiconductor manufacturing devices may also be used as devices used in the pre-process and post-process of the exposure process.
The communication device 13 is a communication interface capable of connecting to a network. The exposure apparatus 1 may operate based on an operation by a terminal on the network, or may store the exposure recipe 110 and the correction value information 111 in a server on the network.
The exposure unit 14 is a set of configurations used in the exposure process. The exposure unit 14 includes, for example, a wafer stage 140, a reticle stage 141, a light source 142, a projection optical system 143, and a camera 144. The wafer stage 140 has a function for holding a wafer WF. The reticle stage 141 has a function for holding a reticle RT (mask). The respective stage positions of the wafer stage 140 and the reticle stage 141 can be controlled based on control by the control device 10. The light source 142 irradiates the reticle RT with generated light. The projection optical system 143 collects the light transmitted through the reticle RT onto the surface of the wafer WF. The camera 144 is an imaging mechanism that is used to measure the alignment marks AM.
The control device 20 is a computer or the like that controls the overall operation of the bonding apparatus 2. The control device 20 controls the carrier device 21, the communication device, and the bonding unit 23, respectively. Although not illustrated, the control device 20 is equipped with a CPU, a ROM, a RAM, and the like, similarly to the exposure apparatus 1.
The carrier device 21 is a device that is equipped with a carrier arm capable of carrying a wafer, and a transition for temporarily placing a plurality of wafers, and the like. For example, the carrier device 21 carries the upper wafer UW and the lower wafer LW received from a pre-process device of the bonding process to the bonding unit 23. In addition, the carrier device 21 carries the bonded wafer BW received from the bonding unit 23 to outside the bonding apparatus 2 after the bonding process. The carrier device 21 may include a mechanism for vertically inverting the wafer.
The communication device 22 is a communication interface capable of connecting to network NW. The bonding apparatus 2 may operate based on control of a terminal on the network NW, may store an operation log on the server 3 on the network NW, or may calculate alignment correction values based on information stored on the server 3.
The bonding unit 23 is a set of configurations used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pushpin 234, and a camera 235. The lower stage 230 has a function for holding the lower wafer LW. The lower stage 230 includes, for example, a wafer chuck that holds the wafer through vacuum suction. The stress device 231 has a function for applying stress to the lower stage 230 and for deforming the lower wafer LW via the lower stage 230. The expansion amount (scaling) of the lower wafer LW held by the lower stage 230 changes according to the amount of deformation of the lower stage 230 by the stress device 231. The camera 232 is an imaging mechanism that is disposed on the lower stage 230 side and that is used to measure the alignment marks AM of the upper wafer UW. The upper stage 233 has a function for holding the upper wafer UW. The upper stage 233 includes, for example, a wafer chuck that holds the wafer through vacuum suction. The pushpin 234 is a pin that can be driven in the up-down direction based on the control by the control device 20 to press the upper surface of the center portion of the upper wafer UW held by the upper stage 233. The camera 235 is an imaging mechanism that is disposed on the upper stage 233 side and that is used to measure the alignment marks AM of the lower wafer LW. The bonding apparatus 2 may have a vacuum pump that is used for vacuum suction of the lower stage 230 and the upper stage 233.
Note that the lower stage 230 and the upper stage 233 are configured such that the lower wafer LW held by the lower stage 230 and the upper wafer UW held by the upper stage 233 can be arranged to face each other. That is, the upper stage 233 can be disposed above the lower stage 230. In other words, the lower stage 230 and the upper stage 233 can face each other. In the bonding process, the upper surface of the upper wafer UW is the back surface of the upper wafer UW and is held on the upper stage 233 of the bonding apparatus 2. In the bonding process, the lower surface of the upper wafer UW is a surface of the upper wafer UW and corresponds to the bonding surface. The upper surface of the lower wafer LW is the surface of the lower wafer LW and corresponds to the bonding surface. The lower surface of the lower wafer LW is the back surface of the lower wafer LW and is held by the lower stage 230 of the bonding apparatus 2. The bonding apparatus 2 is capable of adjusting the shift component and the rotation component of the overlay deviation by adjusting the relative positions of the lower stage 230 and the upper stage 233. The bonding apparatus 2 is also capable of adjusting the XY common wafer magnification of the lower wafer LW held by the deformed lower stage 230 by using the stress device 231 to deform the lower stage 230.
Note that the above-mentioned “bonding-process pre-process device” is a device having a function for modifying and hydrophilizing the bonding surfaces of the upper wafer UW and the lower wafer LW so as to enable bonding, before the bonding process by the bonding apparatus 2. In brief, the pre-process device first performs a plasma process on the respective surfaces of the upper wafer UW and the lower wafer LW and modifies the respective surfaces of the upper wafer UW and the lower wafer LW. In the plasma process, oxygen ions or nitrogen ions are generated based on oxygen gas or nitrogen gas, which is the treatment gas, under a predetermined reduced atmosphere, and the generated oxygen ions or nitrogen ions are applied to the bonding surface of each wafer. Thereafter, the pre-process device supplies pure water to the respective surfaces of the upper wafer UW and the lower wafer LW. Thereupon, hydroxyl groups adhere to the respective surfaces of the upper wafer UW and the lower wafer LW, and the surfaces are hydrophilized. In the bonding process, the upper wafer UW and the lower wafer LW, the bonding surfaces of which have been modified and hydrophilized as described above, are used. The bonding apparatus 2 may be combined with a pre-process device or the like to constitute a bonding system.
Hereinafter, as a method for manufacturing a semiconductor device according to the first embodiment, an example of a specific process using the exposure apparatus 1 will be described. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the first embodiment described hereinbelow.
When the completion of the wafer pre-process is reported by the coating-development device, the exposure apparatus 1 starts the exposure process (Start).
First, the exposure apparatus 1 loads a wafer (S100). The wafer loaded from the coating-development device is held by the wafer stage 140.
Next, the exposure apparatus 1 checks the exposure recipe 110 (S101). As a result, the control device 10 determines process conditions to be applied to the loaded wafer.
Next, the exposure apparatus 1 measures the alignment marks AM (S102). More specifically, the camera 144 photographs a plurality of alignment marks AM arranged in predetermined positions on the wafer.
Next, the exposure apparatus 1 executes an alignment correction process (S103). More specifically, the control device 10 calculates alignment correction values for shot arrangements and shot shapes with which the wafer is to be exposed, based on the measurement results of the plurality of alignment marks AM. Furthermore, the exposure apparatus 1 according to the first embodiment selects a map correction value based on the wafer magnification correction values that are included in the calculated alignment correction values, and uses these values for the alignment. For this reason, in the exposure apparatus 1 according to the first embodiment, in a case where the exposure process is continuously performed with respect to a plurality of wafers included in one lot, different map correction values can be applied for each wafer.
Next, the exposure apparatus 1 executes an exposure sequence (S104). More specifically, the control device 10 controls the light source 142, the wafer stage 140, and the reticle stage 141 based on the alignment correction values calculated in S103, and irradiates the wafer with the light transmitted through the mask by using a step-and-repeat method.
Next, the exposure apparatus 1 updates the correction value information 111 (S105). That is, in S105, the alignment correction values calculated in S103 are recorded in the correction value information 111 in association with the processed wafer.
Next, the exposure apparatus 1 unloads the wafer (S106). The unloaded wafer is delivered to the coating-development device. The coating-development device performs processes such as a heat treatment, development, and cleaning with respect to the wafer for which the exposure process has been completed. Thus, a pattern is formed on the wafer.
When the wafer is unloaded, the exposure apparatus 1 ends the exposure process (End).
(1) of
Upon starting the bonding process, the control device 20 controls the stress device 241 based on common wafer magnification alignment correction values in the X direction and the Y direction, thereby deforming the lower stage 240 as illustrated in (2) of
Next, the control device 20 causes the carrier device 21 to carry the lower wafer LW to the lower stage 230 and to carry the upper wafer UW to the upper stage 233. Further, as illustrated in (3) of
Next, the control device 20 executes rotational alignment. More specifically, first, as illustrated in (4) of
Next, as illustrated in (5) of
Next, the control device 20 executes camera origin alignment. More specifically, as illustrated in (6) of
Next, the control device 20 executes shift alignment. More specifically, first, as illustrated in (7) of
Next, the control device 20 executes a bonding sequence as illustrated in (8) of
Thereafter, the control device 20 sequentially releases the holding (vacuum suction) of the upper wafer UW by the upper stage 243 from the inside to the outside. Thereupon, the upper wafer UW drops onto the lower wafer LW, and the surface of the upper wafer UW and the surface of the lower wafer LW are bonded. More specifically, a van der Waals force (intermolecular force) is generated between the modified bonding surface of the upper wafer UW and the modified bonding surface of the lower wafer LW, and the contact portions of the upper wafer UW and the lower wafer LW are bonded. Furthermore, because the respective bonding surfaces of the upper wafer UW and the lower wafer LW are hydrophilized, the hydrophilic group at the contact portion between the upper wafer UW and the lower wafer LW is hydrogen-bonded (intermolecular force), and the contact portion between the upper wafer UW and the lower wafer LW is more firmly bonded.
First, the upper wafer UW is held on the upper stage 233 through vacuum suction in each of the regions CRV, DIV, and CEV (time T1) . More specifically, the four regions CRV are arranged so as to each include an X-shaped vertex portion. The four regions DIV are arranged so as to each include a cross-shaped vertex portion. The regions CRV and DIV are alternately arranged in the vicinity of the outer periphery of the upper wafer UW. Thus, the combination of the regions CRV and DIV forms a ring-shaped region in the vicinity of the outer periphery of the upper wafer UW. The region CEV is a ring-shaped region surrounding the center portion of the upper wafer UW in plan view, and is surrounded by a set of the regions DIV and CRV. The pushpin 334 is disposed in the center portion of the region CEV.
Further, the control device 20 releases the vacuum suction of each of the regions DIV and CEV, uses the pushpin 234 to push down the center portion of the upper wafer UW, thereby bringing the surface of the upper wafer UW and the surface of the lower wafer LW into contact with each other. Thereupon, the bonding region BA spreads from the center portion of the upper wafer UW toward the outer periphery (time T2) .
When the time elapses from the time T2, in the upper wafer UW, bonding proceeds in the portion of the adjacent region CRV. On the other hand, the bonding in the portion of the region CRV of the upper wafer UW does not proceed because the vacuum suction is performed by the upper stage 233 (time T3). Such a difference in the progress of bonding may cause local stress in the upper wafer UW. As a result, the portion where the local stress is generated in the upper wafer UW can be bonded to the lower wafer LW in a distorted state. Hereinafter, a portion where the upper wafer UW is bonded to the lower wafer LW in a distorted state is referred to as the “distorted portion DP”.
Thereafter, the control device 20 releases the vacuum suction of the region CRV. Thereupon, the portion of the upper wafer UW held on the upper stage 233 in the region CRV falls to the lower wafer LW side, and the bonding region BA is formed up to the outermost periphery of the upper wafer UW as time elapses (times T4 to T5). That is, the bonding region BA is formed on the whole surface of the bonding surface between the upper wafer UW and the lower wafer LW, and the bonding between the upper wafer UW and the lower wafer LW in the bonding sequence is complete.
First, a plurality of lower wafers LW exposed by changing the wafer magnification in a predetermined exposure process is prepared. (S110). That is, in S110, two or more lower wafers LW having different wafer magnifications are prepared. The predetermined exposure process in S110 corresponds to the exposure process of the wiring layer in the vicinity of the surface of the lower wafer LW, and is a process that has a large effect on the bond OL. Throughout the present specification, this exposure process will also be referred to as a “bonding-surface exposure process for the lower wafers LW”.
Next, a plurality of upper wafers UW, which have been exposed at a fixed wafer magnification in a predetermined exposure process, are prepared. (S111). The predetermined exposure process in S111 corresponds to the exposure process of the wiring layer in the vicinity of the surface of the upper wafer UW, and is a process that has a large effect on the bond OL. Throughout the present specification, this exposure process will also be referred to as a “bonding-surface exposure process for the upper wafers UW”.
Next, the wafer magnification of each of the plurality of lower wafers is corrected so that the wafer magnification set in S110 becomes equal to the wafer magnification set in S111, and bonding process of the lower wafer LW and the upper wafer UW is executed (S112). That is, in S112, the lower wafer LW is held in a state where the lower stage 230 is deformed into a shape that is based on the wafer magnification that was set in S110, and the lower wafer LW and the upper wafer UW are bonded. Thus, the bonding process corrected in accordance with the wafer magnification of the upper wafer UW is executed for each of the lower wafers LW that have different wafer magnifications.
Next, bond OL measurement is executed (S113). Through this bond OL measurement, the bond OL measurement results are obtained for each wafer magnification that was set in S110. The bond OL measurement results are stored on the server 3, for example.
Next, the server 3 creates map correction values in which wafer magnification correction values and the bond OL measurement results are associated with each other based on the bond OL measurement results of S113 (S114). Further, the plurality of map correction values thus created are stored in the storage device 11 of the exposure apparatus 1 as the map correction value set 112. Each map correction value is associated with, for example, mutually different wafer magnification correction values in a predetermined range. This predetermined range is set based on the wafer magnification correction values set in S110, for example.
First, the respective pre-processings of the upper wafer UW and the lower wafer LW are executed. More specifically, in the pre-process of the upper wafer UW, the exposure process of the upper wafer UW is executed (S120). The correction value information 111a that includes the wafer magnification correction values used in the exposure process of S120 is stored on the server 3 (S121). On the other hand, in the pre-process of the lower wafer LW, the exposure process of the lower wafer LW is executed using map correction values that are based on the wafer magnification correction values being used (S130). More specifically, in the exposure process of S130, the exposure apparatus 1 calculates the alignment correction coefficient of the magnification component at the wafer surface based on the measurement results of the alignment marks at at least three points, and selects one correction map from the plurality of correction maps based on the magnitude of the calculated alignment correction coefficient of the magnification component. For example, the exposure apparatus 1 selects, as the map correction value to be applied to a wafer that has a large wafer magnification, a map correction value that was created based on bond OL measurement results for a bonded wafer BW that was obtained using a lower wafer LW set with a large wafer magnification in S110. In addition, the exposure apparatus 1 selects, as the map correction value to be applied to a wafer that has a small wafer magnification, a map correction value that was created based on the bond OL measurement results for a bonded wafer BW that was obtained using a lower wafer LW set with a small wafer magnification in S110. Further, the correction value information 111b that includes the wafer magnification correction values used in the exposure process of S130 is stored on the server 3 (S131).
When the respective pre-processings of the upper wafer UW and the lower wafer LW are complete (S140), the server 3 calculates the wafer magnification correction values in the bonding process based on the correction value information 111a and 111b stored in S121 and S131 respectively (S141). More specifically, in S141, the server 3 calculates the difference between the process value (alignment correction value + overlay correction value) for wafer magnification of the upper wafer UW and the process value (alignment correction value + overlay correction value) for wafer magnification of the lower wafer LW. Further, the server 3 feeds forward the calculation results of S141 to the bonding apparatus 2. Note that, in this example, “alignment correction value” is a correction value of the overlay deviation component that is calculated based on the measurement results for the alignment marks AM. The “overlay correction value” is, for example, a correction value that is calculated based on exposure OL measurement results in advanced process control executed at the time of a large-scale lot process.
Thereafter, the bonding apparatus 2 executes the bonding process by using the wafer magnification correction value calculated in S141. That is, the bonding apparatus 2 determines the wafer magnification correction value in the bonding process based on the respective exposure process alignment results for the upper wafer UW and the lower wafer LW in the pre-process. In other words, in the bonding process, the bonding apparatus 2 controls the stress device 231, based on the difference between the alignment results of the respective exposure processes of the upper wafer UW and the lower wafer LW in the pre-process, to deform the lower stage 230 ((2) in
Note that, in the above description, a case has been exemplified in which the wafer magnification correction values in the bonding process are determined using the server 3, but the present invention is not limited thereto. The exposure apparatus 1 or the bonding apparatus 2 may calculate the wafer magnification correction values in the bonding process. In this case, information regarding the wafer magnification correction values is exchanged between the exposure apparatus 1 and the bonding apparatus 2. When there is no map correction value associated with the wafer magnification correction values, the exposure apparatus 1 may use map correction values associated with the wafer magnification correction values which are close to the wafer magnification correction values, or may use map correction values which have been calculated based on a combination of a plurality of map correction values. In addition, the exposure apparatus 1 or the server 3 may create a relational expression between the wafer magnification and the correction values for each shot based on a plurality of combinations of the wafer magnification and the map correction values, and map correction values which are based on this relational expression may be used in the exposure process.
With the exposure apparatus 1 according to the first embodiment described hereinabove, it is possible to improve semiconductor device yield. Hereinafter, the advantageous effects of the exposure apparatus 1 according to the first embodiment will be described in detail.
In the case of a semiconductor device formed by bonding two wafers, the states of wafer magnification (that is, the sizes of the wafers) before one wafer is bonded to the other wafer may be different. For example, the wafer magnification may vary depending on the film stress (that is, the warpage of the wafer) on the front and back surfaces, respectively, of the wafer. For this reason, the variation in the wafer magnification may be different between one wafer and the other wafer, depending on the design of the circuit, the elements, and the like.
In addition, as described with reference to
Here, an example of a method for improving a bond overlay according to the first embodiment will be described using a comparative example. In this example, it is assumed that the variation in the wafer magnification in the pre-process of the upper wafer UW is small and that the variation in the wafer magnification in the pre-process of the lower wafer LW is large. In the following description, “overlay is favorable” corresponds to the suppression, in the exposure process, of overlay deviation between the substrate pattern and the pattern formed by the exposure process, and corresponds to suppression, in the bonding process, of overlay deviation between the pattern of the upper wafer UW and the pattern of the lower wafer LW. “Poor overlay” corresponds to the presence of a portion where the overlay deviation between the substrate pattern and the pattern formed by the exposure process is large in the exposure process, and corresponds to the presence of a portion where the overlay deviation between the pattern of the upper wafer UW and the pattern of the lower wafer LW is large in the bonding process.
As illustrated in (A) of
In the first comparative example, a map correction value MCV1 is created based on the bond OL measurement results for the bonded wafer BW1, and the map correction value MCV1 is used for process of subsequent lots. Thereupon, as illustrated in (B) of
Therefore, the exposure apparatus 1 according to the first embodiment has a function for selecting the map correction value MCV to be used according to the wafer magnification correction value in the exposure process.
In the first embodiment, the map correction value MCV1 is created based on the wafer magnification correction amount used in the exposure process of the lower wafer LW1 and the bond OL measurement results for the bonded wafer BW1, and a map correction value MCV2 is created based on the wafer magnification correction amount used in the exposure process of the lower wafer LW2 and the bond OL measurement results for the bonded wafer BW2. Further, the map correction values MCV1 and MCV2 are each stored in the storage device 11 of the exposure apparatus 1 as the map correction value set 112. Further, the map correction value set 112 is used for process of subsequent lots.
Thereupon, as illustrated in (B) of
Further, in the bonding process of the subsequent lot, the wafer magnification is corrected in the case where the lower wafer LW5 and the upper wafer UW are bonded, and the case where the lower wafer LW6 and the upper wafer UW are bonded, respectively. The bond OL measurement results for the bonded wafer BW5, obtained by bonding the lower wafer LW5 to the upper wafer UW, are favorable because the map correction value MCV1 is used, which is suitable for the magnification correction amount of the exposure process of the lower wafer LW5, thus suppressing the overlay deviation of the random component. Similarly, the bond OL measurement results for the bonded wafer BW6, obtained by bonding the lower wafer LW6 to the upper wafer UW, are favorable because the map correction value MCV2 is used, which is suitable for the magnification correction amount of the exposure process of the lower wafer LW6, thus suppressing the overlay deviation of the random component.
As described above, the exposure apparatus 1 according to the first embodiment increases the overlay deviation in the exposure process, but can suppress the overlay deviation in the bonding process. Where the effect on the yield in concerned, there may be more cases of the bond OL deteriorating than cases where the exposure OL deteriorates. In contrast, the exposure apparatus 1 according to the first embodiment suitably permits an overlay deviation in a process for which the permissible overlay deviation range is wide (for example, in a pre-process exposure process), and thus suppresses an overlay deviation in a process for which the permissible overlay deviation range is narrow (for example, in a bonding process). As a result, the exposure apparatus 1 according to the first embodiment is capable of improving semiconductor device yield.
A semiconductor manufacturing system PS according to a second embodiment has the same configuration as that of the first embodiment. In the second embodiment, the overlay deviation of the random component, which depends on the wafer magnification of a lower waver LW, is corrected using a method different from that of the first embodiment. Hereinafter, details of the semiconductor manufacturing system PS according to the second embodiment will be described.
As illustrated in
Hereinafter, an example of a specific process using the semiconductor manufacturing system PS will be described as a method for manufacturing a semiconductor device according to the second embodiment. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the second embodiment described hereinbelow.
First, as in the first embodiment, the processes of S110 to S113 are executed. That is, a plurality of lower wafers LW exposed by changing the wafer magnification in a predetermined exposure process are prepared (S110). Further, a plurality of upper wafers UW exposed at a fixed wafer magnification in a predetermined exposure process are prepared (Sill). Thereafter, the wafer magnification of the lower wafer LW is corrected so as to be equal to the wafer magnification set in S111, and a bonding process of the lower wafer LW and the upper wafer UW is executed (S112). Thereafter, bond OL measurement is executed (S113) .
Next, the server 3 creates an OL (overlay) correction formula with which wafer magnification correction values and bond OL measurement results are associated with each other based on the bond OL measurement results in S113 (S200). Further, the OL correction formula thus created is stored in, for example, the storage device 11 of the exposure apparatus 1. The OL correction formula is a relational expression between wafer magnification correction values and predetermined K values. That is, by substituting wafer magnification correction values into the OL correction formula, the K values that can be used for alignment correction by the exposure apparatus 1 can be calculated. The predetermined K values are parameters that are dependent upon the wafer magnification in the bonding process, and are, for example, K17 and K18. The K values used in the OL correction formula are not limited to K17 and K18, and other K values may be used. In the second embodiment, it suffices that at least a K value having sensitivity to the wafer magnification correction values in the bond OL is used in the OL correction formula.
In the second embodiment, the process relating to the exposure process in the pre-process of the lower wafer LW is different from that of the first embodiment. More specifically, the flowchart illustrated in
In the process of S210, the exposure process of the • lower wafer LW is executed using alignment that is based on the OL correction formula created in S200 and on the wafer magnification correction values. More specifically, in the alignment correction process (S103 in
In the process of S211, the correction value information 111b that includes the wafer magnification correction values used in S210 is stored on the server 3. When the processes of the respective pre-processings of the upper wafer UW and the lower wafer LW are complete (S140), the processes of S141 and S142 are executed as per the first embodiment. The other processes in the exposure apparatus 1 according to the second embodiment are similar to those of the first embodiment.
In the case of the exposure apparatus 1 according to the second embodiment described hereinabove, although the overlay deviation increases due to the exposure process for pre-processing the lower wafer LW in the same manner as in the first embodiment, the overlay deviation can be suppressed between the upper wafer UW and lower wafer LW during the bonding process. As a result, the exposure apparatus 1 according to the second embodiment is capable of improving semiconductor device yield similarly to the first embodiment.
In the second embodiment, a case has been exemplified where an alignment correction process is executed using a polynomial regression coefficient that is based on the wafer magnification, but the present invention is not limited thereto. A Zernike polynomial may also be used to create the OL correction formula. The Zernike polynomial is a function (orthogonal polynomial) that is defined inside a unit circle having a radius of “1”. More specifically, the Zernike polynomial is expressed by, for example, Formula (1) below.
In Formula (1), “W(x, y)” indicates a wavefront at coordinates (x, y). “Zj (x, y)” indicates the j-th Zernike polynomial. “cj” indicates a Zernike coefficient (that is, the coefficient of a Zernike polynomial) corresponding to a j-th Zernike polynomial. “J” indicates the number of Zernike polynomials used for expansion. The Zernike polynomial summation can (approximately) represent all surface shapes.
In the exposure process, the exposure apparatus 1 according to the second embodiment is capable of acquiring information on the wavefront corresponding to the wafer surface and of executing a focus on the wafer (focusing) or the like. When Zernike polynomials are used in the second embodiment, the Zernike polynomials and the coefficients that have a high correlation with the wafer magnification correction values in the bonding process are used to create the OL correction formula. In this case, in the exposure process, the exposure apparatus 1 calculates the Zernike coefficient corresponding to the surface shape of the lower wafer LW based on measurement results for the wavefront aberration, the focus, and the like. Further, the exposure apparatus 1 may change the offset value in the alignment correction process based on the numerical value obtained by substituting the predetermined Zernike coefficient into the OL correction formula. It suffices that the exposure apparatus 1 calculates the offset value using an OL correction formula that is based on at least the surface shape of the lower wafer LW and the alignment results, and uses the offset value in the alignment correction process.
A third embodiment relates to a specific example of a semiconductor device to which the method for manufacturing a semiconductor device described in the first and second embodiments can be applied. Hereinafter, as a specific example of the semiconductor device, a memory device 4, which is a NAND flash memory, will be described.
The memory I/F 40 is a hardware interface connected to an external memory controller. The memory I/F 40 performs communication according to an interface standard between the memory device 4 and the memory controller. The memory I/F 40 supports, for example, the NAND interface standard.
The sequencer 41 is a control circuit that controls the whole operation of the memory device 4. The sequencer 41 controls the driver module 43, the row decoder module 44, the sense amplifier module 45, and the like based on commands received via the memory I/F 40 to execute a read operation, a write operation, an erase operation, and the like.
The memory cell array 42 is a storage circuit that includes a set of a plurality of memory cells. The memory cell array 42 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is used, for example, as a data erase unit. A plurality of bit lines and a plurality of word lines are also provided in the memory cell array 42. Each memory cell is associated with, for example, one bit line and one word line. Each memory cell is identified based on an address identifying a word line WL and an address identifying a bit line BL.
The driver module 43 is a driver circuit that generates a voltage which is used in a read operation, a write operation, an erase operation, and the like. The driver module 43 is connected to the row decoder module 44 via a plurality of signal lines. The driver module 43 is capable of changing the voltage applied to each of the plurality of signal lines based on a page address received via the memory I/F 40.
The row decoder module 44 is a decoder that decodes row addresses received via the memory I/F 40. The row decoder module 44 selects one block BLK based on the decoding results. Further, the row decoder module 44 transfers the voltages applied to the plurality of signal lines to the plurality of wirings (word lines WL and the like) that are provided to the selected block BLK.
The sense amplifier module 45 is a sense circuit that, in a read operation, senses data which is read from the selected block BLK based on the voltage of the bit line BL. The sense amplifier module 45 transmits the read data to the memory controller via the memory I/F 40. Further, in a write operation, the sense amplifier module 45 is capable of applying, to each bit line BL, a voltage which corresponds to the data to be written to the memory cell.
Each string unit SU includes a plurality of NAND strings NS. The NAND strings NS are associated with bit lines BL0 to BLm (m is an integer of 1 or more), respectively. Different column addresses are allocated to the bit lines BL0 to BLm, respectively. Each bit line BL is shared by the NAND string NS to which the same column address is allocated among the plurality of blocks BLK. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors STD and STS.
Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is provided for each block BLK. A set of plural memory cell transistors MT connected to the common word line WL in the same string unit SU is referred to as, for example, “cell unit CU”. When each memory cell transistor MT stores 1-bit data, the cell unit CU stores “1-page data”. The cell unit CU may have a storage capacity of two page data or more according to the number of bits of data stored by the memory cell transistor MT.
Each of the select transistors STD and STS is used to select the string unit SU. The drain of the select transistor STD is connected to the associated bit line BL. The source of the select transistor STD is connected to one end of the memory cell transistors MT0 to MT7 connected in series. Gates of the select transistors STD included in the string units SU0 to SU3 are connected to select gate lines 5GD0 to SGD3, respectively. The drain of the select transistor STS is connected to the other ends of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor STS is connected to the source line SL. The gate of the select transistor STS is connected to the select gate line SGS. The source line SL is shared by a plurality of blocks BLK, for example.
Hereinafter, an example of the structure of the memory device 4 according to the third embodiment will be described. Note that, in the third embodiment, the X direction corresponds to the direction of extension of the word lines WL, the Y direction corresponds to the direction of extension of the bit lines BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate used to form the memory device 4.
The memory region MR includes a memory cell array 42. The hookup regions HR1 and HR2 include wiring or the like that is used for interconnecting the stacked wiring provided to the memory chip MC, and the row decoder module 44 provided to the CMOS chip CC. The pad region PR1 includes a pad or the like that is used for a connection between the memory device 4 and the memory controller. The hookup regions HR1 and HR2 sandwich the memory region MR in the X direction. The pad region PR1 is adjacent, in the Y direction, to the memory region MR and the hookup regions HR1 and HR2, respectively.
The sense amplifier region SR includes a sense amplifier module 45. The peripheral circuit region PERI includes a sequencer 41, a driver module 43, and the like. The transfer regions XR1 and XR2 include a row decoder module 44. The pad region PR2 includes a memory I/F 40. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap the memory region MR. The transfer regions XR1 and XR2 sandwich a set of the sense amplifier region SR and the peripheral circuit region PERI in the X direction, and overlap the hookup regions HR1 and HR2, respectively. The pad region PR2 overlaps the pad region PR1 of the memory chip MC.
The memory chip MC includes a plurality of attachment pads BP below the memory region MR, the hookup regions HR1 and HR2, and the pad region PR1, respectively. The attachment pads BP of the memory region MR are connected to the associated bit lines BL. The attachment pads BP of the hookup regions HR are connected to associated wiring (for example, word lines WL) among the stacked wiring provided to the memory region MR. The attachment pad BP of the pad region PR1 is connected to a pad (not illustrated) provided to the upper surface of the memory chip MC. The pad provided to the upper surface of the memory chip MC is used, for example, for a connection between the memory device 4 and the memory controller.
The CMOS chip CC includes a plurality of attachment pads BP above the sense amplifier region SR, the peripheral circuit region PERI, the transfer regions XR1 and XR2, and the pad region PR2, respectively. The attachment pad BP of the sense amplifier region SR overlaps the attachment pad BP of the memory region MR. The attachment pads BP of the transfer regions XR1 and XR2 overlap the attachment pads BP of the hookup regions HR1 and HR2, respectively. The attachment pad BP of the pad region PR1 overlaps the attachment pad BP of the pad region PR2.
The memory device 4 has a structure in which the lower surface of the memory chip MC and the upper surface of the CMOS chip CC are bonded to each other. Among the plurality of attachment pads BP provided to the memory device 4, two attachment pads BP facing each other between the memory chip MC and the CMOS chip CC are electrically connected through bonding. Thus, the circuit in the memory chip MC and the circuit in the CMOS chip CC are electrically interconnected via the attachment pads BP. A set of two attachment pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated with one another.
Each slit SLT has, for example, a structure in which an insulating member is embedded. Each slit SLT insulates adjacent wirings (for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS) via the slit SLT. Each slit SLT has a portion that is provided so as to extend along the X direction and that crosses the memory region MR and the hookup regions HR1 and HR2, along the X direction. The plurality of slits SLT are arranged in the Y direction. The regions that are delimited by the slits SLT correspond to the blocks BLK.
Each slit SHE has, for example, a structure in which an insulating member is embedded. The slits SHE insulate adjacent wirings (at least select gate line SGD) from each other via the slits SLT. Each slit SHE has a portion that is provided so as to extend along the X direction and that crosses the memory region MR. The plurality of slits SHE are arranged in the Y direction. In this example, three slits SHE are arranged between adjacent slits SLT. The plurality of regions partitioned by the slits SLT and SHE correspond to the string units SU0 to SU3, respectively.
Each memory pillar MP functions as, for example, one NAND string NS. The plurality of memory pillars MP are arranged in a staggered manner of, for example, 19 rows in a region between two adjacent slits SLT. Further, one slit SHE overlaps the memory pillar MP of the fifth column, the memory pillar MP of the 10 column, and the memory pillar MP of the 15 column, respectively, from the upper side of the paper surface.
Each of the bit lines BL has a portion that is provided so as to extend along the Y direction, and that crosses a region where the plurality of blocks BLK are provided, along the Y direction. The plurality of bit lines BL are arranged in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP, for each string unit SU. In this example, two bit lines BL overlap each memory pillar MP.
Each contact CV is provided between one bit line BL among the plurality of bit lines BL overlapping the memory pillar MP, and the memory pillar MP. The contact CV electrically interconnects the memory pillar MP and the bit line BL. Note that the contact CV between the memory pillar MP overlapping the slit SHE and the bit line BL is omitted.
The insulating layer 50 is provided, for example, in the lowermost layer of the memory chip MC. The conductive layer 60 is provided on the insulating layer 50. The insulating layer 51 is provided on the conductive layer 60. The conductive layer 61 and the insulating layer 52 are alternately provided on the insulating layer 51. The insulating layer 53 is provided on the uppermost conductive layer 61. The conductive layer 62 and the insulating layer 54 are alternately provided on the insulating layer 53. The insulating layer 55 is provided on the uppermost conductive layer 62. The conductive layer 63 and the insulating layer 56 are alternately provided on the insulating layer 55. The insulating layer 57 is provided on the uppermost conductive layer 63. The conductive layer 64 is provided on the insulating layer 57. The contact V1 is provided on the conductive layer 64. The conductive layer 65 is provided on the contact V1. The contact V2 is provided on the conductive layer 65. The conductive layer 66 is provided on the contact V2. Hereinafter, the wiring layers provided with the conductive layers 64, 65, and 66 are referred to as “M0”, “M1”, and “M2”, respectively.
Each of the conductive layers 60, 61, 62, and 63 is formed in, for example, a plate shape that extends along the XY plane. The conductive layer 64 is formed in, for example, a line shape that extends in the Y direction. The conductive layers 60, 61, and 63 are used as a source line SL, a select gate line SGS, and a select gate line SGD, respectively. The plurality of conductive layers 62 are used as the word lines WL0 to WL7, respectively, in order from the conductive layer 60 side. The conductive layer 64 is used as the bit line BL. The contacts V1 and V2 are provided in a columnar shape. The conductive layers 64 and 65 are interconnected via the contact V1. The conductive layer 65 and the conductive layer 66 are interconnected via a contact V2. The conductive layer 65 is, for example, wiring formed in a line shape that extends in the X direction. The conductive layer 66 is in contact with the interface of the memory chip MC and is used as an attachment pad BP. The conductive layer 66 contains copper, for example.
The slit SLT has a portion formed in a plate shape that extends along the XZ plane, and divides the insulating layers 51 to 56 and the conductive layers 61 to 63. Each memory pillar MP is provided so as to extend along the Z direction, and penetrates the insulating layers 51 to 56 and the conductive layers 61 to 63. Each memory pillar MP includes, for example, a core member 70, a semiconductor layer 71, and a stacked film 72. The core member 70 is an insulator provided so as to extend along the Z direction. The semiconductor layer 71 covers the core member 70. A lower portion of the semiconductor layer 71 is in contact with the conductive layer 60. The stacked film 72 covers the lateral surface of the semiconductor layer 71. The contact CV is provided on the semiconductor layer 71. The conductive layer 64 is in contact with the top of contact CV.
Note that, in the illustrated region, the contact CV corresponding to one memory pillar MP of the two memory pillars MP is illustrated. The contacts CV are connected in a region (not illustrated) to the memory pillar MP to which the contacts CV are not connected in the region. A portion where the memory pillar MP intersects the plurality of conductive layers 61 functions as the select transistor STS. The portion where the memory pillar MP intersects the conductive layer 62 functions as the memory cell transistor MT. The portion where the memory pillar MP intersects the plurality of conductive layers 63 functions as the select transistor STD.
The core member 70 is provided, for example, at the center portion of the memory pillar MP. The semiconductor layer 71 surrounds the lateral surface of the core member 70. The tunnel insulating film 73 surrounds the lateral surface of the semiconductor layer 71. The insulating film 74 surrounds the lateral surface of the tunnel insulating film 73. The block insulating film 75 surrounds the lateral surface of the insulating film 74. The conductive layer 62 surrounds the lateral surface of the block insulating film 75. The semiconductor layer 71 is used as a channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors STD and STS. Each of the tunnel insulating film 73 and the block insulating film 75 contains, for example, silicon oxide. The insulating film 74 is used as the charge storage layer of the memory cell transistor MT, and includes, for example, silicon nitride. As a result, each of the memory pillars MP functions as one NAND string NS.
The semiconductor substrate 80 is a substrate that is used to form the CMOS chip CC. The semiconductor substrate 80 includes a plurality of well regions (not illustrated). For example, a transistor TR is formed in each of the plurality of well regions. The plurality of well regions are separated by shallow trench isolation (STI), for example. A conductive layer GC is provided on the semiconductor substrate 80 via a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as a gate electrode of the transistor TR included in the sense amplifier module 45. The contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 80 in correspondence with the source and the drain of the transistor TR.
The conductive layer 81 is provided on the contact CS and the contact C0, respectively. The contact C1 is provided on the conductive layer 81. The conductive layer 82 is provided on the contact C1. The conductive layers 81 and 82 are electrically interconnected via the contact C1. The contact C2 is provided on the conductive layer 82. The conductive layer 83 is provided on the contact C2. The conductive layers 82 and 83 are electrically interconnected via the contact C2. The contact C3 is provided on the conductive layer 83. The conductive layer 84 is provided on the contact C3. The conductive layers 83 and 84 are electrically connected via the contact C3. Hereinafter, the wiring layers on which the conductive layers 81 to 84 are provided are referred to as “D0”, “D1”, “D2”, and “D3”, respectively.
The conductive layer 84 is in contact with the interface of the CMOS chip CC and is used as an attachment pad BP. The conductive layer 84 in the sense amplifier region SR is bonded to the conductive layer 66 (that is, the attachment pad BP of the memory chip MC) in the memory region MR that is arranged to face the conductive layer 84. Further, each conductive layer 84 in the sense amplifier region SR is electrically connected to one bit line BL. The conductive layer 84 contains copper, for example.
In the memory device 4, the wiring layer D3 of the CMOS chip CC and the wiring layer M2 of the memory chip MC are adjacent to each other due to the memory chip MC and the CMOS chip CC being bonded to each other. The semiconductor substrate 80 corresponds to the back surface side of the upper wafer UW, and the wiring layer D3 corresponds to the front surface side of the upper wafer UW. The insulating layer 50 corresponds to the back surface side of the lower wafer LW, and the wiring layer M2 corresponds to the front surface side of the lower wafer LW. The semiconductor substrate, which is used to form the memory chip MC, is removed along with processes such as pad formation after the bonding process.
As described hereinabove, the memory device 4 includes, for example, the memory chip MC, which includes a structure in which memory cells are three-dimensionally stacked, and the CMOS chip CC, which includes other control circuits and the like. In the memory chip MC and the CMOS chip CC, the variation in wafer magnification tends to be larger between the wafers in the memory chip MC. More specifically, because the memory chip MC includes the memory cell array 42 formed in a high layer, the variation in the amount of warpage of the wafer increases, and the variation in wafer magnification may increase. On the other hand, the arrangement of the shots of the CMOS chip CC is close to an ideal lattice that is based on the exposure apparatus. Therefore, when the bonding process is executed, the wafer whereon the memory chip MC is formed is preferably allocated to the lower wafer LW that enables wafer magnification to be corrected, and the wafer whereon the CMOS chip CC is formed is preferably allocated to the upper wafer UW. Thus, the first and second embodiments each enable the yield of the memory device 4 to be improved.
A semiconductor manufacturing system PS according to a fourth embodiment has a configuration similar to that of the first embodiment. In the fourth embodiment, the overlay deviation of a random component, which depends on the amount of warpage of the upper wafer UW, is corrected using a method similar to that of the first embodiment. The semiconductor manufacturing system PS according to the fourth embodiment will be described in detail below.
Hereinafter, as a method for manufacturing a semiconductor device according to the fourth embodiment, an example of a specific process using the exposure apparatus 1 will be described. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the first embodiment described hereinbelow.
First, a plurality of upper wafers UW having different amounts of warpage are prepared, upon each of which an exposure process is executed (S300). That is, in the process in S300, two or more upper wafers UW that have different amounts of warpage are prepared. The exposure process in S300 corresponds to a bonding-surface exposure process for the upper wafers UW.
Next, a plurality of lower wafers LW having approximately the same amount of warpage are prepared, upon each of which an exposure process is executed (S301). That is, in the process in S301, two or more lower wafers LW that have approximately the same amount of warpage are prepared. The exposure process in S301 corresponds to the bonding-surface exposure process for the lower wafers LW.
Next, a bonding process is executed upon the lower wafers LW and upper wafers UW (S302) . In this manner, a plurality of bonded wafers BW incorporating the upper wafers UW, whose amounts of warpage differ from each other, are formed.
Next, bond OL measurement is executed (S303). Through this bond OL measurement, the bond OL measurement results are obtained for each amount of warpage pertaining to the upper wafers UW set in the process of S300. The bond OL measurement results are stored on the server 3, for example.
Next, the server 3 creates, based on the bond OL measurement results obtained in the process of S303, map correction values in which the amounts of warpage of the wafers and the bond OL measurement results are associated with each other (S304). Further, the plurality of map correction values thus created are stored in the storage device 11 of the exposure apparatus 1 as the map correction value set 112. Each of the map correction values is associated with, for example, a respective one of the amounts of warpage of the wafers in certain ranges that differ from each other. A certain range is set as a reference for the amounts of warpage of the wafers set in S300, for example.
Even if the lower wafers LW have different amounts of warpage, this will have a small effect upon the map correction values created in S304. The amounts of warpage therefore may differ from each other among the lower wafers LW prepared in the process of S301.
First, the amount of warpage of an upper wafer UW, which is the bonding-surface exposure target, is measured (S310). The data of the amount of warpage of the upper wafer UW is transferred, for example, to the exposure apparatus 1 via the server 3, and stored in the storage device 11 of the exposure apparatus 1.
Next, an exposure process is executed on the bonding surface of the upper wafer UW, using a map correction value corresponding to the measured amount of warpage (S311). For example, the exposure apparatus 1 selects, as a map correction value to be applied to a wafer having a large amount of warpage, a map correction value created based on the bond OL measurement results of a bonded wafer BW obtained using an upper wafer UW with a large amount of warpage. The exposure apparatus 1 further selects, as a map correction value to be applied to a wafer having a small amount of warpage, a map correction value created based on the bond OL measurement results of a bonded wafer BW obtained using an upper wafer UW with a small amount of warpage.
In parallel with the processes in S310 and S311, a pre-processing is executed on the lower wafer LW (S320). As a result, a lower wafer LW is formed.
After the respective pre-processings of the upper wafer UW and the lower wafer LW are completed (in other words, the pre-processing upon each of the upper wafer UW and lower wafer LW that are associated with each other is completed) (S330), a bonding process is executed (S331). In this manner, a bonded wafer BW is formed in which the associated upper wafer UW and lower wafer LW are bonded to each other.
Note that, if there is no map correction value associated with the amount of warpage, the exposure apparatus 1 may use a map correction value associated with an amount of warpage close to the amount of warpage of this wafer, or may use a map correction value calculated based on a combination of a plurality of map correction values. Moreover, the exposure apparatus 1 or the server 3 may create, for each shot, a relational expression between the amounts of warpage of a wafer and the overlay correction values based on a plurality of combinations of the amounts of warpage and the map correction values so that map correction values which are based on this relational expression can be used in the exposure process.
In a semiconductor device formed by bonding two wafers, an overlay deviation of a random component may occur in the bond overlay (OL) in accordance with an amount of warpage of the upper wafer UW. One of the factors responsible for this may be a stress applied to the upper wafer UW during the bonding process, which may vary in accordance with the amount of warpage of the upper wafer UW. If the stress applied to the upper wafer UW varies, the stress on the upper wafer UW at the time of the upper wafer UW coming off the upper stage 233 and falling upon the lower wafer LW may vary during the bonding process, which may produce an overlay deviation. As a method for suppressing such an overlay deviation of the random component in a bonded wafer BW, an exposure map correction that can improve the bond OL may be used in a predetermined exposure process of the pre-processing.
Here, an example of a method for improving a bond overlay according to the fourth embodiment will be described using a second comparative example. In this example, it is assumed that the variation in the amounts of warpage of the lower wafers LW is small in the pre-processing and that the variation in the amounts of warpage of the upper wafers UW is large in the pre-process.
As illustrated in (A) of
In the second comparative example, a map correction value MCV3 is created based on the bond OL measurement results for the bonded wafer BW1, and this map correction value MCV3 is used for the process of subsequent lots. Thereupon, as illustrated in (B) of
However, the overlay deviation tendency of the random component may change according to the amount of warpage of the upper wafer UW. In the bonded wafer BW4 obtained by bonding the upper wafer UW4 to a lower wafer LW, the map correction value MCV3 corresponding to a “large amount of warpage” is used even though the amount of warpage of the wafer is small in the exposure process. This may worsen the improvement amount of the overlay deviation of the random component than in the bonded wafer BW3. As indicated in this example, the tendency of the map of the overlay may produce differences depending on the amount of warpage in the upper wafer UW. As a result, the improvement amount of the overlay may decrease depending on the amount of warpage of the upper wafer UW in the second comparative example.
The exposure apparatus 1 according to the fourth embodiment has a function for selecting a map correction value MCV to be used in the exposure process for the bonding surface of the upper wafer UW in accordance with the amount of warpage of the upper wafer UW.
In the fourth embodiment, a map correction value MCV3 is created based on the amount of warpage of the upper wafer UW1 measured before the exposure process upon the bonding surface of the upper wafer UW1, and the bond OL measurement result of the bonded wafer BW1. Similarly, a map correction value MCV4 is created based on the amount of warpage of the upper wafer UW2 measured before the exposure process upon the bonding surface of the upper wafer UW2 and the bond OL measurement result of the bonded wafer BW2. Further, the map correction values MCV3 and MCV4 are each stored in the storage device 11 of the exposure apparatus 1 as the map correction value set 112. Thereafter, the map correction value set 112 is used for the process of subsequent lots.
Thereupon, as illustrated in (B) of
In the bonding process, a bonded wafer BW5 is formed using the upper wafer UW5 and the corresponding lower wafer LW, and a bonded wafer BW6 is formed using the upper wafer UW6 and the corresponding lower wafer LW. The bond OL measurement results for the bonded wafer BW5 may demonstrate that the overlay is favorable with the overlay deviation of the random component being suppressed because the map correction value MCV3 suitable for the amount of warpage of the upper wafer UW5 is used in the exposure process of the bonding surface of the upper wafer UW5. Similarly, the bond OL measurement results for the bonded wafer BW6 may demonstrate that the overlay is favorable with the overlay deviation of the random component being suppressed because the map correction value MCV4 suitable for the amount of warpage of the upper wafer UW6 is used in the exposure process of the bonding surface of the upper wafer UW6.
As described above, the exposure apparatus 1 according to the fourth embodiment can suppress the overlay deviation in the bonding process even though the overlay deviation in the exposure process of the bonding surface of the upper wafer UW may increase. Where the effect on the yield is concerned, in general, the degree of deterioration in the bond OL may be worse than the degree of deterioration in the exposure OL of the bonding surface of the upper wafer UW. In contrast, the exposure apparatus 1 according to the fourth embodiment suitably permits an overlay deviation in a process that allows for a large overlay deviation range (for example, in a pre-process exposure process). Thus, the exposure apparatus 1 according to the fourth embodiment suppresses an overlay deviation in a process that allows for only a small overlay deviation range (for example, in the bonding process). As a result, the exposure apparatus 1 according to the fourth embodiment is capable of improving semiconductor device yield similarly to the first embodiment.
A semiconductor manufacturing system PS according to a fifth embodiment has a configuration similar to that of the first embodiment. In the fifth embodiment, the overlay deviation of the random component depending on the amount of warpage of an upper wafer UW is corrected using a method similar to that of the second embodiment. Hereinafter, details of the semiconductor manufacturing system PS according to the fifth embodiment will be described.
As illustrated in
Hereinafter, an example of a specific process using the semiconductor manufacturing system PS will be described as a method for manufacturing a semiconductor device according to the fifth embodiment. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the fifth embodiment, which is described hereinbelow.
First, in the same manner as in the fourth embodiment, the processes of S300 to S303 are executed. That is, a plurality of upper wafers UW having different amounts of warpage are prepared, and an exposure process is executed upon the bonding surfaces of the upper wafers UW (S300). A plurality of lower wafers LW having approximately the same amount of warpage are prepared, and an exposure process is executed upon the bonding surfaces of the lower wafers LW (S301). Thereafter, a bonding process is executed upon a lower wafer LW and an upper wafer UW (S302). Then, a bond OL measurement is performed on each of a plurality of bonded wafers BW formed in the process of S302 (S303).
Next, the server 3 creates an overlay (OL) correction formula by which the amount of warpage of the upper wafer UW and the bond OL measurement results are associated with each other, based on the bond OL measurement results obtained in the process of S303 (S400). The OL correction formula thus created is stored in, for example, the storage device 11 of the exposure apparatus 1. The OL correction formula is a relational expression between the amount of warpage of the upper wafer UW and the predetermined K value. That is, by substituting the measured value for the amount of warpage of the upper wafer UW into the OL correction formula, a correction value for the K value, which can be used for alignment correction by the exposure apparatus 1, can be calculated. The predetermined K value is a parameter dependent upon the amount of warpage of the upper wafer UW, and includes, for example, K17 and K18. The K values used in the OL correction formula are not limited to K17 and K18, and other K values may be used. In the fifth embodiment, it suffices that at least a K value exhibiting sensitivity to the amount of warpage of the upper wafer UW in the bond OL is used in the OL correction formula.
First, the amount of warpage of the upper wafer UW, which is the bonding-surface exposure target, is measured (S310). The data of the amount of warpage of the upper wafer UW is transferred, for example, to the exposure apparatus 1 via the server 3, and stored in the storage device 11 of the exposure apparatus 1.
Next, an exposure process is executed on the bonding surface of the upper wafer UW, using the OL correction formula created in the process of S400 and the OL correction value based on the amount of warpage of the upper wafer UW calculated in the process of S310 (S410). Specifically, the exposure apparatus 1 according to the fifth embodiment first calculates the OL correction values, for example, for K17 and K18 by substituting the value for the amount of warpage of the upper wafer UW into the OL correction formula. Then, in the alignment correction process (S103 in
In parallel with the processes in S310 and S311, a pre-processing is executed upon the lower wafer LW (S320). As a result, a lower wafer LW is formed.
After the respective pre-processings of the upper wafer UW and the lower wafer LW are completed (S330), a bonding process is executed (S331). In this manner, a bonded wafer BW, in which the upper wafer UW and corresponding lower wafer LW are bonded to each other, is formed. The other processes in the exposure apparatus 1 according to the fifth embodiment are similar to those of the fourth embodiment.
In the exposure apparatus 1 according to the fifth embodiment described hereinabove, the overlay deviation in the bonding process can be suppressed, even though the overlay deviation in the upper wafer UW in the exposure process increases, in the same manner as in the fourth embodiment. As a result, the exposure apparatus 1 according to the fifth embodiment is capable of improving semiconductor device yield similarly to the fourth embodiment.
For the creation of the OL correction formula according to the fifth embodiment, a Zernike polynomial may be used as in the modification of the second embodiment. In this example, an OL correction formula is created by using a Zernike coefficient having a high correlation with the amount of warpage of the upper wafer UW. The exposure apparatus 1 calculates a correction value for the Zernike coefficient based on the amount of warpage of the upper wafer UW, and uses this value for the alignment correction process. That is, the exposure apparatus 1 may correct the value of a specific Zernike coefficient for the alignment correction based on the specific correction value of the Zernike coefficient calculated based on the amount of warpage of the upper wafer UW. When a Zernike polynomial is used for creation of an OL correction formula, an overlay deviation can be suppressed in the bonding process in the same manner as in the use of a polynomial regression coefficient.
In the above embodiments, the flowchart used to describe the operations is merely an example. The operations described using the flowchart are interchangeable within a range permitting the order of processing, and further processes may be added, or some processes may be omitted. In the foregoing embodiment, a case where bonding is performed by applying alignment correction to the lower wafer LW placed (held) on the lower stage 230 has been exemplified, but the present invention is not limited thereto. The alignment correction in the bonding process may also be applied to, for example, the upper wafer UW placed (held) on the upper stage 233, or may be applied to both the upper wafer UW held on the upper stage 233 and the lower wafer LW held on the lower stage 230. The fourth embodiment may be combined with any of the first to third embodiments. The fifth embodiment may be combined with any of the first to third embodiments. In this specification, a micro processing unit (MPU), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like, may also be used instead of the CPU. Furthermore, each of the processes described in the embodiment may also be realized using dedicated hardware. The processing described in the embodiment may be a mixture of processing executed by software and processing executed by hardware, or only either one of such processing may be used.
The amount of warpage of a wafer may be measured by the exposure apparatus 1, or by an externally provided measurement apparatus. Throughout the present specification, the amount of warpage of a wafer is expressed, for example, by a difference between the heights of the wafer at its peripheral portion and at its central portion. A micrometer (µm) may be used as a unit of the amount of warpage of the wafer. The amount of warpage of a wafer may be expressed by a signed distance from a three-point reference plane, based on the measurement results of the height of the wafer at the center. The amount of warpage of the wafer may be set, for example, to a positive value if it is above the three-point reference plane and to a negative value if it is below the plane. The amount of warpage of a wafer may be measured through the calculation of the geometry (warpage) of the wafer by measuring the heights at different coordinates of the wafer using, for example, a laser displacement gauge, a confocal displacement gauge, a capacitance formula, a heterodyne interferometer, and a Fizeau interferometer.
In the present specification, a “connection” indicates that two elements are electrically connected, and does not preclude another element being interposed therebetween. “Electrically connected” may signify that an insulator is interposed, as long as operation like that afforded by an electrical connection is possible. “Columnar shape” indicates a structure that is provided in a hole formed in the manufacturing process. The “plan view” corresponds to, for example, viewing an object in a direction perpendicular to the surface of the semiconductor substrate 80. A “region” may be regarded as a configuration that is contained by the semiconductor substrate 80 of the CMOS chip CC. For example, in a case where it is prescribed that the semiconductor substrate 80 includes the memory region MR, the memory region MR is associated with a region above the semiconductor substrate 80. The attachment pads BP may also be referred to as “joint metal”. The camera 144 of the exposure apparatus 1 may also be configured by being divided into an optical system (microscope) and a light receiving sensor. Each of the cameras 144, 232, and 235 may be referred to as a “measurement device” as long as same are capable of measuring the alignment marks AM. In the present specification, “overlap deviation” may also be paraphrased as “misalignment”.
The configuration described in the third embodiment is merely an example, and the configuration of the memory device 4 is not limited thereto. The circuit configuration, planar layout, and cross-sectional structure of the memory device 4 can be appropriately changed according to the design of the memory device 4. For example, although a case where the memory chip MC is provided on the CMOS chip CC has been given by way of an example in the third embodiment, the CMOS chip CC may also be provided on the memory chip MC. Although a case where the memory chip MC is allocated to the lower wafer LW and the CMOS chip CC is allocated to the upper wafer UW has been given by way of an example, the memory chip MC may be allocated to the upper wafer UW, and the CMOS chip CC may be allocated to the lower wafer LW. When the manufacturing method described in the first and second embodiments is applied, a wafer exhibiting a large variation in wafer magnification between wafers is preferably allocated to the lower wafer LW. Thus, because overlay deviation in the bonding process can be suppressed, the occurrence of defects caused by such overlay deviation can be suppressed.
Some or all of the embodiments described above can be described as in the following supplementary notes, but is not limited thereto:
A method for manufacturing a semiconductor device, comprising:
The method according to Supplementary Note 1, wherein the first alignment correction coefficient corresponds to misalignment of a magnification component.
The method according to Supplementary Note 1, wherein the second alignment correction coefficient is calculated from the polynomial regression, and is corrected based on the magnitude of the first alignment correction coefficient.
The method according to Supplementary Note 3, wherein
The method according to Supplementary Note 1, wherein the second alignment correction coefficient is a coefficient of a Zernike polynomial.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-009549 | Jan 2022 | JP | national |
| 2022-124977 | Aug 2022 | JP | national |
