Patent Application
20080176150
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-11461, filed on Jan. 22, 2007, the disclosure of which is incorporated herein in its entirety by reference.
The present invention relates to improvement of a lithography process when manufacturing a semiconductor device and, in particular, to an exposure mask and a method of forming a pattern of the semiconductor device which are used for a fine dimension of a submicron region.
With the recent development of a manufacturing technology of a semiconductor device, a semiconductor device in which elements are integrated with high density has come into practical use. For example, in a Dynamic Random Access Memory, a memory having a storage capacity of 1 Gbit has come into practical use. With the high integration of the semiconductor device, an element pattern is to be miniaturized. Although a current minimum processing dimension is a submicron region, further miniaturization is considered for main purposes of cost reduction of an integrated circuit device and speed-up of an operating speed.
In a lithography process for manufacturing a semiconductor device, a reduced projection exposure apparatus (a stepper) is used. In the stepper, a pattern on an exposure mask (hereinafter, referred to as a “reticle mask”) is reduced and projected to a semiconductor substrate on a stage. When one shot exposure is terminated, the stage is moved in X and Y directions and next shot exposure is then carried out. By repeating such an operation, an overall surface of the semiconductor substrate is exposed. As an exposing light source, a light source of a short wavelength such as visible light (g-ray: wavelength of 436 nm), ultraviolet rays (i-ray: wavelength of 365 nm), a KrF laser (wavelength of 248 nm), and an ArF laser (wavelength of 193 nm) is used. There are various reticle masks that reduced projection ratio is in the range of 1/4to 1/10 or the like.
Exposure by a stepper will be described with reference to
An element pattern is miniaturized with high integration of the semiconductor device, whereby a dimension of the light shielding element pattern 4 in the reticle mask 1 becomes smaller. Thus, in the case of a thickness of each of a light shielding element pattern and resist film according a related art, an image projected in the resist film includes a light shielding element and a Fresnel diffraction area in the vicinity of the light shielding element, and further includes a Fraunhofer diffraction area far from the light shielding element. As a result, as shown in
A representative example of the related art is shown in a column of the related art of Table 1. In the case where incident light wavelength λ is 248 nm and a minimum opening dimension D of the light shielding element pattern 4 in the reticle mask 1 is 90 nm, it meets D*D/λ=32.7 nm. The equation D*D/λ will be described later. In the case where the thickness of the resist film 8 is 480 nm and the reduced projection ratio is 1/4, a portion of 1920 nm in the area of the reticle mask 1 with respect to a traveling direction of the incident light is an area to be projected. However, as shown in Table 1, since the thickness of a representative light shielding element currently used is about 150 nm, the thickness of 150 nm of the light shielding element reaches less than 10% as long as the necessary dimension of 1920 nm. Even a value (314 nm) of the sum of the dimension of the light shielding element and the dimension of 5*D*D/λ=163.5 nm) reaches merely about 16% of the necessary dimension in the related art. Therefore, in the related art, not only a pattern image of the light shielding element is projected in the resist film, but also an image of the Fraunhofer diffraction area is projected.
The Fraunhofer diffraction area is an area in which a distance (a distance with respect to the traveling direction of the exposing light) Z from a bottom end surface of the light shielding element becomes D*D/λ<<Z. In this area, deformation of the light shielding element pattern and/or a sub peak becomes marked. As a concrete example, an example in which a resist pattern 12 is formed in a resist film 8 having a film thickness of 0.5 μm by means of ¼ reduced projection exposure to a rectangular hole pattern 11 is shown in
As mentioned above, there is a problem that an image fogged and widely deformed from an original light shielding element pattern is projected in the resist film due to diffraction of the incident light. Further, since the film thickness of the light shielding element in the reticle mask is thinner, a projection image including an area in which diffraction of light passing through the opening pattern by the light shielding element occurs remarkably is formed in the resist film. As a result, there is a problem that a depth of focus (DOF) is small in view of a practical aspect. Moreover, the thickness of the resist film is set to be thicker in associated with processing of the film to be processed. Thus, there is a problem that the resist film is too thick compared with the film thickness of the light shielding element in the reticle mask and this causes low resolution. Furthermore, a technique to form the light shielding element by simply etching processing of a film made of chromium or the like with a resist mask has been adopted. Thus, there is also a problem that a yield on formation of the light shielding element pattern having a thick film thickness is lowered.
Following documents are related art documents relating to a lithography process of manufacturing a semiconductor device and a reticle mask. Patent Document 1 (Japanese Patent Application Publication No. 6-097029) discloses a pattern forming method in which a thickness of a light shielding element pattern in an oblique light incident exposure mask is made thicker, thereby obtaining a dimension near a design dimension. Further, an upper limit and a lower limit of the thickness of the light shielding element pattern are defined on the basis of an exposure wavelength λ, a numerical aperture NA, a projection exposure magnification (a reduced projection ratio) 1/m and a value a obtained by dividing a gap amount from the center of an opening diaphragm by a radius of the opening diaphragm. Patent Document 2 (Japanese Patent Application Publication No. 10-010703) discloses that a thickness of a light shielding element (chromium) pattern is set to a value in the proximity of n (where “n” is an integer number) times of ½ of an exposure wavelength to be used, thereby reducing an influence of comatic aberration of projection optics.
In Patent Document 3 (Japanese Patent Application Publication No. 2005-182031), in order to solve a problem to improve projection contrast, a thickness of a light shielding element in an exposure mask is set so as to be larger than a wavelength of exposing light, and so as to be less than three or four times as much as a width of the light shielding element pattern. As a principle to heighten contrast, by making the thickness of the light shielding element larger, an absorption ratio of TM polarization against TE polarization is increased, whereby the contrast is improved because interference of the TE polarization is increased at a semiconductor substrate level. The upper limit of the thickness of the light shielding element is set to three or four times as much as the width of the light shielding element pattern in accordance with intense shortness and cost of manufacture.
Patent Document 4 (Japanese Patent Application Publication No. 2005-50851), Patent Document 5 (Japanese Patent Application Publication No. 2004-4715), Patent Document 6 (Japanese Patent Application Publication No. 2004-77808), Patent Document 7 (Japanese Patent Application Publication No. 5-323563), and Patent Document 8 (Japanese Patent Application Publication No. 5-119464) respectively disclose that a light shielding element is achieved from one made of chromium oxide and having a thickness of 100 to 200 nm, one configured from a bilayer of chromium oxide and chromium and having a thickness of 50 to 120 nm, one configured from a bilayer structure of a chromium thin film having a thickness of 800 nm and a low-reflection chromium thin film having a thickness of 400 nm, one configured from a metal thin film layer having a thickness of 5 to 500 nm, and one configured from a light impermeable chromium film having a thickness of 50 to 300 nm. Although there are descriptions relating to a film thickness of a light shielding element of a mask in these Patent Documents, there is no explanation for a relationship to a resist film thickness. Therefore, there is no description about technical suggestion relating to the present invention.
As described above, in the related art, in the case where the thickness of the light shielding element is smaller and the thickness of the resist film is larger, there is a problem that a pattern (a projection image) to be projected in the resist film is fogged and widely deformed due to diffraction of the exposing light (problem 1). A film thickness of the light shielding element pattern in the reticle mask is smaller, and a projection image including an area in which diffraction of the exposing light passing through an opening pattern by the light shielding element occurs remarkably is formed in the resist film. As a result, there is a problem that the depth of focus is smaller in view of the practical aspect (problem 2). Further, there is a problem that resolution is lowered because the thickness of the resist film is made larger in associated with processing of the film to be processed (problem 3).
The present invention aims to solve the problems described above by analyzing causes of pattern deformation on formation of an exposure pattern and taking a wave-optical approach.
More specifically, the present invention aims to provide a reticle mask suitable for a fine processing dimension and a pattern forming method for a semiconductor device.
According to a first aspect of the present invention, a method of forming a pattern is provided. The method comprises preparing a reduced projection exposure apparatus having a reduced projection ratio 1/m and a wavelength λ (nm) of exposing light and patterning a light shielding element pattern of a reticle mask on a resist film having a thickness tr (nm). The light shielding element pattern has a pattern opening portion having a minimum opening dimension D (nm). In this case, a thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr≦t0+5*D*D/λ.
In the first aspect, the thickness t0 of the light shielding element pattern may be set so as to meet a relational equation of m*tr≦t0+D*D/λ.
According to a second aspect of the present invention, a reticle mask is provided. The reticle mask is used in a reduced projection exposure apparatus having a reduced projection ratio 1/m and a wavelength λ (nm) of exposing light, and is used for patterning on a resist film having a thickness tr (nm). The reticle mask comprises a light shielding element pattern having a pattern opening portion with a minimum opening dimension D (nm). A thickness t0 of the light shielding element pattern is set so as to meet a relational equation of m*tr≦t0+5*D*D/λ.
According to a third aspect of the present invention, a method of manufacturing the reticle mask mentioned in the above second aspect is provided. The method comprises forming a groove in a reticle substrate, the groove having a depth t0 (nm), and embedding a light shielding element in the formed groove.
According to a fourth aspect of the present invention, a method of manufacturing a semiconductor device is provided. The method comprises patterning the resist film by means of the method of forming a pattern as mentioned the above first aspect and processing a film to be processed using the resist pattern formed by the patterning as a mask.
In the aspect of the present invention, a film thickness of a light shielding element pattern is made larger, and a resist film thickness is made smaller. Thus, processing of a fine pattern can be carried out without transcribing a spatial image of a Fraunhofer diffraction area into a resist film at the exposure. In the case of a reduced projection ratio of 1/m, a wavelength λ (nm) of exposing light, a minimum opening dimension D (nm) of a light shielding element pattern, a thickness t0 (nm) of the light shielding element pattern and a resist film thickness tr (nm), a fine pattern can be formed by setting m*tr≦t0+5*D*D/λ.
By making the thickness of the light shielding element pattern of the reticle mask lager, an effect to improve resolution of the resist pattern is achieved. Further, since high resolution is kept, an effect to make a depth of focus (DOF) lager is achieved. Moreover, when the light shielding element has a laminated structure, stress on the light shielding element can be reduced, whereby an effect to heighten a processing yield of the mask is achieved. In addition, an error caused by distortion due to stress at the pattern formation can be made smaller, whereby an effect to heighten pattern accuracy is achieved. Furthermore, by adopting a damascene structure for formation of the light shielding element, an effect that a light shielding element pattern having a high aspect ratio can be formed is achieved. A method of processing a film to be processed after transcribing a thin resist pattern into another layer has an effect that a relatively thick member can be processed with a high accuracy thin film resist pattern. Thus, a reticle mask suitable for fine processing and a pattern forming method of a semiconductor device can be obtained.
The present invention will be described with reference to
The diffraction of exposing light relating to the present invention will be described with reference to
At the bottom surface of the light shielding element pattern 4 (Z=0), amplitude intensity of light becomes rectangular-shaped distribution as shown at the upper right of
Now, if the distance Z is 10*D*D/λ that is one digit larger than D*D/λ, it is said the area far from the light shielding element (D*D/λ<<Z). Here, with respect to the distance Z, consider the distance between the D*D/λ and the 10*D*D/λ. In the case where a paraxial approximation equation is discussed in view of whether or not a secondary term thereof can be omitted when a wave equation in which a light intensity distribution function is met is to be solved, it is to be said that the secondary term can be omitted so long as the Z is larger than the 10*D*D/λ. At the area in which the distance Z is smaller than the D*D/λ, it is necessary to leave the secondary term without being omitted. Thus, on the basis of the effect that an area at which diffraction occurs but deformation is small is admitted, in the present invention, Z=5*D*D/λ is considered to be a “near side boundary” at which inadmissible pattern deformation occurs. Moreover, more preferable distance Z is less than D*D/λ.
In the present invention, a thickness of a light shielding element of an exposure reticle mask is made larger, and a spatial image in a Fresnel diffraction area of light passing through an opening portion in the light shielding element is projected and exposed in the resist film formed on a surface of a semiconductor substrate. The spatial image at the distance Z more than about 5 times as far as the D*D*/λ at which the projection light is subjected to Fraunhofer diffraction is not to be projected in the resist film. A measure of the projected area is set to an area in which the thickness t0 of the light shielding element and a value of about 5 times as much as the D*D*/λ are added. It is further preferable to be an area in which the thickness t0 of the light shielding element and the D*D*/λ are added.
More specifically, the measure of the thickness t0 of the light shielding element is set so that a value m*tr obtained by multiplying a resist film thickness (tr) by a reciprocal number of a reduced projection ratio (1/m) is not greater than a value obtained by adding the thickness t0 of the light shielding element to the 5*D*D/λ. It is more preferable to be set so that the value m*tr is not greater than a value obtained by adding the thickness t0 of the light shielding element to the D*D/λ. Now, in the case where an application thickness of the resist film is 0.2 μm, a reduced projection ratio is 1/4, the wavelength λ of the incident light 9 is set to 248 nm, and the minimum opening dimension D of the light shielding element pattern 4 is set to 80 nm, then the thickness t0 of the light shielding element can be defined as follows.
m*tr≦t0+5*D*D/λ
4*0.2 μm≦t0+5*80 nm*80 nm/248 nm
671 nm≦t0
It is more preferable that the thickness t0 of the light shielding element is defined as follows.
m*tr≦t0+D*D/λ
4*0.2 μm≦t0+80 nm*80 nm/248 nm
774 nm≦t0
Further, in the case where the application thickness of the resist film is set to 0.1 μm, the thickness t0 of the light shielding element can be defined as follows.
4*0.1 μm≦t0+5*80 nm*80 nm/248 nm
271 nm≦t0
It is more preferable that the thickness t0 of the light shielding element is defined as follows.
4*0.1 μm≦t0+80 nm*80 nm/248 nm
374 nm≦t0
In addition, although the upper limit of the value of (t0+5*D*D/λ) depends to the respective values of the reduced projection ratio 1 μm, the wavelength λ, the thickness tr, and the minimum opening dimension D, it is desirable not greater than 1.0 μm.
Thus, an appropriate thickness of the light shielding element can be determined on the basis of the application thickness of the resist film, the reduced projection ratio, the wavelength of the incident light, and the minimum opening dimension of the light shielding element pattern. By carrying out reduced projection exposure using the reticle mask having the light shielding element pattern with the necessary thickness determined in this manner, the spatial image passing through the opening portion of the light shielding element and deformed due to the Fraunhofer diffraction can be prevented from being formed in the resist film. Namely, as shown in
In the present invention, the appropriate thickness of the light shielding element is determined on the basis of the application thickness of the resist film, the reduced projection ratio, the wavelength of the incident light, and the minimum opening dimension of the light shielding element pattern. Compared with the related art, by making the application thickness of the resist film smaller and making the thickness of the light shielding element larger, Fraunhofer diffraction is prevent from occurring. As a result, a reticle mask capable of projecting a reticle pattern with a fine dimension of a submicron region in a resist film and a pattern forming method for a semiconductor device are provided.
A first embodiment of the present invention will be described with reference to
Although an illustration is omitted, a reticle mask and a semiconductor substrate are first prepared to be mounted on a stepper. In the reticle mask, a light shielding element pattern 4 (4′) is patterned on a reticle substrate 2. In the semiconductor substrate, a thin film to become a film to be processed is formed, and a resist film 8 (8′) having a predetermined thickness is formed on the film to be processed.
In
On the other hand, in
In
Referring to
On the other hand, in the case where the thickness of the light shielding element pattern is large as shown in
In the following Table 1, distance setup condition dependence of the light shielding element thickness t0 is shown. A distance setup condition (1) is that the space 10 to be projected is not greater than the thickness t0 of the light shielding element pattern 4. A distance setup condition (2) is that the space 10 to be projected is not greater than the sum of the thickness to of the light shielding element pattern 4 and the D*D/λ. A distance setup condition (3) is that the space 10 to be projected is not greater than the sum of the thickness t0 of the light shielding element pattern 4 and the 5*D*D/λ. As a comparative example, values in the general related art are shown in a right column. In the related art, it can be seen that a setup distance is not met. Further, when the setup distance is spread up to t0+5*D*D/λ as the condition (3), it can be seen that an aspect ratio of the light shielding element is somewhat relieved.
Table 2 shows minimum opening dimension dependence in a distance setup condition (2), and shows the results in the case where the minimum opening dimension D in the distance setup condition (2) is changed into 90 nm, 70 mm, and 50 nm. As the opening dimension D becomes smaller due to a change in the D*D/λ, an aspect ratio (A ratio) becomes lager rapidly.
Table 3 shows resist film thickness dependence in a distance setup condition (2), and shows the result in the case where the resist film thickness tr in the distance setup condition (2) is changed into 150, 100, and 50 nm. It can be seen that as a resist film thickness is made smaller, an aspect ratio (A ratio) of the light shielding element is relieved rapidly. In the case where a resist film is thin, processing may become difficult when a monolayer resist pattern is masked thereon in view of a relationship between the film to be processed and a velocity ratio of dry etching (selectivity).
In such a case, a pattern forming method using an intermediate mask layer or multilayer resist (will be described later) allows an accurate pattern processing to be achieved.
In the first embodiment, an optimum thickness of the light shielding element is determined on the basis of the application thickness of the resist film, the reduced projection ratio, the wavelength of the incident light, and the minimum opening dimension of the light shielding element pattern. By making the application thickness of the resist film thinner and making the thickness of the light shielding element thicker compared with the related art, a spatial image of the area in which Fraunhofer diffraction does not occur is projected in the resist film. Thus, a reticle pattern with a fine dimension of a submicron region can be projected in the resist film suitably. In the case of the reduced projection ratio of 1/m, the wavelength λ of the incident light, the minimum opening dimension D of the light shielding element pattern, the thickness t0 of the light shielding element pattern and the resist film thickness tr, it is set to m*tr≦t0+5*D*D/λ. By setting it in this manner, a pattern forming method of a semiconductor device by which the reticle pattern with a fine dimension of a submicron region can be projected in the resist film suitably can be obtained.
A second embodiment of the present invention will be described with reference to
In an exposure reticle mask, a light shielding element pattern 4 is formed on a reticle substrate 2. In the second embodiment, “m” denotes a reciprocal number of a reduced projection ratio, “tr” denotes a thickness of a resist film, “t0” denotes a thickness of a light shielding element pattern, “D” denotes a minimum opening dimension of the light shielding element pattern, and “λ” denotes a wavelength of incident light. A measure of a thickness t0 of the light shielding element pattern 4 is set so as to meet the following equation (condition 3).
m*tr≦t0+5*D*D/λ
It is more preferable that it is set so as to meet the following equation (condition 2).
m*tr≦t0+D*D/λ
It is further more preferable that it is set so as to meet the following equation (condition 1).
m*tr≦t0
In order to meet the above conditions, a ratio (an aspect ratio) of the thickness to a bottom portion dimension of light shielding element becomes larger as shown in Table 1. Even in the case where the condition 3 in which the aspect ratio becomes smaller is applied, the aspect ratio of the light shielding element pattern becomes 4.9, and an advanced technology is required for processing of the reticle mask. As means for relieving the aspect ratio, a scaling reticle mask can be utilized.
In the scaling reticle mask shown in
In the present invention, either a normal reticle mask in which reduced projection ratios in the X and Y directions are the same as each other or a scaling reticle mask in which reduced projection ratios in the X and Y directions are different from each other can be used. In the case where a scaling reticle mask is used, an aspect ratio can be made smaller. Thus, an advantage that workability thereof can be improved and it is thus easy to manufacture it can be achieved. By using these reticle masks, a pattern forming method of a semiconductor device by which a fine dimension pattern of a submicron region can be projected in the resist film suitably can be obtained.
A third embodiment of the present invention will be described with reference to
The light shielding element of the reticle mask can be constructed from a single member as explained with reference to
The light shielding element pattern of
The light shielding element pattern of
Since the aspect ratio of the light shielding element pattern is large in this manner, the light shielding element pattern has a damascene structure in which the light shielding element pattern is embedded in the reticle substrate. In the case of the damascene structure, a depth of the groove to be embedded is set so as to be the thickness t0 that meets the above conditional equations. By setting the depth of the groove to be t0, a height in a vertical direction perpendicular to a surface of the reticle substrate becomes to, thereby preventing diffraction of the incident light. Here, a structure in which a light shielding element pattern is formed in a reticle substrate surface is called a coplanar structure. In the case of the coplanar structure, the thickness of the light shielding element pattern is set to the t0. In the case of the damascene structure, the depth of the groove in the light shielding element is set to the t0. Both the thickness of the light shielding element in the coplanar structure and the depth of the groove in the damascene structure achieve the same function to prevent incident light from transmitting. Therefore, the thickness of the light shielding element and the depth of the groove can be simplified to be simply defined as the thickness of the light shielding element and the height of the light shielding element pattern, respectively. Light shielding elements with high aspect ratio can be formed using a multi-layered structure and/or the damascene structure. Therefore, there is an effect to improve the resolution and the accuracy in patterning.
In an example of
However, in the case where there is no space on the reticle substrate 2 to arrange the auxiliary light shielding element pattern 15 that can be resolved, an auxiliary light shielding element pattern 15′ that is not resolved is arranged as shown in
Further, the auxiliary light shielding element pattern 15′ that is not resolved may be formed so as not to have a damascene structure but a coplanar structure in which it protrudes upward on the reticle substrate 2 as shown in
Alternatively, as shown in
In the present invention, by making the thickness of the light shielding element pattern of the reticle mask larger, the aspect ratio thereof becomes larger. Thus, a monolayer or a plurality of light shielding layers may be laminated as the light shielding element pattern. Further, a groove is provided in the reticle substrate, whereby it may be a damascene structure in which the light shielding layer is embedded in the groove. Moreover, an auxiliary light shielding element pattern for correction may be provided. Furthermore, it may be a Levenson type phase shift mask or a halftone type phase shift mask. By using these reticle masks provided with the light shielding element pattern, a pattern forming method of a semiconductor device by which the reticle pattern with a fine dimension of a submicron region can be projected in the resist film suitably can be obtained.
A fourth embodiment of the present invention will be described with reference to
In
The intermediate film 20 is a member having a property that it can be removed from the reticle substrate 2 with selectivity. By using such an intermediate film 20, even though a scratch occurs in the CMP, this influence can be removed. When the intermediate film 20 is removed after the CMP, as shown in
When a portion of the light shielding element 3 other than the groove 19 is removed by means of dry etching, a film thickness of the intermediate film 20 is over etched to form a light shielding element pattern 4 (
The film thickness of the light shielding element pattern of the reticle mask in the present invention is larger, and the aspect ratio is larger. Such a reticle mask can be made using the various manufacturing methods described above. By using the reticle mask made using these manufacturing methods, a pattern forming method of a semiconductor device by which the reticle pattern with a fine dimension of a submicron region can be projected in the resist film suitably can be obtained. Light shielding elements with high aspect ratio can be formed in the damascene structure without a collapse. Therefore, a fabrication yield of reticle mask is improved, and there is an effect of decreasing the manufacturing cost, too.
A fifth embodiment of the present invention will be described with reference to
A semiconductor substrate on which a reticle mask, a film to be processed and a resist film are formed is prepared to be placed in an exposure apparatus (a stepper). A three-dimensional spatial image corresponding to the light shielding element pattern of the reticle mask is formed in the resist film, whereby a resist pattern is formed. Patterning is made by subjecting the film 7 to be processed to etching using this resist pattern. In this case, the stepper may be a scan-and-repeat type one or a step-and-repeat type one. However, the scan-and-repeat type stepper is suitable when the scaling reticle mask is used. Further, a wavelength of a stepper light source is arbitrary. Moreover, a normal illumination method, a deformation illumination method or an oblique light illumination method may be used as an illumination method.
A patterning method using a resist monolayer will be described with reference to
A patterning method using a resist film and an intermediate mask layer will be described with reference to
One in which the etching selection ratio to the film 7 to be processed can be ensured is selected as the intermediate mask layer 22. For example, in the case where the film 7 to be processed is a silicon film, a silicon oxide film is suitable for the intermediate mask layer 22. In the case where the film 7 to be processed is a silicon oxide film, a polycrystalline silicon film is suitable for the intermediate mask layer 22. In the case where the etching selection ratio between the resist film 8 and the film 7 to be processed cannot be ensured in this manner, a light shielding element pattern is transcribed on the resist film 8, and the intermediate mask layer 22 is subjected to etching. Then, the film 7 to be processed can be subjected to etching using the intermediate mask layer 22 as a mask.
The film thickness of the resist film 8 is determined on the basis of an etching rate ratio (selection ratio) to the film 7 to be processed, and a sharp image corresponding to the light shielding element of the reticle mask is formed in this resist film 8 as a resist pattern. The film 7 to be processed is processed by means of etching using the resist pattern as a mask. Further, in the case where the thickness of the resist film 8 cannot be set to be thicker against the film 7 to be processed, a suitable intermediate mask layer 22 is disposed between the resist film 8 and the film 7 to be processed. After the resist pattern is projected on the intermediate mask layer 22, the film 7 to be processed is processed using the pattern of the intermediate mask layer 22. By causing the intermediate mask layer 22 to intervene in this manner, an adequate relationship between the thickness of the light shielding element pattern and the thickness of the resist film 8 is kept. Thus, a pattern having good resolution can be obtained.
A patterning method using a multilayer resist will be described with reference to
A method of planarizing a surface of a semiconductor substrate and carrying out patterning using a resist and an intermediate mask layer will be described with reference to
As shown in
In the method of manufacturing the semiconductor device according to the fifth embodiment, the film thickness of the light shielding element pattern is made larger, and the resist film thickness is made smaller. Thus, a method of manufacturing a semiconductor device by which processing of a fine pattern can be carried out can be obtained without transcribing a spatial image in a Fraunhofer diffraction area at the exposure into a resist film. In the method of manufacturing the semiconductor device, in the case where the resist film is thinner and an etching selection ratio cannot be ensured, it is possible to ensure the etching selection ratio by adopting the intermediate mask layer, the multilayer resist and the CMP. Thus, a method of manufacturing a semiconductor device by which a pattern with a fine dimension of a submicron region can be processed can be obtained.
In the present invention, the film thickness of the light shielding element pattern is made larger, and the resist film thickness is made smaller. Thus, the processing of a fine pattern can be carried out without transcribing the spatial image in the Fraunhofer diffraction area at the exposure to the resist. A reticle mask in which reduced projection ratios in the X and Y directions are the same magnification or a scaling reticle mask can be used as a reticle mask. The light shielding element pattern may have a damascene structure, or an auxiliary pattern may be combined therewith. The present invention can also be applied to a Levenson type phase mask and a halftone type phase mask.
In the method of manufacturing the semiconductor device according to the present invention, since the resist film is thin, the intermediate mask layer, the multilayer resist and the CMP may be adopted in the case where the etching selection ratio cannot be ensured. Thus, it is possible to ensure the etching selection ratio.
As described above, according to the present invention, a reticle mask suitable for fine processing and a pattern forming method of a semiconductor device can be obtained.
As explained above, although the present invention has specifically been described in conjunction with the plurality of embodiments thereof, the present invention is not limited to the embodiments described above, but various modifications may be applied to the present invention without departing from the scope and spirit of the present invention. Needless to say, such variations are to be included within the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-011461 | Jan 2007 | JP | national |
