Patent Application
20050230725
The present invention is directed, in general, to a capacitor and, more specifically, to a ferroelectric capacitor having an oxide electrode template, a method of manufacture therefor, and an integrated circuit including the same.
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its only supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture affects the read and write access times of a FeRAM.
Currently, high temperatures (e.g., temperatures in excess of 550° C.) are required for the manufacture of the ferroelectric material of the FeRAM. These high temperatures are required to provide sufficient energy to adequately crystallize the ferroelectric material, especially when the ferroelectric material is formed on traditional lower metal electrodes having different lattice structures. As the desired crystallinity provides the requisite ferroelectric properties, high polarization and beneficial non-volativity required in todays FeRAM devices, it is quite important to achieve this desired crystallinity.
Unfortunately, the high temperatures required to adequately crystallize the ferroelectric material have deleterious effects on next generation devices. Specifically, the high temperatures required to adequately crystallize the ferroelectric material negatively affect the nickel silicides used in the next generation devices. Nevertheless, the use of nickel silicide is important to the acceptance of these next generation devices. Thus, there is a tradeoff between continuing to use cobalt silicide and keeping the temperatures high, and using nickel silicide and being required to substantially reduce the temperatures.
Accordingly, what is needed in the art is a ferroelectric capacitor, and method of manufacture therefore, that achieves the benefits of the high temperature ferroelectric material formation, as well as the use of nickel silicides, without experiencing the drawbacks associated with each.
To address the above-discussed deficiencies of the prior art, the present invention provides a ferroelectric capacitor, a method for manufacture therefor, and a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor, among other elements, may include a first electrode layer located over a substrate, wherein the first electrode layer includes iridium, and an oxide electrode template located over the first electrode layer. The ferroelectric capacitor may further include a ferroelectric dielectric layer located over the oxide electrode template, and a second electrode layer located over the ferroelectric dielectric layer.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.
The invention is best understood from the following detailed description when read with the accompanying FIGURES. It is emphasized that in accordance with the standard practice in the semiconductor industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Referring initially to
The transistor 120 illustrated in
Located over the transistor 120 is a dielectric layer 130. The dielectric layer 130 may be any insulative material known for use in a semiconductor device, however, in the particular embodiment illustrated in
Advantageously located over the transistor 120 and contacting the interconnect 140 is a ferroelectric capacitor 150. The ferroelectric capacitor 150 in the embodiment of
The first oxide electrode template 164, which is unique to the present invention, advantageously comprises a material having a substantially similar crystal structure as the ferroelectric dielectric layer 165 located thereover. The term substantially similar crystal structure, as used throughout this document, means the matching of the oxygen octahedron in the crystal structure of the ferroelectric material and the proposed perovskite or distorted perovskite electrode materials. The cations such as Pb and (Ti or Zr) in the case of PZT ferroelectric material are simply to be replaced by Sr and Ir for example in the case of SrIrO3 respectively. One can imagine building blocks of oxygen octahedral and then after a certain thickness instead of inserting Sr and Ir ions in the open spaces, one starts inserting Pb and (Zr or Ti) ions respectively. Contrast this to a situation where one has to crystallize the oxygen octahedron on a metal surface such as Pt or Ir. In this case, the oxygen octahedron will need a lot more energy and therefore temperature to form due to lack of a preferred chemical ambient, i.e., oxygen. The first oxide electrode template 164 may have, among others, a thickness that ranges from about 20 nm to about 100 nm. Additionally, the first oxide electrode template 164 may advantageously have a resistivity of less than about 400 micro-ohms/cm.
The first oxide electrode template 164 in an exemplary embodiment comprises a perovskite material or a distorted perovskite material. For instance, the first oxide electrode template 164 may comprise SrIrO3 or SrRuO3 in various different embodiments. Similarly, the first oxide electrode template 164 may comprise BaPbO3, PbIrO3, PbRuO3, BiRuO3, BiIrO3, (La,Sr)CoO3, CaRuO3, BaPbO3, etc., while staying within the scope of the present invention. One of the keys to the first oxide electrode template 164 is that it has a crystalline structure more similar to the crystalline structure of the ferroelectric dielectric layer 165 than the traditional metal electrodes.
As indicated above, located over the first oxide electrode template 164 is a ferroelectric dielectric layer 165. The ferroelectric dielectric layer 165 in an advantageous embodiment comprises a perovskite material, such as lead zirconate titanate (PZT), strontium bismuth tantalate (SBT) or other similar materials. Located over the ferroelectric dielectric layer 165 in the embodiment of
Additionally located over the second electrode 170 may be a second protective layer 175. It should be noted that other layers may or may not comprise the ferroelectric capacitor 150. Similarly, a ferroelectric capacitor 150 manufactured in accordance with the present invention may or may not have all the layers depicted in
Unique to the present invention, the oxide electrode template 164 allows the ferroelectric dielectric layer 165 to be formed using less energy. As mentioned above, the oxide electrode template 164 has a more similar crystalline structure to the ferroelectric dielectric layer 165 than the first electrode layer 162. Accordingly, much less energy is required to crystallize the ferroelectric dielectric layer 165 on the first oxide electrode template 164 than the first electrode layer 162. As less energy is required, the temperature required to form the ferroelectric dielectric layer 165 may be reduced. For instance, it is believed that the temperature used to form the ferroelectric capacitor 150, and more specifically the ferroelectric dielectric layer 165 is reduced to less than about 500° C.
As the industry scales toward smaller feature sizes in next generation devices, smaller thermal budgets are required. This is specifically the case when using nickel silicides in place of cobalt silicides in the transistor 120. Accordingly, the aforementioned reduction in temperature allows the integration of nickel silicides into the FeRAM 100. As those skilled in the art are aware, the high temperatures previously used to form the ferroelectric dielectric layer 165 cause the resistance of nickel silicide layers to substantially increase.
Turning now to
Located over the substrate 210 is a conventional transistor 220. Basically, the transistor 220 includes a gate dielectric 223 (preferably comprised of silicon dioxide, an oxynitride, a silicon nitride, BST, PZT, a silicate, any other high-k material, or any combination or stack thereof), a gate electrode 225 (preferably comprised of polycrystalline silicon doped either p-type or n-type with a silicide formed on top or a metal such as titanium, tungsten, TiN, tantalum, TaN), and side wall insulators (preferably comprised of an oxide, a nitride, an oxynitride, or a combination or stack thereof). In general the generic terms oxide, nitride and oxynitride refer to silicon oxide, silicon nitride and silicon oxy-nitride. The term “oxide” may, in general, include doped oxides as well as boron and/or phosphorous doped silicon oxide. Source/drain regions 228 are preferably implanted using conventional dopants and processing conditions. Lightly doped drain extensions as well as pocket implants may also be utilized. In addition, the source/drain regions 228 may be silicided (preferably with titanium, cobalt, nickel, tungsten or other conventional silicide material).
A dielectric layer 230 is formed over the entire substrate 210 and over the transistor 220. The dielectric layer 230 is, preferably, comprised of an oxide, FSG, PSG, BPSG, PETEOS, HDP oxide, a silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-oxy-nitride, a low dielectric constant material (preferably SiLK, porous SiLK, Teflon, low-K polymer (possibly porous), aerogel, xerogel, BLACK DIAMOND, HSQ, or any other porous glass material), or a combination or stack thereof. Other known materials could, nonetheless, be used.
Located within the dielectric layer 230 is an interconnect 240. To form the interconnect 240 the dielectric layer 230 is patterned and etched so as to form an opening for contact to the substrate 210. This opening is filled with one or more conductive materials, such as a conductive plug 248 (preferably comprised of a metal such as tungsten, molybdenum, titanium, titanium nitride, tantalum nitride, metal silicide such as Ti, Ni or Co, copper or doped polysilicon). A barrier layer 243 may or may not be formed between the conductive plug 248 and dielectric layer 230. While the barrier layer 243 may comprise a multitude of different materials, the barrier layer 243 of
optionally located over the dielectric layer 230 is a first protective layer 250. The first protective layer 250 may or may not be formed depending on whether the interconnect 240 needs to be protected during subsequent processing of the capacitor dielectric. If formed, the first protective layer 250 is, preferably, comprised of TiAlN or other possible barriers (some of which have a slow oxidation rate compared to TiN) which include: TiAl, TaSiN, TiSiN, TiN, TaN, HfN, ZrN, HfAlN, CrN, TaAlN, CrAlN, or any other conductive material. The thickness of this layer is, preferably, on the order of 60 nm, however, it may range from about 50 nm to about 100 nm, or outside that range, without departing from the scope of the present invention. In the future, scaling the via size will allow scaling of the first protective layer 250 as well.
The preferred deposition technique for the first protective layer 250 is reactive sputter deposition using Ar+N2 or Ar+NH3. It should be noted that Ar is the standard inert gas used for sputter deposition or physical etching based on cost and performance. It is possible to use other inert gases instead of Ar for these applications throughout the process described in this document. Other deposition techniques that might be used include chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD). CVD of nitrides actually results in carbo-oxy-nitrides, especially when metalorganic precursors are used. For the preferred tungsten contact it is desirable to deposit a bilayer diffusion barrier. First, CVD TiN (40 nm is preferred) is deposited followed by PVD TiAlN (30 nm preferred). Even more preferred would be CVD or PECVD deposition of TiAlN (about 60 nm). The preferred proportion of aluminum in TiAlN is around 30-60% Al and 40-50% is more preferred in order to have improved oxidation resistance. A better first protective layer 250 (such as the one of an embodiment of the instant invention) will, in general, allow the oxygen stable bottom electrode material to be thinner or a higher process temperature to be used.
Turning now to
The first electrode 310 in the embodiment of
Uniquely formed over the first electrode layer 313 is the first oxide electrode template 318. The first oxide electrode template 318, in contrast to the first electrode layer 313, comprises a perovskite material. For instance, the first oxide electrode template 318 may comprise SrIrO3 and SrRuO3, as well as BaPbO3, PbIrO3, PbRuO3, BiRuO3, BiIrO3, (La,Sr)CoO31 CaRuO3, and BaPbO3 while staying within the scope of the present invention. As previously discussed, it is important that the first oxide electrode template 318 comprise a material having a substantially similar crystal structure to the subsequently formed ferroelectric dielectric layer 410 (
The first oxide electrode template 318 may be formed to a thickness ranging from about 20 nm to about 100 nm. Additionally, the first oxide electrode template 318 may be manufactured using a CVD process and having a resistivity of less than about 400 micro-ohms/cm. The preferred deposition technique for the first oxide electrode template 318 is reactive sputter deposition using Ar+O2 or Ar+N2O using a ceramic target of the material or simultaneous deposition from targets of individual components of the material. It should be noted that Ar is the standard inert gas used for sputter deposition or physical etching based on cost and performance. It is possible to use other inert gases instead of Ar for these applications throughout the process described in this document. Other deposition techniques that might be used include chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), Atomic Layer Deposition (ALD), or Metal Organic Chemical Vapor Deposition (MOCVD). The preferred composition would be stoichiometric with respect to the individual components.
Turning now to
PZT is the most preferable choice for the ferroelectric dielectric layer 410 because it has the highest polarization and the lowest processing temperature of the aforementioned materials. In addition, the preferred Zr/Ti composition is around 20/80, respectively, in order to obtain good ferroelectric switching properties (large switched polarization and relatively square-looking hysterisis loops). Alternatively Zr/Ti compositions of approximately 65/35 may be preferred to maximize uniformity in capacitor properties. The donor dopant may improve the reliability of the PZT by helping to control the point defect concentrations.
The preferred deposition technique for the ferroelectric dielectric layer 410 is metal organic chemical vapor deposition (MOCVD). MOCVD is preferred especially for thin films (i.e., films less than 100 nm thick). Thin PZT is extremely advantageous in making integration simpler (less material to etch), cheaper (less material to deposit therefore less precursor) and allows lower voltage operation (lower coercive voltage for roughly the same coercive electric field). The ferroelectric dielectric layer 410 can be deposited in either a single crystalline/poly-crystalline state or it can be deposited in an amorphous phase at low temperatures and then crystallized using a post-deposition anneal. This is commonly done for Bi ferroelectric films. The post deposition crystallization anneal can be performed immediately after deposition or after later process steps such as electrode deposition or post capacitor etch anneal. The preferred MOCVD PZT approach results in a poly-crystalline film completely formed using temperatures of about 500° C. or less, and more preferably between about 400° C. and about 450° C.
Turning now to
Turning now to
The second protective layer 610 may or may not be removed after the etching of the capacitor stack. If the second protective layer 610 is not removed, then it is preferable to form it of a conductive material. However, a non-conductive or semiconductive material may be used, but the interconnection to the second electrode 510 of the capacitor should preferably be formed through this layer so as to make direct connection to the second electrode 510.
Turning now to
The etch process is a dirty process and hence it is likely that the etch tool and the frontside, edge and backside of the wafers will have FeRAM contamination or have etch residues with FeRAM contamination. It is, therefore, often necessary to clean the frontside of the wafer and chemically remove etch residues and possibly remove a thin layer of damaged PZT. This post-capacitor-etch wet-clean may, with some etch conditions and chemistries, be as simple as a deionized water (DI water or DIW) clean (tank soak with or without megasonic followed by a spin rinse dry) or the tank etch might be acid-based in order to improve the clean or remove more damage.
The sidewalls of the completed ferroelectric capacitor 710 are, preferably, fairly steep. A sidewall diffusion barrier is, preferably, formed on the completed ferroelectric capacitor 710 prior to the formation of another interlevel dielectric thereover. The sidewall diffusion barrier is important because it allows for the misalignment of the interconnect without shorting the capacitor, it protects the capacitor from the diffusion of most substances into the capacitor, and it protects the rest of the structures from the out-diffusion of substances from the capacitor. The sidewall diffusion barrier often comprises two layers, but the sidewall diffusion barrier may be comprised of more or fewer layers and stay within the scope of the present invention. Preferably, the first layer is around 30 nm thick and is comprised of AlOx, Ta2O5, AlN, TiO2, ZrO2, HfO2, or any stack or combination thereof; and the second layer is around 30 nm thick and is comprised of silicon nitride, AlN, or any stack or combination thereof. The preferred process for depositing these layers is MOCVD under conditions with minimal free hydrogen (e.g., enough oxygen such that H2O is formed rather than H2). It is also possible to use a plasma enhanced CVD or MOCVD process. Alternatively reactive sputter deposition can be used with either Ar+O2 (for oxides), Ar+N2 (for nitrides) or Ar+O2+N2 (for oxy-nitrides). For the preferred embodiment listed here, the first layer is used as a Pb and H diffusion barrier while the second layer is used as a contact etch stop. Subsequent to the formation of the first and second diffusion barrier layers the manufacturing process would continue resulting in a device similar to the FeRAM 100 illustrated in
Referring finally to
Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
