Patent Application
20070158700
The present invention relates to a field effect transistor and a method for producing the same.
[Structure]
First, the feature of a general FinFET will be described. A field effect transistor called a FinFET characterized in that for the purpose of improving the performance of a field effect transistor, a gate electrode is provided on opposite side surfaces of a projecting semiconductor region and channels are formed on opposite side surfaces of the semiconductor region has been proposed. A typical structure of the transistor is shown in
In the FinFET, a structure in which a channel is also formed on the upper part of the semiconductor layer (FIGS. 32(a) and 32(b)) is called a tri gate structure. A transistor having the tri gate structure is characterized in that the thickness of the insulating film on the upper part of the semiconductor layer and the thickness of the insulating film on the semiconductor side surface are comparable. A structure in which no channel is formed on the upper part of the semiconductor layer (FIGS. 33(a) and 33(b)) is called a double gate structure. The transistor having the double gate structure is characterized in that a cap insulating film 8 consisting of an insulating film thicker than the insulating film (gate insulating film 4) on the semiconductor side surface is provided on the upper part of the semiconductor layer. Usually, the cap insulating film 8 is formed in a step different from a step of forming the gate insulating film 4. In the conventional configuration, the structure in the section B-B′ and the structure in the section C-C′ in
The technique disclosed in Japanese Patent Laid-Open No. 6-302817 (hereinafter referred to as Patent Document 1) will now be described with reference to
In the structure in Patent Document 1, a source region 42 and a drain region 43 are formed on the semiconductor layer 3 projecting from a substrate and the channel forming region 7 is formed on a region sandwiched between the source region 42 and the drain region 43 in an n-channel FinFET formed on a p type bulk silicon substrate. A p+ conductive layer 20 is formed on an upper end portion of the channel forming region 7. Therefore, the upper end portion of the channel forming region 7 does not operate as a channel, and can reduce an influence of a gate voltage above the region. As a result, a parasitic transistor having a low threshold voltage is prevented from being formed on the upper end portion of the semiconductor layer. In Patent Document 1, the “upper end portion of the semiconductor layer” refers to a region extending from the upper end surface (“upper end surface” will be described as “upper end” in embodiments of the present invention below) of the semiconductor layer to a certain depth, and is used as a term indicating a portion in which the p+ conductive layer 20 is formed.
[Problems of Conventional Technique]
Problems in the conventional FinFET will be described taking an n-channel transistor as an example. The n-channel transistor will be described here, but in a p-channel transistor, the same holds true if the polarity is reversed (for example, an increase in electric potential in the n-channel transistor is reversely read as a decrease in electric potential in the p-channel transistor, and a decrease in threshold voltage in the n-channel transistor is reversely read as an increase in threshold voltage in the p-channel transistor).
(First Problem)
The results of simulating an electric potential distribution on the upper end portion of the semiconductor layer 3 in the section A-A′ in
In any of the double gate structure and the tri gate structure, the isopotential line is curved at an upper corner portion of the semiconductor layer.
This indicates that in the upper corner portion, electric fields traveling toward impurity ions from the gate electrode are concentrated, and therefore the electric potential increases compared to other portions of the semiconductor layer. When the electric potential of the upper corner portion increases, a parasitic transistor having a low threshold voltage is formed in the upper corner portion. Formation of the parasitic transistor causes a problem of increasing a subthreshold current and increasing an off current as in
Thus, a technique for inhibiting an increase in electric potential in the semiconductor layer upper corner portion and reducing an influence of the parasitic transistor is desired.
(Second Problem)
In the transistor having the tri gate structure, a channel is formed on each of a semiconductor layer upper surface 23, a semiconductor layer upper side surface 24 and a semiconductor layer side surface 25 (see
In the transistor having the double gate structure, a channel is formed on each of the semiconductor layer upper side surface 24 and the semiconductor layer side surface 25 (see
Thus, a technique for inhibiting the parasitic transistor on the upper corner portion of the semiconductor layer and inhibiting a reduction in drain current associated with the inhibition of the parasitic transistor.
It is an object of the present invention to provide a FinFET in which formation of a parasitic transistor in an upper corner portion of a semiconductor layer projecting from the plane of a base of the FinFET is inhibited while sufficiently securing a drain current to improve element characteristics.
According to the present invention, field effect transistors described in the following items and methods for producing the same can be provided.
forming a gate electrode via an insulating film so as to straddle the projecting semiconductor layer; and
In the present invention, the “plane of a base” or “plane of a substrate” means any plane parallel to a substrate (horizontal).
The substrate refers to a structure supporting a projecting semiconductor layer, and is normally a semiconductor substrate such as an SOI substrate or a bulk semiconductor substrate. In the SOI substrate after the entire semiconductor layer is processed into a projective form, a structure consisting of a buried insulating film and a support substrate forms the substrate.
The direction parallel to the substrate refers to a direction parallel to a direction along which the substrate extends. In embodiments described in the specification, the direction is consistent with a direction parallel to the surface of a semiconductor layer before the step of forming a projecting semiconductor layer, or a direction parallel to the surface of a bulk semiconductor substrate before the step of forming a projecting semiconductor layer. The direction is normally a direction parallel to a wafer surface, since a FinFET is normally formed on a semiconductor wafer such as an SOI substrate or a bulk semiconductor substrate.
The longitudinal direction of channel is a direction in which two source/drain regions are linked.
According to the present invention, in a field effect transistor in which a channel is formed on the side surface of a semiconductor layer projecting on a substrate, a parasitic transistor formed at the upper corner of the semiconductor layer can be inhibited.
According to the present invention, the parasitic transistor formed at the upper corner of the semiconductor layer can be inhibited, and at the same time, by forming a channel on the side surface of the upper part of the semiconductor layer, and further on the upper surface of the semiconductor layer for the tri gate structure, the upper part of the semiconductor layer can be used as a channel, the area of region on which the channel is formed increases, the amount of current passing into a drain increases, and therefore the amount of on-current increases.
According to the present invention, the parasitic transistor formed at the upper corner of the semiconductor layer can be inhibited, and at the same time, the semiconductor layer can be fully depleted.
According to the present invention, the impurity concentration is increased only in a part of the upper corner required for inhibition of the parasitic transistor, at the upper end of the semiconductor layer, whereby formation of a channel on the upper end portion of the semiconductor layer excepting a region having a high impurity concentration is facilitated, and the channel resistance is reduced, so that the amount of current passing into a drain increases, and therefore the amount of on-current increases.
According to the present invention, regions having an appropriately high impurity concentration are provided at both of the upper and the lower end of the semiconductor layer, and therefore both of the parasitic transistor formed at the upper corner of the semiconductor layer and the parasitic transistor formed at the lower corner of the semiconductor layer can be inhibited.
According to the present invention, a method for producing a field effect transistor having the effects described above can be provided.
FIGS. 2(a), 2(b) and 2(c) are sectional and plan views for explaining the first embodiment;
FIGS. 3(a), 3(b) and 3(c) are sectional and plan views for explaining the first embodiment;
FIGS. 4(a) and 4(b) are sectional views for explaining the first embodiment;
FIGS. 6(a), 6(b) and 6(c) are sectional and plan views for explaining the first embodiment;
FIGS. 7(a), 7(b) and 7(c) are sectional and plan views for explaining the first embodiment;
FIGS. 8(a), 8(b) and 8(c) are sectional and plan views for explaining the first embodiment;
FIGS. 12(a) and 12(b) are plan views for explaining the second embodiment;
FIGS. 14(a), 14(b) and 14(c) are sectional and plan views for explaining the second embodiment;
FIGS. 15(a), 15(b) and 15(c) are sectional and plan views for explaining the second embodiment;
FIGS. 16(a), 16(b) and 16(c) are sectional and plan views for explaining the second embodiment;
FIGS. 17(a) and 17(b) are sectional views for explaining the second embodiment;
FIGS. 18(a), 18(b) and 18(c) are sectional and plan views for explaining the second embodiment;
FIGS. 19(a) and 19(b) are sectional views for explaining the second embodiment;
FIGS. 20(a), 20(b) and 20(c) are sectional and plan views for explaining the second embodiment;
FIGS. 21(a) and 21(b) are sectional views for explaining the second embodiment;
FIGS. 22(a), 22(b) and 22(c) are sectional views for explaining the third embodiment;
FIGS. 24(a), 24(b) and 24(c) are sectional and plan views for explaining the third embodiment;
FIGS. 25(a), 25(b) and 25(c) are sectional and plan views for explaining the third embodiment;
FIGS. 26(a) and 26(b) are sectional views for explaining the third embodiment;
FIGS. 28(a) and 28(b) are plan views for explaining the third embodiment;
FIGS. 29(a) and 29(b) are plan views for explaining the third embodiment;
FIGS. 30(a) and 30(b) are plan views for explaining the third embodiment;
FIGS. 32(a) and 32(b) are sectional views for explaining the conventional technique;
FIGS. 33(a) and 33(b) are sectional views for explaining the conventional technique;
FIGS. 34(a) and 34(b) are views for explaining a problem in the conventional technique;
FIGS. 38(a) and 38(b) are sectional views for explaining the conventional technique;
FIGS. 41(a), 41(b) and 41(c) are sectional views for explaining the fourth embodiment;
FIGS. 42(a), 42(b) and 42(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 43(a), 43(b) and 43(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 44(a) and 44(b) are sectional views for explaining the fourth embodiment;
FIGS. 45(a), 45(b) and 45(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 46(a), 46(b) and 46(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 47(a), 47(b) and 47(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 48(a), 48(b) and 48(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 49(a), 49(b) and 49(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 50(a), 50(b) and 50(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 51(a) and 51(b) are sectional views for explaining the fourth embodiment;
FIGS. 52(a), 52(b) and 52(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 53(a) and 53(b) are sectional views for explaining the fourth embodiment;
FIGS. 54(a), 54(b) and 54(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 55(a) and 55(b) are sectional views for explaining the fourth embodiment;
FIGS. 56(a) and 56(b) are sectional views for explaining the fourth embodiment;
FIGS. 57(a), 57(b) and 57(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 58(a), 58(b) and 58(c) are sectional and plan views for explaining the fourth embodiment;
FIGS. 59(a) and 59(b) are sectional views for explaining the fourth embodiment;
FIGS. 73(a) and 73(b) are plan views for explaining an embodiment of the present invention.
FIGS. 74(a) and 74(b) are sectional views for explaining the fifth embodiment.
FIGS. 75(a) and 75(b) are sectional views for explaining the fifth embodiment.
FIGS. 76(a) and 76(b) are sectional views for explaining the fifth embodiment.
FIGS. 77(a) and 77(b) are sectional views for explaining the fifth embodiment.
FIGS. 78(a), 78(b) and 78(c) are sectional and plan views for explaining the first embodiment;
FIGS. 79(a) and 79(b) are sectional views for explaining an embodiment of the present invention;
FIGS. 81(a) and 81(b) are plan views for explaining the second embodiment;
FIGS. 82(a) and 82(b) are plan views for explaining the second embodiment; and
FIGS. 83(a) and 83(b) are views for explaining the effect of the invention.
[Structure]
The first embodiment will be described with reference to FIGS. 4(a) and 4(b) and
In this embodiment, a semiconductor layer 3 projecting upward from a substrate is provided, and a gate electrode 5 is provided on the side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned in an appropriate size, and source/drain regions 6 where a first conductivity type impurity is introduced in a high concentration are formed on the semiconductor layer 3 at a position where the semiconductor layer 3 is not covered with the gate electrode 5. A low-concentration second conductivity type impurity is introduced into a channel forming region 7 corresponding to the semiconductor layer covered with the gate electrode 5, and an appropriate voltage is applied to the gate electrode 5, whereby a channel consisting of a first conductivity type carrier is formed. An interconnect 18 is connected to the gate electrode 5 or the source/drain region 6 via a contact 17.
A second conductivity type impurity of which the concentration is higher than the concentration in the semiconductor layer 3 excepting a channel impurity concentration adjusting region 10 is introduced into the channel impurity concentration adjusting region 10 provided over a certain area from the upper end of the semiconductor layer 3 forming the channel forming region 7. However, the concentration of the impurity introduced into this channel impurity concentration adjusting region 10 is lower than the concentration of an impurity introduced into high-concentration regions such as source/drain regions. The impurity concentration in the channel impurity concentration adjusting region is adjusted to be a level of concentration with which an increase in electric potential in an upper corner portion of the semiconductor layer is inhibited and channels are formed on the upper surface and the side surface of the channel impurity concentration adjusting region with application of a gate voltage.
The average value Ntop of the net concentration of the second conductivity type impurity in an area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type is typically in a range from 1.3 times to 4 times as large as the average value N of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop. More typically, the average value Ntop is in a range from 1.5 times to 3 times as large as the average value N of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop.
Alternatively, the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop, which is determined excepting an area of 1 nm from the boundary of the upper part and the side face of the semiconductor layer is in a range of 1.5 times to 3 times as large as the average the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop, which is determined in the same way excepting the area of 1 nm from the boundary of the upper part and the side surface of the semiconductor layer. The reason for excepting the area of 1 nm from the boundary of the upper part and the side surface of the semiconductor layer is that the area of 1 nm representing a typical width of a region where the impurity concentration is extremely steeply changed is excluded in consideration of the fact that the impurity concentration is extremely steeply changed around the boundary of the upper part and the side surface of the semiconductor layer, and a region where the concentration is thus steeply changed is so narrow that its influence on an electric characteristic is insignificant.
The impurity concentration in the channel impurity concentration adjusting region is set to satisfy a relationship between Ntop and N in which an increase in electric potential in the corner portion of the upper part of the semiconductor layer can be reduced as compared to a case where no channel impurity concentration adjusting region is provided (i.e. as compared to a case where the impurity concentration in the channel impurity concentration adjusting region is replaced by the N described above). At this time, the amount of reduction of an increase in electric potential in the corner portion of the upper part of the semiconductor layer is preferably 60 mV or more (reduction of 60 mV corresponds to a condition in which a leak current by a parasitic transistor decreases by an order of magnitude) in at least a part of the upper part of the semiconductor layer.
The present invention typically reduces an increase in electric potential due to electric field concentration by 60 mV or more in at least a part of the upper corner portion of the semiconductor layer, and therefore the present invention is typically applied for improving a characteristic of a transistor in which the electric potential increases by 60 mV or more in at least a part of the upper corner of the semiconductor layer when no channel impurity concentration adjusting region is provided.
FIGS. 83(a) and 83(b) show the results of calculating a relationship between each of the amount of increase in electric potential Vcorner (black circle in the figure) in the upper corner portion and an difference in electric potential Vside (white circle in the figure) of the side surface of the semiconductor layer in a portion below the upper corner portion relative to the central portion of the semiconductor layer and the average value of the second conductivity type impurity concentration in the semiconductor layer 3 for the channel forming region. The calculation is performed for positions corresponding to the sections in
A point pcorner shows a position at which the electric potential is highest (generally a corner portion, but if the corner is rounded, the position is determined from comparison of electric potentials of positions) in the upper corner portion of the semiconductor layer. A point pside shows a position of the side surface of the semiconductor layer in a position in a vertical direction (vertical direction refers to a longitudinal direction in the figure) where electric field concentration does not occur (side surface of the semiconductor layer in a portion below the upper corner portion; a position at which the dependency in the vertical direction of the electric potential is almost zero in the semiconductor side surface, or otherwise a position at which the electric potential is minimum in the side surface of the semiconductor layer). The point pcenter is identical to the point pside in position in the vertical direction, and is at a position of the center in the width direction (direction of Wfin, lateral direction in the figure) of the semiconductor layer. The amount of increase in electric potential Vcorner in the upper corner portion is a value obtained by subtracting the electric potential at the point pside from the electric potential at the point pcorner, and the difference in electric potential Vside of the side surface of the semiconductor layer in the portion below the upper corner portion relative to the central portion of the semiconductor layer is a value obtained by subtracting the electric potential at the point pcenter from the electric potential at the point pside. The calculation is performed provided that the width of the semiconductor layer is 30 nm, the thickness of a gate oxide film is 2 nm and the gate voltage is 0 V. The net concentration of the second conductivity type impurity is made constant in the semiconductor layer. The electric potential at the point pside is kept at a minimum value for the vertical direction of the side surface of the semiconductor layer, but when the electric potential at the point pcenter in the same position in the vertical direction changes, a position in the vertical direction at which the electric potential at the point pcenter is minimum.
The present invention is typically applied for improving a characteristic of a transistor in which Vcorner is 60 mV or more when no channel impurity concentration adjusting region is provided as described above, but from
Since the channel impurity concentration adjusting region is typically provided less deeply than the upper corner portion where the electric potential increases, and the influence of provision of the channel impurity concentration adjusting region on Vside as a difference in electric potential in the horizontal direction in a region below the upper corner portion, the transistor of this embodiment is typically characterized in that Vside is 120 mV or more. However, pside in the transistor of this embodiment refers to a position at which the dependency in the vertical direction of the electric potential on the semiconductor side surface is almost zero on the side surface of the semiconductor layer situated in the lower part of the channel impurity concentration adjusting region (the channel forming region excepting the channel impurity concentration adjusting region), or otherwise a position at which the electric potential is minimum on the side surface of a region of the channel forming region situated in the lower part of the channel impurity concentration adjusting region. When electric potentials at pside, pcorner and pcenter change depending on the position in the direction of the gate length for a transistor with a short channel, an electric potential in a section in a position at which the electric potential at pcenter is the lowest is selected. When the electric potential at pcenter has a minimum value over a certain region in the direction of the gate length, an electric potential in a section in a position at which the electric potential at pside is the lowest is selected. When a region in which the electric potential at pcenter and the electric potential at pside each have a minimum value exists over a certain region in the direction of the gate length, an electric potential in a section in a position at which the electric potential at pcorner is the lowest is selected. When a region in which the electric potentials at the three points each have a minimum value exists over a certain region in the direction of the gate length, the electric potential is evaluated in a section in any position in the region. Evaluations of the electric potential and the difference in electric potential are made in a subthreshold region (the gate voltage is normally lower than the threshold voltage by 0.1 to 0.4 V and the gate voltage is typically 0 V) of a linear region (region having a low drain voltage, typically 0.05 V). The discussions concerning pside, pcorner, pcenter, Vcorner and Vside have been described with an n-channel transistor as an example, but in the case of a p-channel transistor, the polarity is reversed.
Since Vside becomes 120 mV or more when the impurity concentration is 7.5×1017 cm−3 or more, the present invention is typically applied for improving the performance of a transistor in which the average value of the impurity concentration in the semiconductor layer is 7.5×1017 cm−3 or more when no channel impurity concentration adjusting region is provided, and therefore in the transistor of this embodiment, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting the channel impurity concentration adjusting region is typically 7.5×1017 cm−3 or more.
If considering that Vcorner and Vside are normally slightly lower in a transistor of a short channel (gate length is typically 0.1 μm or less), the present invention is typically applied for improving the performance of a transistor in which the average value of the impurity concentration in the semiconductor layer is 1.0×1018 cm−3 or more when no channel impurity concentration adjusting region is provided, and therefore in the transistor of this embodiment having a short channel, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting the channel impurity concentration adjusting region is typically 1.0×1018 cm−3 or more.
In this specification, the following terms are used for the following meanings. The “net concentration of the second conductivity type impurity” refers to a value obtained by subtracting the concentration of the first conductivity type impurity (concentration of an activated donor for the n-channel transistor) from the concentration of the second conductivity type impurity (concentration of an activated acceptor ion for the n-channel transistor). The “channel forming region of a second conductivity type” refers to any of two regions: a region of the semiconductor layer 3 which is covered with the gate electrode and is a region of a second conductivity type and a region of the semiconductor layer 3 which is sandwiched between source/drain regions and is a region of a second conductivity type, whose volume is not larger than that of the other. The “region of a second conductivity type” refers to a region in which the concentration of an activated second conductivity type impurity is greater than the concentration of an activated first conductivity type impurity. In a normal FinFET, the end portion of the source/drain region is covered with the gate electrode, and therefore the “region of a second conductivity type in a region covered with the gate electrode” is synonymous with the “region of a second conductivity type in a region sandwiched between source/drain regions”, but if these regions are different, one of these regions which has a smaller volume is determined to be the “channel forming region of a second conductivity type” as described above. The first conductivity type refers to a conductivity type of the source/drain region, and the second conductivity type refers to a conductivity type different from that of the source/drain region.
The depth Htop of the channel impurity concentration adjusting region 10 is normally half of the height Hfin of the semiconductor layer or less (see FIGS. 32(a) and 32(b) and FIGS. 33(a) and 33(b)). However, for a transistor in which the Hfin is very small (typically the Hfin is 40 nm or less), the Htop may be half of the Hfin or more.
The channel impurity concentration adjusting region 10 is preferably provided in a region in which an increase in electric potential of the semiconductor layer occurs due to electric field concentration (referred to as Hcorner; typically a region in which an increase in electric potential by 60 mV or more, which corresponds to an increase by an order of magnitude in a leak current by a parasitic transistor). This will be described with reference to
The size of Hcorner is determined from calculation.
If Htop is too small, an increase in electric potential is inhibited only a quite limited upper part of the semiconductor layer as shown in
For operating the FinFET in a fully depleting manner, the width of Wfin is normally 35 nm or less, and therefore Htop is typically 24.5 nm or less. Htop is preferably 5 nm or more in terms of ease in the production method. Thus, Htop is typically 5 nm to 24.5 nm. In view of a tradeoff between ease in the production method and effect (production becomes easier as Htop increases in terms of production), Htop is preferably in a range from 10 nm to 20 nm, and the most typical value of Htop is 10 nm.
If the impurity concentration in the channel forming region is low, an increase in electric potential in the upper corner is low, and therefore formation of the channel impurity concentration adjusting region 10 is especially effective when the average value of the net concentration of the second conductivity type impurity in the channel forming region is 1×1018 cm−3 or more.
The definition of the depth (Htop) of the channel impurity concentration adjusting region 10 when the impurity distribution smoothly changes will be described with reference to FIGS. 61 to 68. FIGS. 61 to 68 depict an impurity concentration distribution in the longitudinal direction (direction vertical to the substrate) in the semiconductor layer where the position in the depth direction when viewed from the upper end of the semiconductor layer 3 of the FinFET is plotted on the abscissa and the net concentration of the second conductivity type impurity is plotted on the ordinate. In this connection, the net concentration of the second conductivity type impurity on the ordinate refers to the average value of the net concentration of the second conductivity type impurity in a section parallel to the plane of the substrate in the channel forming region of a second conductivity type at each position in the depth direction.
The depth Htop of the channel impurity concentration adjusting region 10 situated in the upper part of the semiconductor layer is a depth from the upper surface of the semiconductor layer 3 at a position below the position of the peak of the impurity concentration (right direction in the figure) and in which the height (Np) of an impurity concentration peak decreases (
If there are a plurality of impurity concentration peaks as shown in
There may be cases where the concentration of the second conductivity type impurity decreases in a quite limited region in the vicinity of the boundary of the lower part of the semiconductor layer, but the impurity concentration in such a region is not included in determination of a standard level of the impurity concentration peak. Specifically, the impurity concentration in a region where the dependency of the net impurity concentration on the position in the depth direction takes on a curve raised upward in the vicinity of the boundary of the lower part (region where the secondary differentiation of the net impurity concentration with the position in the depth direction gives a negative value; it does not mean that the region projects upward) is excluded from determination of the standard level of impurity concentration peak (see
If channel impurity concentration adjusting regions 10 (upper channel impurity concentration adjusting region 19 and lower channel impurity concentration adjusting region 11) are provided on the upper end portion and the lower end portion, respectively, of the semiconductor layer according to the third embodiment described later, the height Htop2 of the lower channel impurity concentration adjusting region 11 is a distance from a position on the plane of the base relative to the semiconductor layer 3 (boundary between the lower end of the semiconductor layer and the buried insulating film if the semiconductor layer is provided on the buried insulating film on the support substrate) for a position above the position of the impurity concentration peak (left direction in the figure) and in which the height of the impurity concentration peak decreases to half (
If the height of the impurity concentration peak situated below the center of the semiconductor layer does not exceed Np/2 when the concentration of the second conductivity type impurity increases in a quite limited region in the vicinity of the boundary of the lower part of the semiconductor layer due to segregation of an impurity or when an impurity is intentionally introduced into the lower part of the semiconductor layer, it is not considered that there is a lower channel impurity concentration adjusting region (see
If there are a plurality of positions at which the impurity concentration is Np/2 or Np2/2, Htop or Htop2 is determined with a position closest to a position at which the impurity concentration decreases to the standard level of the impurity concentration peak (
[Production Method]
A first production method of the first embodiment will be described with reference to
For producing the field effect transistor of the first embodiment, a semiconductor layer 38 of a substrate is patterned to a semiconductor layer 3 projecting from the surface of the substrate, and an impurity is introduced into a region of the upper part of the semiconductor layer 3 by an impurity introduction step such as ion implantation. In this way, a channel impurity concentration adjusting region 10 which has an impurity concentration higher than that of other regions of the semiconductor layer 3 and in which a second conductivity type impurity is introduced is provided in the upper part of the semiconductor layer 3 (FIGS. 2(a), 2(b) and 2(c)). Next, a gate insulating film 4 is formed on the side surface of the semiconductor 3, a gate electrode material is deposited, the gate electrode material is then patterned by RIE (reactive ion etching) or the like to form a gate electrode 5, and a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode 5, whereby source/drain regions 6 are formed (FIGS. 3(a), 3(b) and 3(c)). Thereafter, an interlayer insulating film is deposited to form a contact 17 and an interconnect 18 for the source/drain regions 6 and the gate electrode 5 (FIGS. 4(a) and 4(b) and
A low-concentration second conductivity type impurity is introduced into the semiconductor layer 3 (including a region other than the channel impurity concentration adjusting region 10) by the impurity introduction step carried out at an appropriate time point (e.g. before or after a step of carrying out ion implantation for the channel impurity concentration adjusting region 10, or before forming the semiconductor layer 3 projecting from the surface of the substrate by patterning, or the like).
Here, a typical structure of the first embodiment can be produced by setting the depth and the impurity concentration of the channel impurity concentration adjusting region 10 so as to satisfy the typical structure of the first embodiment (in which the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end of the semiconductor layer 3 to a depth Htop in a channel forming region 7 of a second conductivity type is typically in a range from 1.3 times or more to 4 times or less as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop, and more typically, the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region 7 of a second conductivity type is typically in a range from 1.5 times or more to 3 times or less as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop.
For the first production method of the first embodiment, an example will be described more specifically with reference to FIGS. 1 to 5.
In an SOI substrate (
Next, a gate insulating film 4 is provided on the side surface of the semiconductor layer 3, polysilicon is then deposited, etched by a normal lithography step and RIE step and thereby patterned to form a gate electrode, high-concentration ion implantation is subsequently carried out using the gate electrode as a mask, and a heat treatment is performed to provide source/drain regions 6 on the semiconductor layer 3 at a position in which the semiconductor layer 3 is not covered with the gate electrode, so that the shape in FIGS. 3(a), 3(b) and 3(c) is obtained. The gate insulating film is provided by, for example, thermally oxidizing the semiconductor layer 3. The source/drain regions are formed by introducing an impurity by an impurity introduction step such as vertical ion implantation, slanting ion implantation or plasma doping.
Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. For the insulating film forming the gate side wall 14, an insulating film such as, for example, a SiO2 monolayer film, a Si3N4 monolayer film, a multilayered film composed of SiO2 and Si3N4 is used. The insulating film forming the gate side wall 14 is formed by a film formation technique such as a CVD method. Subsequently, a metal is deposited on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5, and a heat treatment is performed to form a silicide layer 15 on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened, contact holes are then opened to the source/drain regions 6 and the gate electrode 5, a metal is buried to form a contact 17, and an interconnect 18 composed of a metal is connected to the contact 17 to obtain the shape in FIGS. 4(a) and 4(b) and
The First channel ion implantation step, or the second channel ion implantation step for forming the channel impurity concentration adjusting region 10 may be carried out before the step of patterning the semiconductor layer 38 to process the same into an appropriate shape and thereby forming the element region composed of the semiconductor layer 3 projecting from the substrate.
Here, the depth and the impurity concentration of the channel impurity concentration adjusting region 10 are set to satisfy the typical structure of the first embodiment.
A second production method of the first embodiment will be described with reference to FIGS. 6(a), 6(b) and 6(c), FIGS. 7(a), 7(b) and 7(c) and FIGS. 8(a), 8(b) and 8(c).
For producing the field effect transistor of the first embodiment, a semiconductor layer 38 of a substrate is first patterned to form a semiconductor layer 3 projecting from the surface of the substrate (FIGS. 6(a), 6(b) and 6(c)). Next, a gate insulating film 4 is formed on the side surface of the semiconductor layer 3, a gate electrode material is deposited, and an electrode material is patterned by RIE (reactive ion etching) or the like to form a gate electrode 5 straddling the semiconductor layer 3 (FIGS. 7(a), 7(b) and 7(c)). Ion implantation is carried out using the gate electrode as a mask, whereby a channel impurity concentration adjusting region 10 of which the concentration of a second conductivity type impurity is higher than that in other regions of the semiconductor layer 3 is formed on the upper part of the semiconductor layer 3. Then, a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with the gate electrode, and source/drain regions 6 are thereby formed (FIGS. 8(a), 8(b) and 8(c)). Thereafter, an interlayer insulating film is deposited, and a contact 17 and an interconnect 18 are formed for the source/drain regions 6 and the gate electrode 5 by a normal method (The obtained configuration is same as that in FIGS. 4(a) and 4(b) and
A low-concentration second conductivity type impurity is introduced into the semiconductor layer 3 (including a region other than the channel impurity concentration adjusting region 10) by an impurity introduction step carried out at an appropriate time point (e.g. before or after forming the semiconductor layer 3 projecting from the surface of the substrate by patterning). In the second production method of the first embodiment, the channel impurity concentration adjusting region 10 is formed by slanting ion implantation, and therefore the impurity distribution in and near the channel impurity concentration adjusting region 10 is slightly different from that in the first production method of the first embodiment, but the channel impurity concentration adjusting region 10 satisfying a typical structure of the first embodiment is formed on the upper part of the semiconductor layer 3. However, in the second production method of the first embodiment, the channel impurity concentration adjusting region 10 is formed by slanting ion implantation, and therefore there may be an impurity distribution in which the impurity concentration changes in the longitudinal direction of a channel (direction in which two source/drain regions are linked) in the channel impurity concentration adjusting region 10 depending on the condition of ion implantation.
Here, a typical structure of the first embodiment can be produced by setting the depth and the impurity concentration of the channel impurity concentration adjusting region 10 so as to satisfy the typical structure of the first embodiment.
A replacement gate process may be applied for this production method. That is, in the production method described herein, a method of carrying out a production step in which a dummy gate electrode straddling the semiconductor layer 3 is processed instead of the gate electrode, slanting ion implantation is carried out using the dummy gate electrode as a mask to form a channel impurity concentration adjusting region 10 of which the concentration of a second conductivity type impurity is higher than that in other regions of the semiconductor layer 3 on the upper part of the semiconductor layer 3, a step of removing the dummy gate is carried out in an appropriate stage, for example after forming an interlayer insulating film covering the gate electrode, and a conductive material buried in a hollow portion formed as a result of the removal of the dummy gate electrode to form a gate electrode may be used.
For the second production method of the first embodiment, a more specific example will be described with reference to FIGS. 6(a), 6(b) and 6(c), FIGS. 7(a), 7(b) and 7(c) and FIGS. 8(a), 8(b) and 8(c).
In an SOI substrate (having a configuration same as that in
Next, a gate insulating film 4 is provided on the side surface of the semiconductor layer 3, polysilicon is then deposited, etched by a normal lithography step and RIE step and thereby patterned to form a gate electrode 5 straddling the semiconductor layer 3, and slanting ion implantation is carried out with an angle provided with respect to a plane vertical to the plane of the substrate and the longitudinal direction of a channel using the gate electrode as a mask (see FIGS. 8(a), 8(b) and 8(c) illustrating a case where an angle of +θ and −θ is provided with respect to a plane vertical to the plane of the substrate and the longitudinal direction of the channel), whereby a channel impurity concentration adjusting region 10 of which the concentration of a second conductivity type impurity is higher than that in other regions of the semiconductor layer 3 is formed on the upper part of the semiconductor layer 3.
If the slanting ion implantation has an angle with respect to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel (angle ψ) in
Subsequently, high-concentration ion implantation is carried out using the gate electrode 5 as a mask, and a heat treatment is performed to provide source/drain regions 6 on the semiconductor layer 3 at a position in which the semiconductor layer 3 is not covered with the gate electrode, so that the shape in FIGS. 8(a), 8(b) and 8(c) is obtained. The gate insulating film is provided by, for example, thermally oxidizing the semiconductor layer 3. The source/drain regions are formed by introducing an impurity by an impurity introduction step such as vertical ion implantation, slanting ion implantation or plasma doping.
Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. For the insulating film forming the gate side wall 14, an insulating film such as, for example, a SiO2 monolayer film, a Si3N4 monolayer film, a multilayered film composed of SiO2 and Si3N4 is used. The insulating film forming the gate side wall 14 is formed by a film formation technique such as a CVD method. Subsequently, a metal is deposited on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5, and a heat treatment is performed to form a silicide layer 15 on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened, a contact hole is then opened to the source/drain regions 6 and the gate electrode 5, a metal is buried to form a contact 17, and an interconnect 18 composed of a metal is connected to the contact 17 (the obtained configuration is same as that in FIGS. 4(a) and 4(b) and
As shown in FIGS. 78(a), 78(b) and 78(c), if a capability of forming a hollow region is positively provided when slanting ion implantation is carried out using the gate electrode as a mask, ion implantation may be carried out not only with an angle (in FIGS. 8(a), 8(b) and 8(c), angles −θ, +θ with respect to the vertical line of the plane of the substrate in a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel) provided in a plane vertical to a wafer but also with an angle (in
Both of first slanting ion implantation which has an angle in a plane vertical to the wafer and is parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel (ion implantation illustrated in FIGS. 8(a), 8(b) and 8(c)) and second slanting ion implantation having an angle in a plane vertical to the wafer and having an angle with respect to the longitudinal direction of the channel in the plane of the wafer (ion implantation illustrated in FIGS. 78(a), 78(b) and 78(c) may be carried out. In this case, second ion plantation has a role of normal hollow ion implantation (inhibition of a short channel effect) and first ion implantation has a role of introducing into the upper part of the semiconductor layer an impurity sufficient for formation of a channel impurity concentration adjusting region capable of inhibiting parasitic transistor, thus being especially effective for formation of a FinFET with a short channel.
First slanting ion implantation which has an angle in a plane vertical to the wafer and is not parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel and second slanting ion implantation having an angle in a plane vertical to the wafer and having an angle with respect to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel, with the angle greater than that of first slanting ion implantation, may be carried out. The case where first ion implantation has a role of introducing into the upper part of the semiconductor layer an impurity sufficient for formation of a channel impurity concentration adjusting region capable of inhibiting a parasitic transistor and second slanting ion implantation has a role of hollow ion implantation is same as the aforementioned case where first slanting ion implantation is parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel. In this case, an angle with respect to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel in first slanting ion implantation is preferably 10 degrees or less in terms of formation of a channel impurity concentration adjusting region.
If energy for slanting ion implantation is low or if the angle θ is small, two channel impurity concentration adjusting regions may be formed such that they are adjacent to each other or explicitly isolated from each other, in the vicinity of two source/drain regions having a channel forming region sandwiched therebetween, but such a state will be described in the second embodiment.
Here, the depth and the impurity concentration of the channel impurity concentration region 10 are set so as to satisfy the typical structure of the first embodiment.
[Effect]
The results of simulation for a transistor characteristic when applying the first embodiment to an n-channel field effect transistor (structure in FIGS. 3(a), 3(b) and 3(c), FIGS. 4(a) and 4(b) and
If the impurity concentration is uniform throughout the semiconductor layer (Ntop/N=1), the on-current is low. In this case, the electric potential increases in an upper corner portion 34 of the semiconductor layer 3 to generate a parasitic transistor, and the off-current increases. Thus, when a comparison is made on the on-current with the off-current kept constant as in
If Ntop/N is very high (e.g. Ntop/N=6), the upper end portion of the semiconductor layer 3 does not operate as a channel. In this case, the off-current is inhibited because the parasitic transistor is inhibited, but the drain current decreases because channels are no longer formed on the upper surface 23 of the semiconductor layer and the upper side surface 24 of the semiconductor layer (see
The on-current becomes maximum when Ntop is twice as large as N. In a condition close to this condition, channels are formed on the upper surface 23 of the semiconductor layer and the upper side surface 24 of the semiconductor layer, and there is an action of inhibiting the parasitic transistor. Thus, inhibition of the off-current is compatible with improvement of the on-current, and the on-current is improved. When Ntop is twice as large as N, this action becomes most remarkable, and a maximum effect can be obtained.
When Ntop is in a range from 1.5 times to 3.5 times as large as N, an effect accounting for 75% of the maximum effect can be obtained, and a sufficient action can be obtained. When Ntop is in a range from 1.3 times to 4 times as large as N, an effect accounting for 50% of the maximum effect can be obtained, and an action that is effective in a practical standpoint is obtained.
The results of calculating a ratio of the electron concentration of a channel formed on the upper surface of the semiconductor layer to the electron concentration of a channel formed on the side surface of the semiconductor layer are shown in
Here, Ntop is determined at a position of the center in the Fin width direction (Wfin direction) on the upper surface of the semiconductor layer, but this position is a position in which a channel becomes hardest to be formed when the impurity concentration in the upper part of the semiconductor layer is increased, and therefore if a condition under which the channel is formed in this position is used, channels are formed on the entire upper surface and side surface of the channel impurity concentration adjusting region. Here, the text “channels are formed on the upper surface and the side surface” means that channel carriers are induced to an area of a certain depth of the semiconductor layer facing the upper surface and the side surface.
Thus, for inducing channel carriers to the upper surface of the semiconductor layer so that the semiconductor upper surface functions as a channel, Ntop/N is preferably 4 or less. For inducing sufficient channel carriers to the upper surface of the semiconductor layer so that the semiconductor upper layer operates sufficiently as a channel, Ntop/N is preferably 3 or less.
In the element structure described in Patent Document 1, the channel is not formed in a p+ region 20 of the upper end portion of the semiconductor layer, and therefore it is conceivable that the channel is neither formed on the upper surface of the p+ region 20 (upper surface 23 of the semiconductor layer in
In the conventional technique in which the parasitic transistor of the upper corner portion is inhibited by means of merely providing the p+ region 20 in the upper end portion of the semiconductor layer, a depleted layer does not extend throughout a portion of the semiconductor upper end portion where the impurity concentration is high, and a neutral region is formed in the portion of the semiconductor upper end portion where the impurity concentration is high. In the FinFET, it is desirable to satisfy the condition that the semiconductor layer is fully depleted and no neutral region is formed in the semiconductor layer at least in a state in which the transistor is ON (state in which a voltage equal to or greater than a threshold voltage is applied to the gate electrode) (when this condition is satisfied, the field effect transistor is called a full depletion field effect transistor). Generally, however, if the concentration of an impurity introduced into the semiconductor layer increases, the neutral region is more easily formed. On the other hand, if the condition describe in this embodiment is followed, the channel impurity concentration adjusting region can be formed on the upper part of the semiconductor layer with a depth and impurity concentration just necessary for inhibition of the parasitic transistor, and therefore a situation in which a larger amount of impurity than is necessary is introduced into the upper part of the semiconductor layer is prevented to facilitate depletion of the entire semiconductor layer. When the neutral region is formed, an abnormal operation called a substrate floatation effect in which excessive carriers are accumulated in the semiconductor layer so that the current varies tends to occur, but according to the present invention, the parasitic transistor can be inhibited and at the same time, the transistor can be operated in a fully depleted state, thus making it possible to prevent this problem. In the subthreshold, by operating the transistor in a fully depleted state, an S factor (variation in gate voltage required for changing the drain current by an order of magnitude) can be reduced to make on-off transition steep.
[Structure]
In the second embodiment, a region having a high impurity concentration is provided only in a part of the upper end portion of the semiconductor layer. This embodiment will be described with reference to
In this embodiment, a semiconductor layer 3 projecting upward from a substrate is provided, a gate electrode 5 is provided on the side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned in an appropriate dimension, and source/drain regions 6 where a first conductivity type impurity is introduced in a high concentration are formed on the semiconductor layer in a position at which the semiconductor layer is not covered with the gate electrode. On a channel forming region 7 representing the semiconductor layer covered with the gate electrode 5, a channel composed of a first conductivity type carrier is formed by applying an appropriate voltage to the gate electrode 5. An interconnect 18 is connected to the gate electrode 5 or the source/drain region 6 via a contact 17.
A second conductivity type impurity of which the concentration is higher than that in the semiconductor layer 3 excepting a channel impurity concentration adjusting region 10 is introduced into the channel impurity concentration adjusting region 10 provided over a certain area (depth Htop) extending from the upper end of the semiconductor layer 3 forming the channel forming region 7. In the second embodiment, the channel impurity concentration adjusting region 10 may be formed on a part of the semiconductor layer including an upper corner portion. In the plan view of
FIGS. 81(a) and 81(b) show a case where the channel impurity concentration adjusting region 10 is provided to contact only one of source/drain regions in the configuration shown in
FIGS. 21(a) and 21(b) show a case where in a transistor in which a hollow region is formed, the channel impurity concentration adjusting region 10 having an especially high impurity concentration is formed in and near the upper corner portion contacting the source/drain regions (position shown in
The hollow region refers to a region provided in a part of a channel region of a second conductivity type contacting the source/drain regions (or region called an extension where the source/drain regions are extended into the channel region), wherein the concentration of the second conductivity type impurity is higher than that in the channel region excepting the hollow region. A general purpose for providing the hollow region is to improve a short channel effect (variation in threshold voltage in a short channel transistor).
In the second embodiment, the ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type to the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 is set to be in a range same as the range for the ratio of Ntop to N in the first embodiment.
In the second embodiment, the ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type to the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 may be set according to a criterion different from the criterion in the first embodiment as described later.
The range of Htop applied in the second embodiment is set to a range same as the range of Htop in the first embodiment.
The definition of Htop in the second embodiment follows the definition described in the first embodiment. However, when the concentration of the channel impurity concentration adjusting region is set based on the rule for Ntop1 described later, Htop is determined according to the descriptions of the first embodiment based on the distribution of the net concentration of the second conductivity type impurity on a line for evaluation of Ntop1. When the concentration of the channel impurity concentration adjusting region is set based on the rule for Ntop2 described later, Htop is determined according to the descriptions of the first embodiment based on the distribution of the average value of the net concentration of the second conductivity type impurity at each depth in a plane for evaluation of Ntop2.
The net concentration of the second conductivity type impurity on the ordinate is an average value of the net concentration of the second conductivity type impurity in a section parallel to the plane of the substrate in the channel forming region of a second conductivity type in each position of the depth direction.
Generally, in the second embodiment, the impurity concentration of the channel impurity concentration adjusting region 10 may be higher than that for the first embodiment.
In the second embodiment, a region provided with no channel impurity concentration adjusting region 10 is locally formed on a part of the upper surface of the semiconductor layer or the upper side surface of the semiconductor layer, and this region becomes a path for a channel current (particularly, structure in
In the second embodiment, a channel is more preferably formed on the channel impurity concentration adjusting region 10 because the drain current increases as compared to a case where no channel is formed on the channel impurity concentration adjusting region 10. For a channel to be formed on the channel impurity concentration adjusting region 10, in the second embodiment, the depth and the impurity concentration of the channel impurity concentration adjusting region 10 are set so as to satisfy the condition for the channel impurity concentration adjusting region 10 in the first embodiment described above.
That is, in the second embodiment, most preferably, the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end to the depth Htop in the channel forming region of a second conductivity type is set typically to be in a range from 1.3 times to 4 times as large as the average value of the net concentration of the second conductivity impurity in a region other than the area extending from the upper end to the depth Htop in the channel forming region of a second conductivity type as in the first embodiment. More typically, the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end to the depth Htop in the channel forming region of a second conductivity type is set typically to be in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity impurity in a region other than the area extending from the upper end to the depth Htop in the channel forming region of a second conductivity type. However, in the second embodiment, Ntop may be set to be 4 times or more as large as N. This is because in the second embodiment, a region of which the concentration of the second conductivity type impurity is low is locally provided in a part of the upper surface or the upper side surface of the semiconductor layer, and therefore even if Ntop is set to be 4 times or more as large as N, a constant channel current can be passed through the upper surface or the upper side surface of the semiconductor layer.
In the second embodiment, Ntop may be set to be 1.3 times or less as large as N if Ntop is higher than N. This is because in the second embodiment, the channel impurity concentration adjusting region of which the concentration of the second conductivity type impurity is high is locally provided in a part of the upper surface or the upper side surface of the semiconductor layer, and therefore an average value for the entire channel forming region to a certain depth (Htop in the first embodiment) may be below the range of Ntop defined in the first embodiment. As a typically lower limit, if considering the configuration in
In the second embodiment, the impurity concentration in the locally provided channel impurity concentration adjusting region 10, rather than the average of the impurity concentration for the entire semiconductor layer to a certain depth, influences the operation, and therefore for forming a sufficient channel in the channel impurity concentration adjusting region 10 and obtaining an action of inhibiting the parasitic transistor of the upper corner portion as in the first embodiment, as the most preferred form of the second embodiment, Ntop1 or Ntop2 described below preferably satisfies the condition defined for Ntop in the first embodiment for the impurity concentration of the channel impurity concentration adjusting region 10.
In the second embodiment, the impurity concentration of the channel impurity concentration adjusting region 10 may be defined by an average value Ntop2 of the net concentration of the second conductivity type impurity in the area of the channel forming region extending from the upper end to the depth Htop in a section (e.g. section C-C′ in
The impurity concentration of the channel impurity concentration adjusting region 10 may be defined by an average value Ntop1 of the net concentration of the second conductivity type impurity in the area of the channel forming region extending from the upper end to the depth Htop in a distribution in the depth direction at a point p included in the channel impurity concentration adjusting region 10 (e.g. distribution from the upper end surface to the lower end surface of the semiconductor layer at the point p in
The condition for Ntop1 or Ntop2 described above is preferably satisfied over a length of 10 nm or more in the longitudinal direction of the channel for one channel impurity concentration adjusting region 10.
In the configuration in which the condition for Ntop1 or Ntop2 described above is satisfied, it is not necessary that the average value Ntop of the net concentration of the second conductivity type impurity in the area extending from the upper end to the depth Htop in the channel region of a second conductivity type should satisfy defined condition. For example, Ntop may be set to be 1.3 times or less as large as N.
In the configuration in which the condition for Ntop1 described above is satisfied, it is not necessary for Ntop2 to satisfy the defined condition. For example, Ntop2 may be set to be 1.3 times or less as large as N.
The characteristic of the electric potential difference such as Vside and Vcorner and the characteristic of the impurity concentration in the channel forming region in a transistor of which characteristics are to be improved by application of this embodiment and the transistor of this embodiment are same as those of the first embodiment.
That is, the impurity concentration of the channel impurity concentration adjusting region is set to satisfy a relationship between Ntop and N, which can reduce an increase in electric potential in the upper corner portion of the semiconductor layer, as compared to a case where no channel impurity concentration adjusting region is provided. At this time, the amount of reduction of an increase in electric potential in the upper corner portion of the semiconductor layer is preferably 60 mV or more typically in at least a part of the upper corner portion of the semiconductor layer.
The present invention is typically applied for improving the characteristic of the transistor in which the electric potential increases by 60 mV or more in at least part of the upper corner portion of the semiconductor layer when no channel impurity concentration region is provided. The present invention is typically applied for improving the characteristic of the transistor in which Vside is 120 mV or more when no channel impurity concentration adjusting region is provided.
The transistor of this embodiment has a characteristic in which Vside is typically 120 mV or more. The process for determining pside, pcorner, pcenter, Vcorner and Vside is same as that in the first embodiment. However, pside of this embodiment is selected from a region provided at any position in the channel forming region below the lower end of the channel impurity concentration adjusting region, irrespective of whether or not the channel impurity concentration adjusting region is provided just above pside.
In this connection, pside, pcorner, pcenter, Vcorner and Vside have been discussed above taking an n-channel transistor as an example, but for a p-channel transistor, the polarity is reversed.
The present invention is typically applied for improving the performance of the transistor in which the average value of the impurity concentration in the semiconductor layer is 7.5×1017 cm−3 or more when no channel impurity concentration adjusting region is provided, and therefore in the transistor of this embodiment, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting the channel impurity concentration adjusting region is typically 7.5×1017 cm−3 or more.
For a transistor with a short channel (gate length is typically 0.1 μm or less), the present invention is typically applied for improving the performance of the transistor in which the average value of the impurity concentration in the semiconductor layer is 1.0×1018 cm−3 or more when no channel impurity concentration adjusting region is provided, and in the transistor of this embodiment with a short channel, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting the channel impurity concentration adjusting region is typically 1.0×1018 cm−3 or more.
[Production Method]
The first production method of the second embodiment is a method for forming a configuration in which a channel impurity concentration adjusting region 10 is provided in the vicinity of the upper corner portion of the semiconductor layer, and no channel impurity concentration adjusting region 10 is provided in a region distant from the upper corner portion although the region is included in the upper end portion of the semiconductor layer (
The first production method of the second embodiment will be described with reference to FIGS. 14(a), 14(b) and 14(c), FIGS. 15(a), 15(b) and 15(c), FIGS. 16(a), 16(b) and 16(c) and FIGS. 17(a) and 17(b).
FIGS. 14(b), 15(b) and 16(b) are sectional views in sections B-B′ of FIGS. 14(c), 15(c) and 16(c) which are plan views, respectively, and depict the shape of a section in a position corresponding to the section B-B′ in
For producing the field effect transistor of the second embodiment, a resist pattern 22 (resist pattern may be replaced by a mask pattern composed of an oxide film) for defining an element region is formed on a semiconductor layer 38, and a second conductivity type impurity for forming a channel impurity concentration adjusting region 10 is introduced by slanting ion implantation using the resist pattern 22 as a mask. In this way, the second conductivity type impurity is introduced into the upper part of a region near the end portion of a resist in a region of the semiconductor layer 38 covered with the resist (symbol 26 in FIGS. 14(a), 14(b) and 14(c) denote a region where the second conductivity type impurity is introduced). Next, an element region having a semiconductor layer 3 projecting from a substrate is formed by patterning by an etching step such as RIE using the resist pattern 22 as a mask. In this way, the channel impurity concentration adjusting region 10 which is a region where the second conductivity type impurity is higher than that in other regions of the semiconductor layer is formed in the upper corner portion of the semiconductor layer 3 (FIGS. 15(a), 15(b) and 15(c)).
The resist pattern 22 is removed, a gate insulating film 4 is then formed on the side surface of the semiconductor 3, a gate electrode material is deposited, the gate electrode material is then patterned by RIE (reactive ion etching) or the like to form a gate electrode 5, and a high-concentration first conductivity type impurity is introduced into a region of the semiconductor layer 3 which is not covered with gate electrode 5, whereby source/drain regions 6 are formed (FIGS. 16(a), 16(b) and 16(c)). Thereafter, an interlayer insulating film is deposited, and a contact 17 and an interconnect 18 are formed for the source/drain regions 6 and the gate electrode 5 by a normal method (FIGS. 17(a) and 17(b), the form of the plan view is same as that of
The depth and the impurity concentration of the channel impurity concentration adjusting region 10 are set so as to satisfy the structural characteristic of the second embodiment described above.
A specific example of the first production method of the second embodiment will be described as a supplementary explanation.
In the specific example, in an SOI substrate prepared by, for example, laminating a buried insulating layer 2 composed of an insulating material such as SiO2 on a support substrate 1 composed of silicon and further laminating thereon a semiconductor layer 38 composed of monocrystalline silicon, a resist pattern 22 for defining an element region is provided by a normal lithography step (FIGS. 14(a), 14(b) and 14(c)).
For a step of forming a gate side wall 14, an interlayer insulating film 16, a contact 17, an interconnect 18 and the like after forming a gate electrode 5, a step same as that of the first production method of the first embodiment or the second production method of the first embodiment is used.
The second production method of the second embodiment is a method for forming a configuration in which a channel impurity concentration adjusting region 10 is provided so as to include a part of the upper corner portion, only in the vicinity of a portion of the upper end of a channel forming region 7 contacting source/drain regions 6, and no channel impurity concentration adjusting region 10 is provided in a region distant from the source/drain regions 6 although the region is included in the upper end portion of the semiconductor layer (
The second production method of the second embodiment will be described with reference to FIGS. 18(a), 18(b) and 18(c) and FIGS. 19(a) and 19(b).
The second production method of the second embodiment is a method in which in the second production method of the first embodiment, the step of carrying out slanting ion implantation using a gate electrode as a mask to form on the upper part of a semiconductor layer 3 a channel impurity concentration adjusting region 10 of which the concentration of a second conductivity type impurity is higher than that in other regions of the semiconductor layer 3 is modified, and the production method excluding this step is all same as the second production method of the first embodiment.
FIGS. 18(a), 18(b) and 18(c) show a case where slanting ion implantation is carried out parallel to a plane vertical to the plane of a substrate and parallel to the longitudinal direction of a channel. Slanting ion implantation is most preferably carried out parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel in terms of formation of the channel impurity concentration adjusting region 10 on the upper part of the semiconductor layer 3 as in the second production method of the first embodiment. If an angle (angle V in
If slanting ion implanting is carried out only from one side (only at an angle −θ in
The configuration of
In the second production method of the second embodiment, channel impurity concentration adjusting regions 10 are formed by implanting ions from opposite sides of the gate electrode so as not to contact each other when slanting ion implantation is carried out using a gate electrode as a mask.
For example, ion implantation is carried out with energy lower than that in the second production method of the first embodiment. Alternatively, ions heavier than those in the second production method of the first embodiment are implanted. Alternatively, for example, the transistor of the second embodiment is formed when the second production method of the first embodiment is applied to a transistor having a long gate length.
For this production method, a displacement gate process may be applied as in the second production method of the first embodiment.
The third production method of the second embodiment is a method for a configuration in which a channel impurity concentration adjusting region 10 is provided in the vicinity of a portion where the upper corner portion of a semiconductor layer 3 contacts source/drain regions 6, and no channel impurity concentration adjusting region 10 is provided in a region distant from the source/drain regions 6 and a region distant from the upper corner portion although those regions are included in the upper end portion of the semiconductor layer (
The third production method of the second embodiment will be described with reference to FIGS. 20(a), 20(b) and 20(c) and FIGS. 21(a) and 21(b).
The third production method of the second embodiment is a method in which in the second production method of the first embodiment, the step of carrying out slanting ion implantation using a gate electrode as a mask to form on the upper part of a semiconductor layer 3 a channel impurity concentration adjusting region 10 of which the concentration of a second conductivity type impurity is higher than that in other regions of the semiconductor layer 3 is modified, and the production method excluding this step is all same as the second production method of the first embodiment.
In the third production method of the second embodiment, ion implantation is carried out with an angle (in
By providing an angle +θ, −θ in a plane perpendicular to the wafer (angle with respect to the vertical line of the plane of the substrate in a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel), the impurity concentration in the upper end portion of the semiconductor layer 3 is increased.
If slanting ion implantation is carried out only from one side of a gate (only at an angle +ψ, −ψ in
Thus, in the third production method of the second embodiment, the impurity concentration is highest in a region of the upper end portion of the semiconductor layer 3 contacting both one of the upper corner portions and one of the source/drain regions, and therefore the channel impurity concentration adjusting region 10 is formed only in the region of the upper end portion of the semiconductor layer 3 contacting both one of the upper corner portions and one of the source/drain regions.
The “region 28 having a slightly high concentration” in the figure is a region that is formed according to a feature of this production method in terms of the step, and in the region, the net concentration of the second conductivity type impurity is lower than that in the channel impurity concentration adjusting region 10, but the net concentration of the second conductivity type is higher than that in the semiconductor layer 3 below the “region 28 having a slightly high concentration”.
Both of first slanting ion implantation which has an angle in a plane vertical to the wafer and is parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel (ion implantation illustrated in FIGS. 18(a), 18(b) and 18(c)) and second slanting ion implantation having an angle in a plane vertical to the wafer and having an angle (ψ in
First slanting ion implantation which has an angle in a plane vertical to the wafer and is not parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel and second slanting ion implantation having an angle in a plane vertical to the wafer and having an angle with respect to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel, with the angle greater than that of first slanting ion implantation, may be carried out. The case where first ion implantation has a role of introducing into the upper part of the semiconductor layer an impurity sufficient for formation of a channel impurity concentration adjusting region capable of inhibiting a parasitic transistor and second slanting ion implantation has a role of hollow ion implantation is same as the aforementioned case where first ion implantation is parallel to a plane vertical to the plane of the substrate and parallel to the longitudinal direction of the channel. In this case, an angle (ψ in
[Effect]
In the second embodiment, the channel impurity concentration adjusting region 10 is formed on at least a part of each of two corner portions (positions (symbol 37) shown by two bold broken lines in the plan view of
The feature of the field effect transistor of the second embodiment in terms of the action consists in that the channel impurity concentration adjusting region 10 is limited to minimum regions necessary for inhibition of the parasitic transistor, whereby regions where the impurity concentration is locally lower than that in the channel impurity concentration adjusting region 10 are formed on the upper surface of the semiconductor layer and the upper side surface of the semiconductor layer. In the region where the impurity concentration is locally low, the threshold locally low enough to induce a channel charge easily, and the mobility of channel carriers is improved, so that a region where the channel resistance is locally low is formed. That is, in the field effect transistor of the second embodiment, the channel impurity concentration adjusting region 10 is provided in minimum necessary regions, whereby a region having a low channel resistance is expanded and the drain current is increased.
The action in the configuration of
The action in the configuration of
In the second embodiment, a channel is formed on a region of the upper end portion of the semiconductor layer where the channel impurity concentration adjusting region 10 having a high impurity concentration is not provided (e.g. near the upper end portion in the section B-B′ in
In the second embodiment, the concentration of the channel impurity concentration adjusting region 10 is most preferably controlled to the extent that the channel is formed on and near the channel impurity concentration adjusting region 10 (if the concentration in the channel impurity concentration adjusting region 10 is too high, no channel is formed not only on the channel impurity concentration adjusting region 10 but also near the channel impurity concentration adjusting region 10).
In the field effect transistor of the second embodiment, on checking with the result of simulation for the field effect transistor of the first embodiment in consideration of the fact that for the reason described previously, a channel is easily formed on the upper end portion of the semiconductor layer and a drain current equivalent or greater than that of the field effect transistor of the first embodiment is obtained, the depth and the impurity concentration of the channel impurity concentration of the channel impurity concentration adjusting region 10 are preferably set so as to satisfy the condition for the channel impurity concentration adjusting region 10 of the first embodiment, and if the condition for the field effect transistor is within the range of such a condition, a sufficient effect is obtained. For example, if the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end of the semiconductor layer to the depth Htop in the channel impurity concentration adjusting region 10 is in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity type impurity in the channel forming region excepting the area extending from the upper end of the semiconductor layer to the depth Htop in the channel impurity concentration adjusting region, a sufficient effect is obtained.
If the average value of the net concentration of the second conductivity type impurity in an area extending from the upper end to the depth Htop in the channel forming region of a second conductivity type is in a range from 1.3 times to 4 times as large as the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting the area extending from the upper end to the depth Htop, an effect which is effective from a practical standpoint is obtained.
In the second embodiment, if the average value Ntop2 of the net concentration of the second conductivity type impurity in an area extending from the upper end to the depth Htop in a section (e.g. section C-C′ in
If the average value Ntop1 of the net concentration of the second conductivity type impurity in an area extending from the upper end to the depth Htop in a distribution in the depth direction at a point p included in the channel impurity concentration adjusting region 10 (e.g. distribution from the upper end surface to the lower end surface of the semiconductor layer at the point p in
However, if the length of the channel impurity concentration adjusting region 10 in the longitudinal direction of the channel (direction in which two source/drain regions are linked; e.g. B-B′ direction in
In a configuration in which the condition for Ntop1 or Ntop2 described above is satisfied, an effect for solving the first problem is obtained even if the average value Ntop of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer to the depth Htop in the channel region of a second conductivity type does not satisfy the specified condition (e.g. Ntop is 1.3 times or less as large as N).
In the transistor of the second embodiment, it is most preferable that no neutral region is formed in the semiconductor layer as in the first embodiment. As in the case of the first embodiment, if the condition described in this embodiment is followed, the channel impurity concentration adjusting region can be formed on the upper part of the semiconductor layer with a depth and an impurity concentration just necessary for inhibiting the parasitic transistor, and therefore a situation in which a larger amount of impurity than is necessary is introduced into the upper part of the semiconductor layer is prevented to facilitate depletion of the entire semiconductor layer.
This configuration and effect in the first embodiment or the second embodiment for depletion of the entire semiconductor layer are the same in each embodiment described later in which the channel impurity concentration adjusting region is formed under the condition described in the first embodiment or the second embodiment.
A preferable range of the depth Htop of the channel impurity concentration adjusting region defining Ntop, Ntop1 and Ntop2 is same as that in the first embodiment. Htop is typically 5 nm to 24.5 nm. In view of the tradeoff between ease in the production method (production becomes easier as Htop increases in terms of production) and the effect, Htop is preferably in a range from 10 nm to 20 nm, and the most typical value of Htop is 10 nm. The preferable value of Htop is the same in each embodiment described later in which the channel impurity concentration adjusting region is formed under the condition described in the first embodiment and the second embodiment.
[Structure]
In the third embodiment, a channel impurity concentration adjusting region 10 having a configuration same as that in the first embodiment and the second embodiment is provided on both the upper end portion and lower end portion of a semiconductor layer 3.
In the third embodiment, a condition for the upper channel impurity concentration adjusting region 10 in the first embodiment and the second embodiment can appropriately be applied to a condition for the lower channel impurity concentration adjusting region. In a concentration condition for the upper channel impurity concentration adjusting region 10 in the first embodiment and the second embodiment, a concentration range defined for the net concentration of a second conductivity type impurity in the semiconductor layer excepting a certain area extending from the upper end of the semiconductor layer is applied as an impurity concentration range of the channel impurity concentration adjusting region 10 defined for the net concentration of the second conductivity type impurity in the semiconductor layer region excepting a certain area extending from the upper end of the semiconductor layer and a certain area extending from the lower end of the semiconductor layer. For example, the value of a concentration range defined for the “net concentration of the second conductivity type impurity in the semiconductor layer excepting an area extending from the upper end of the semiconductor layer 3 to the depth Htop” is applied to a concentration range defined for the “net concentration of the second conductivity type impurity in the semiconductor layer excepting both of an area extending from the upper end of the semiconductor layer 3 to the depth Htop and an area extending from the lower end of the semiconductor layer to the height Htop2”.
The third embodiment will be described with reference to FIGS. 26(a) and 26(b) and
In this embodiment, a semiconductor layer 3 projecting upward from a substrate is provided, and a gate electrode 5 is provided on the side surface of the semiconductor layer via a gate insulating film 4. The gate electrode 5 is patterned in an appropriate dimension, and source/drain regions 6 where a first conductivity type impurity is introduced in a high concentration are formed on the semiconductor layer 3 at a position in which the semiconductor layer is not covered with the gate electrode 5. A low-concentration second conductivity type impurity is introduced into a channel forming region 7 representing the semiconductor layer covered with the gate electrode 5, and a channel composed of a first conductivity type carrier is formed by applying an appropriate voltage to the gate electrode 5. An interconnect 18 is connected to the gate electrode 5 or the source/drain region 6 via a contact 17.
Into a channel impurity concentration adjusting region 10 provided over a certain area from the upper end of the semiconductor layer 3 forming the channel forming region 7 (to the depth Htop) (hereinafter referred to as an upper channel impurity concentration adjusting region 19) and a channel impurity concentration adjusting region 10 provided over a certain area from the lower end of the semiconductor layer 3 (to the height Htop2) (hereinafter referred to as a lower channel impurity concentration adjusting region 11) is introduced a second conductivity type impurity having a concentration higher than that is the semiconductor layer 3 excepting the upper channel impurity concentration adjusting region 19 and the lower channel impurity concentration adjusting region 11 (referred to as a middle channel forming region).
The impurity concentration in the lower channel impurity concentration adjusting region is adjusted to be a concentration with which an increase in electric potential in the lower corner portion of the semiconductor layer is inhibited and a channel is formed on the side surface of the lower channel impurity concentration adjusting region with application of a gate voltage.
If the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 in the channel forming region of a second conductivity type is represented by N2, the impurity concentration in the lower channel impurity concentration adjusting region is set so as to satisfy a relationship between Ntop and N2 in which an increase in electric potential in the corner portion of the upper part of the semiconductor layer can be reduced as compared to a case where no lower channel impurity concentration adjusting region is provided (i.e. a case where the impurity concentration in the lower channel impurity concentration adjusting region is replaced by N2). At this time, the amount of reduction of an increase in electric potential in the lower corner portion of the semiconductor layer is preferably 60 mV or more typically in at least a part of the lower corner portion of the semiconductor layer (the reduction amount of 60 mV corresponds to a condition under which a leak current by the parasitic transistor decreases by an order of magnitude).
In the third embodiment, a ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type to the average value (N2) of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 in the channel forming region of a second conductivity type is set to be in a range same as the range of the ratio of Ntop to N in the first embodiment.
In the third embodiment, a ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the lower end of the semiconductor layer 3 to the height Htop2 in the channel forming region of a second conductivity type to the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 is set to be in a range same as the range of the ratio of Ntop to N in the first embodiment.
The range of Htop that is applied in the third embodiment is set to a range same as the range of Htop in the first embodiment.
The range of Htop2 that is applied in the third embodiment is set to a range same as the range of Htop in the first embodiment.
Definitions of Htop and Htop2 in the third embodiment conform to those described in the first embodiment.
The average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type is typically in a range from 1.3 times to 4 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2, and more typically in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2. Alternatively, the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop is in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 exclusive of an area within 1 nm of the boundary surface.
The average value of the net concentration of the second conductivity type impurity in the area extending from the lower end of the semiconductor layer 3 to the height Htop2 in the channel forming region of a second conductivity type is typically in a range from 1.3 times to 4 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2, and more typically in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2. Alternatively, the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop is in a range from 1.5 times to 3 times as large as the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 exclusive of an area within 1 nm of the boundary surface.
In the third embodiment, the second embodiment may be applied to the upper channel impurity concentration adjusting region 19 or the lower channel impurity concentration adjusting region 11. That is, a region having a high impurity concentration is provided only in a part of the upper end portion of the semiconductor layer. Alternatively, a region having a high impurity concentration is provided only in a part of the lower end portion of the semiconductor layer. When the second embodiment is applied to the lower channel impurity concentration adjusting region 11, the “upper end portion” is replaced by the “lower end portion” in the description of the impurity distribution in the upper end portion in the second embodiment.
When the second embodiment is applied to the upper channel impurity concentration adjusting region 19, a ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the upper end of the semiconductor layer 3 to the depth Htop in the channel forming region of a second conductivity type to the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 is set to be in a range same as the range of any of the ratio of Ntop to N, the ratio of Ntop1 to N and the ratio of Ntop2 to N in the second embodiment.
When the second embodiment is applied to the lower channel impurity concentration adjusting region 11, a ratio of the average value of the net concentration of the second conductivity type impurity in the area extending from the lower end of the semiconductor layer 3 to the height Htop2 in the channel forming region of a second conductivity type to the average value of the net concentration of the second conductivity type impurity in the semiconductor layer excepting the area extending from the upper end of the semiconductor layer 3 to the depth Htop and the area extending from the lower end of the semiconductor layer 3 to the height Htop2 is set to be in a range same as the range of any of the ratio of Ntop to N, the ratio of Ntop1 to N and the ratio of Ntop2 to N in the second embodiment.
Configurations when combining the configuration of the channel impurity concentration adjusting region 10 of the second embodiment with the configuration of the upper channel impurity concentration adjusting region 19 in the third embodiment are shown in FIGS. 28(a) and 28(b), FIGS. 29(a) and 29(b) and FIGS. 30(a) and 30(b). The configurations of FIGS. 28(a) and 28(b), FIGS. 29(a) and 29(b) and FIGS. 30(a) and 30(b) are configurations obtained by combining the configurations of FIGS. 17(a) and 17(b), FIGS. 19(a) and 19(b) and FIGS. 21(a) and 21(b), respectively, with the third embodiment having the lower channel impurity concentration adjusting region 11 in the lower part of the semiconductor layer.
The “upper region 29 having a slightly high concentration 29” and the “lower region 30 having a slightly high concentration” in
The characteristic of the electric potential difference such as Vside and Vcorner and the characteristic of the impurity concentration in the channel forming region in a transistor of which the characteristic is to be improved by application of this embodiment and the transistor of this embodiment are same as those in the first embodiment.
That is, the impurity concentration in the channel impurity concentration adjusting region is set so that an increase in electric potential in the upper corner portion of the semiconductor layer and an increase in electric potential in the lower corner portion of the semiconductor layer can be reduced as compared to a case where no channel impurity concentration adjusting region is provided. At this time, at least one of the amount of reduction of an increase in electric potential in the upper corner portion of the semiconductor layer and the amount of reduction of an increase in electric potential in the lower corner portion of the semiconductor layer is preferably 60 mV or more typically in at least a part of the upper corner portion of the semiconductor layer or the lower corner portion of the semiconductor layer.
The present invention is typically applied for improving the characteristic of the transistor in which an increase in electric potential by 60 mV or more occurs in at least a part of the upper corner portion of the semiconductor layer or the lower corner portion of the semiconductor layer when no channel impurity concentration adjusting region is provided. Furthermore, the present invention is typically applied for improving the characteristic of the transistor in which Vside is 120 mV or more when no channel impurity concentration adjusting region is provided.
The transistor of this embodiment has a characteristic in which Vside is typically 120 mV or more. The process for determining pside, pcorner, pcenter, Vcorner and Vside is same as that in the first embodiment. However, pcorner is set for both the upper corner and lower corner of the semiconductor layer, and Vcorner is either Vcorner for the upper corner of the semiconductor layer or Vcorner for the lower corner of the semiconductor layer, whichever is greater. Vside is situated at a position below the lower end of the upper channel impurity concentration adjusting region and above the upper end of the lower channel impurity concentration adjusting region. When any of the upper channel impurity concentration adjusting region or the upper channel impurity concentration adjusting region is provided in accordance with the second embodiment, pside of this embodiment is selected from a region below the lower end of the upper channel impurity concentration adjusting region provided at any position in the channel forming region and above the upper end of the lower channel impurity concentration adjusting region provided at any position in the channel forming region, irrespective of whether or not the channel impurity concentration adjusting region is provided just above pside or irrespective of whether or not the channel impurity concentration adjusting region is provided just below pside.
In this connection, pside, pcorner, pcenter, Vcorner and Vside have been discussed above taking an n-channel transistor as an example, but for a p-channel transistor, the polarity is reversed. The present invention is typically applied for improving the performance of the transistor in which the average value of the impurity concentration in the semiconductor layer is 7.5×1017 cm−3 or more when neither the upper channel impurity concentration adjusting region nor the lower channel impurity concentration adjusting region is provided, and therefore in the transistor of this embodiment, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting both the upper channel impurity concentration adjusting region and the lower channel impurity concentration adjusting region is typically 7.5×1017 cm−3 or more. For the transistor with a short channel (typically, the gate length is 0.1 μm or less), the present invention is typically applied for improving the performance of the transistor in which the average value of the impurity concentration in the semiconductor layer is 1.0×1018 cm−3 or more when neither the upper channel impurity concentration adjusting region nor the lower channel impurity concentration adjusting region is provided, and in the transistor of this embodiment with a short channel, the average value of the net concentration of the second conductivity type impurity in the channel forming region of a second conductivity type excepting both the upper channel impurity concentration adjusting region and the lower channel impurity concentration adjusting region is typically 1.0×1018 cm−3 or more.
[Production Method]
One example of the production method of the third embodiment will be described with reference to FIGS. 22(a), 22(b) and 22(c),
FIGS. 22(a), 22(b) and 22(c) and
In this production method, a semiconductor layer having a low impurity concentration (shown as an epitaxial layer 12 in the figure; typically composed of monocrystalline silicon) is epitaxially grown (
Into the middle-concentration second conductivity type semiconductor layer 31 and an upper middle-concentration second conductivity type semiconductor layer 32 is introduced a second conductivity type impurity having a concentration with which an upper channel impurity concentration adjusting region 19 and a lower channel impurity concentration adjusting region 11 of the formed transistor satisfy the condition of the first embodiment or the second embodiment.
The production method of the third embodiment will be described with reference to FIGS. 22(a), 22(b) and 22(c),
Into an SOI substrate prepared by laminating a buried insulating layer 2 composed of an insulating material such as SiO2 on a support substrate 1 composed of silicon and further laminating thereon a semiconductor layer 38 composed of monocrystalline silicon (
A preferable value of the thickness Htop of the middle-concentration second conductivity type semiconductor layer 31 is typically 24.5 nm or less, and Htop is preferably 5 nm or more in terms of ease in the production method, and therefore Htop is typically 5 nm to 24.5 nm, and in view of the tradeoff between ease in the production method (production becomes easier as Htop increases in terms of production) and the effect, Htop is preferably in a range from 10 nm to 20 nm, and the most typical value of Htop is 10 nm.
The thickness of the epitaxial layer 12 is typically 30 nm to 100 nm.
Next, a semiconductor layer 3 projecting from the surface of a substrate is formed by patterning by a normal lithography step and a normal etching step such as RIE (
Subsequently, an insulating film is deposited on the entire surface and etched back to provide a gate side wall 14. For the insulating film forming the gate side wall 14, an insulating film such as, for example, a SiO2 monolayer film, a Si3N4 monolayer film, a multilayered film composed of SiO2 and Si3N4 is used. The insulating film forming the gate side wall 14 is formed by a film formation technique such as a CVD method. Subsequently, a metal is deposited on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5, and a heat treatment is carried out to form a silicide layer 15 on the upper part of the source/drain regions 6 and the upper part of the gate electrode 5. Subsequently, an interlayer insulating film 16 is deposited and flattened, a contact hole is then opened in the upper part of the source/drain regions 6 or the upper part of the gate electrode 5, a metal is buried in the contact hole to form a contact 17, and an interconnect 18 composed of a metal is connected to the contact 17 to obtain the shape in FIGS. 26(a) and 26(b) and
[Effect]
The transistor of this embodiment has an effect of inhibiting concentration of an electric field on the lower corner of a semiconductor layer in addition to an effect of inhibiting concentration of an electric field on the upper corner of the semiconductor layer. Thus, not only a parasitic in the upper corner of the semiconductor layer but also a parasitic transistor in the lower corner of the semiconductor layer can be inhibited.
[Structure]
The fourth embodiment has a configuration in which a cap insulating film thicker than a gate electrode is provided between the upper part of a projecting semiconductor layer in the present invention and the gate electrode so that a channel is not formed on the upper surface of the semiconductor layer.
For example, the fourth embodiment may have configuration in which a cap insulating film 8 is formed on the upper part of the semiconductor layer 3 and below the gate electrode 5 in the first embodiment, the second embodiment and the third embodiment. There is a configuration shown in FIGS. 44(a) and 44(b) as a configuration corresponding to FIGS. 4(a) and 4(b) in the first embodiment. There are configurations shown in FIGS. 51(a) and 51(b), FIGS. 53(a) and 53(b) and FIGS. 55(a) and 55(b) as configurations corresponding to FIGS. 17(a) and 17(b), FIGS. 19(a) and 19(b) and FIGS. 21(a) and 21(b), respectively, in the second embodiment. There is a configuration shown in FIGS. 59(a) and 59(b) as a configuration corresponding to FIGS. 26(a) and 26(b) in the third embodiment.
[Production Method]
In this embodiment, a field effect transistor can be produced by a production method similar to those of the first embodiment, the second embodiment and the third embodiment except that a step of forming a cap insulating film on a semiconductor layer is carried out before a step of forming a gate electrode.
Views for explaining the production of the configuration shown in FIGS. 44(a) and 44(b) are shown in FIGS. 41 (a) to 43(c) and FIGS. 45(a) to 47(c). FIGS. 41 (a) to 43(c) correspond to FIGS. 1 to 3(c) and FIGS. 45(a) to 47(c) correspond to FIGS. 6(a) to 8(c). In the method shown in FIGS. 1 to 3(c), a projecting semiconductor layer 3 is formed, and an impurity is then ion-implanted to form a channel impurity concentration adjusting region 10, but in FIGS. 41(a) to 43(c), an impurity region 10 as a channel impurity concentration adjusting region 10 is formed, an insulating layer 8 as a cap insulating layer is formed thereon, and patterning is then carried out to form a projecting semiconductor layer 3 having the cap insulating film 8 in the upper part. Views for explaining the production of the configuration shown in FIGS. 51(a) and 51(b) are shown in FIGS. 48(a) to 50(c). FIGS. 48(a) to 50(c) correspond to FIGS. 14(a) to 16(c). Views for explaining the production of the configuration shown in FIGS. 53(a) and 53(b) are shown in FIGS. 52(a), 52(b) and 52(c). FIGS. 52(a), 52(b) and 52(c) correspond to FIGS. 18(a), 18(b) and 18(c). Views for explaining the production of the configuration shown in FIGS. 55(a) and 55(b) are shown in FIGS. 54(a), 54(b) and 54(c). FIGS. 54(a), 54(b) and 54(c) correspond to FIGS. 20(a), 20(b) and 20(c). Views for explaining the production of the configuration shown in FIGS. 59(a) and 59(b) are shown in FIGS. 56(a) to 58(c). FIGS. 56(a) to 58(c) correspond to FIGS. 23(a) to 25(c).
For the slanting ion implantation step in FIGS. 48(a), 48(b) and 48(c), ion implantation may be carried out using a resist pattern 22 as a mask, or may be carried out using the cap insulating film 8 as a mask after removing the resist pattern 22.
In the step in FIGS. 52(a), 52(b) and 52(c) and FIGS. 54(a), 54(b) and 54(c), the gate electrode is patterned, the cap insulating film 8 in a region which is not covered with the gate electrode is subsequently etched, and slanting ion implantation is then carried out.
[Effect]
Concentration of an electric field on the upper corner of a semiconductor layer can also be inhibited in a double gate structure in which a cap insulating film 8 is provided on a semiconductor layer 3. Thus, a parasitic transistor can be inhibited in the upper corner of the semiconductor layer.
If the impurity concentration in a channel impurity concentration adjusting region is set to be in the aforementioned suitable concentration range applied to the first embodiment, the second embodiment and the third embodiment, formation of a channel on the upper side surface 24 of the semiconductor layer (
If the concentration of a second conductivity type impurity introduced into the upper end portion of the semiconductor layer for inhibiting the parasitic transistor is high (e.g. p+) in the transistor having a double gate structure, no channel is formed on the upper side surface 24 of the semiconductor layer in
Since
[Structure]
The fifth embodiment has a configuration in which a projecting semiconductor layer is united with a support substrate in the first embodiment, the second embodiment, the third embodiment and the fourth embodiment (FIGS. 74(a) and 74(b), FIGS. 75(a) and 75(b), FIGS. 76(a) and 76(b) and FIGS. 77(a) and 77(b)). FIGS. 74(a) and 74(b), FIGS. 75(a) and 75(b), FIGS. 76(a) and 76(b) and FIGS. 77(a) and 77(b) show a configuration in which the projecting semiconductor layer is united with the support substrate in embodiments shown by FIGS. 4(a) and 4(b), FIGS. 17(a) and 17(b), FIGS. 21(a) and 21(b) and FIGS. 26(a) and 26(b), respectively.
In the fifth embodiment, the channel forming region 7 refers to a region sandwiched between source/drain regions in a semiconductor layer 3 situated above the lower end of a region where gate electrodes face the semiconductor layer via a gate insulating film on the side surface of the semiconductor layer. Equally, the “channel forming region of a second conductivity type” is assumed to be a region situated above the lower end of a region where gate electrodes face a semiconductor layer via the gate insulating film on the side surface of the semiconductor layer.
[Production Method]
A field effect transistor is produced by applying the production method of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment using a bulk semiconductor substrate 40 instead of an SOI substrate.
A bulk semiconductor substrate (typically a silicon substrate) is processed by etching such as RIE to form a projecting semiconductor layer. A step of forming an under-gate insulating film 39 composed of an insulating material such as SiO2 on a substrate (e.g. depositing SiO2 by the CVD method and then etching back SiO2 to a predetermined height by RIE) is carried out after forming the projecting semiconductor layer and before forming a gate electrode.
The under-gate insulating film 39 has an action of reducing a parasitic capacity of the lower part of the gate electrode, but if it is desired to simplify the step, the capacity of the lower part of the gate electrode is allowed to increase, or the like, the step of providing the under-gate insulating film 39 may be omitted. In this case, an insulating film having a thickness comparable to the thickness of the gate insulating is formed at the position of the under-gate insulating film 39 by the step of forming the gate insulating film.
The structure above a buried insulating layer when the SOI substrate is used, but a semiconductor layer 38 is not fully removed in a region around a projecting semiconductor layer 3 (for example, when a semiconductor layer around the projecting semiconductor layer 3 is not fully removed in etching for forming the projecting semiconductor layer 3, and the lower part of the projecting semiconductor layer 3 is connected to a semiconductor layer on the buried insulating layer. See
[Effect]
In the configuration in which a projecting semiconductor layer is united with a support substrate, an effect same as the effect of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment can be obtained.
Specific examples of materials, dimensions and process conditions in first to fifth embodiments will be described.
(Support Substrate)
The support substrate 1 is normally a monocrystalline silicon wafer, but a substrate other than a silicon substrate, such as a substrate of silica, glass, sapphire or a semiconductor other than silicon, may be used.
(Buried Insulating Layer 2)
The buried insulating layer 2 is normally Sio2, but may be some other insulating material, or may be a multilayered film composed of a plurality of materials. The buried insulating layer may be a low-dielectric constant material having a dielectric constant lower than that of Sio2, such as porous SiO2 or SiOF. When the support substrate is an insulating material such as silica, glass or sapphire, the support substrate 1 may also serve as the insulating layer 2. The thickness of the buried insulating layer 2 is normally about 50 nm to 2 μm, more typically 50 nm to 200 nm, but may be 50 nm or less or 2 μm or more as necessary.
In the fifth embodiment, a structure having no buried insulating layer 2 is used.
(Semiconductor Layer 3)
The semiconductor layer 3 is most preferably monocrystalline in terms of improvement of an on-current and inhibition of an off-current, but may be a material other than a monocrystalline material, such as an amorphous material or a polycrystalline material, if the on-current is set to be low in a required specification or the off-current is set to be high in a required specification.
The semiconductor layer 3 may be replaced by a semiconductor layer other than silicon. It may be replaced by a combination of two or more types of semiconductors.
The semiconductor layer 3 has a shape projecting from the substrate plane. The substrate plane is generally the upper surface of the support substrate 1, but in the case of a structure in which the buried insulating layer 2 and the support substrate are united, the substrate plane is the upper surface of the buried insulating layer 2.
The height Hfin of the semiconductor layer 3 (see FIGS. 32(a) and 32(b) and FIGS. 33(a) and 33(b)) is typically 20 nm to 150 nm, more typically 50 nm to 100 nm, and the width Wfin of the semiconductor layer (see FIGS. 32(a) and 32(b) and FIGS. 33(a) and 33(b)) is typically 5 nm to 100 nm, more typically 15 nm to 50 nm. However, for both Hfin and Wfin, a value outside the above range may be used. However, it is preferable that the semiconductor layer in a channel forming region is depleted in a state of applying a threshold voltage to a gate electrode in terms of taking advantage of characteristics of a FinFET (the steeping of the ON-OFF characteristic represented by a reduction in S factor, etc.). For achieving a fully depleted state in which depleted layers extending from opposite side surfaces of the semiconductor layer contact each other in a state of applying a threshold voltage to the gate electrode, it is preferable that Wfin is set to normally 50 nm or less, more typically 35 nm or less.
In each example of the present invention, the upper corner portion of the semiconductor layer 3 may be processed into a rounded shape by a rounding step of thermal oxidization or the like. A shape obtained in a section corresponding to
In the configuration in which the upper corner portion is rounded, the depth Htop of the channel impurity concentration adjusting region is measured from the uppermost position of the semiconductor layer. In the configuration in which the lower corner portion of the semiconductor layer 3 on the buried insulating layer is rounded, the height Htop 2 of the channel impurity concentration adjusting region provided in the lower part of the semiconductor layer is measured from the lowermost position of the semiconductor layer.
(Gate Insulating Film 4)
The gate insulating film 4 may be formed by thermal oxidization of silicon, or may be a SiO2 film formed by some other method. For example, a SiO2 film formed by radical oxidization may be used. The gate insulating film may be replaced with a film of an insulating material other than SiO2. The gate insulating film may be replaced with a multilayered film of SiO2 and other insulating films, or a multilayered film of insulating films other than SiO2. The gate insulating film may be replaced with a material having a high dielectric constant, such as HfO2 or HfSiO4.
The equivalent oxide thickness of the gate insulating film is typically 1.2 nm to 3 nm. The equivalent oxide thickness is a value obtained by dividing the thickness of an insulating film forming the gate insulating film by the dielectric constant of the gate insulating film and multiplying the resulting quotient by the dielectric constant of SiO2. When the gate insulating film is a multilayered film, the equivalent oxide thickness is a value obtained by determining the equivalent oxide thickness by the above-mentioned method for each layer and adding up the resulting values. However, in a very small transistor, a gate insulating film having an equivalent oxide thickness of 1.2 nm or less may be used.
(Gate Electrode 5)
The gate electrode 5 may be a polycrystalline semiconductor such as polysilicon, or may be a conductor other than a polycrystalline semiconductor, such as a metal or a metal compound. If the gate electrode 5 is composed of a polycrystalline semiconductor such as polysilicon, an impurity of a first conductivity type which is the same conductivity type as that of a channel is typically introduced into polysilicon of the gate electrode 5. The gate electrode may be formed by a replacement gate process. Specifically, the gate electrode may be formed by a step of forming a shape of a gate electrode with a dummy material on a temporary basis, introducing a first conductivity type impurity in a high concentration into source/drain regions, covering the dummy material with an insulating film, and burying the gate electrode or a gate insulating film and the gate electrode in a cavity obtained by removing the dummy material.
If the gate electrode material is formed with a semiconductor such as polysilicon or a polycrystalline silicon-germanium mixed crystal, introduction of an impurity into a gate may be carried out concurrently with introduction of an impurity into the source/drain. It may be carried out concurrently with deposition of the gate electrode material. It may be carried out before the gate electrode material is deposited and processed into the shape of the gate electrode.
(Source/Drain Regions 6)
The first conductivity impurity is introduced in a high concentration into source/drain regions 6. In this specification, the source/drain regions include all of regions called shallow source/drain regions (also referred to as extension regions) and regions called deep source/drain regions.
In the FinFET, definitions of the extension region and the deep source/drain region are not generally specified, but include, for example, both of a source/drain region formed on a rectangular region adjacent to the gate in
For reducing a parasitic resistance of source/drain regions, a method in which the size of a semiconductor layer forming source/drain regions is increased in an upward or in-plane direction by epitaxially growing a semiconductor such as silicon in a part of source/drain regions may be used in combination.
A part of source/drain regions may extend into a region covered with the gate electrode.
(Channel Forming Region 7)
A low-concentration acceptor or donor impurity is introduced into the channel forming region 7. When the gate electrode is first conductivity type polysilicon, a low-concentration second conductivity type impurity is typically introduced into the channel forming region as it is necessary to set a threshold voltage to an appropriate value, and the channel forming region has a second conductivity type.
A hollow region that is a region into which the second conductivity type impurity is introduced in a concentration slightly higher than that in an area which is covered with the gate electrode and is not adjacent to source/drain regions may be provided on a region of the channel forming region covered with the gate electrode and adjacent to source/drain regions.
Each embodiment has been described taking as an example a FinFET comprising a single channel forming region, but each embodiment may be applied in a FinFET having a plurality of channel forming regions (shown in
(Cap Insulating Film 8)
The cap insulating film 8 for use in the fourth embodiment may be an insulating film of a single layer such as a SiO2 film or a Si3N4 film, or may be a multilayered film composed of an insulating film such as a SiO2 film or a Si3N4 film. The thickness of the cap insulating film 8 is typically 10 nm to 100 nm, more typically 10 nm to 50 nm, but the thickness may be at least twice as large as the thickness of the gate insulating film, and therefore may be 10 nm or less when the gate insulating film is thin.
(Channel Impurity Concentration Adjusting Region 10)
In each embodiment of the present invention, if the channel impurity concentration adjusting region is provided only in the upper part of the semiconductor layer, the impurity concentration in the channel impurity concentration adjusting region is set so as to satisfy a relationship between Ntop and N in which an increase in electric potential in the upper corner portion of the semiconductor layer can be reduced as compared to a case no channel impurity concentration adjusting region is provided (i.e. case where the impurity concentration in the channel impurity concentration adjusting region is replaced by N). At this time, the amount of reduction of an increase in electric potential in the upper corner portion of the semiconductor layer is preferably 60 mV or more (the amount of reduction of 60 mV corresponds to the condition under which a leak current by a parasitic transistor decreases by an order of magnitude) typically in at least a part of the upper corner portion of the semiconductor layer.
In each embodiment of the present invention, if the channel impurity concentration adjusting region is provided in the lower part of the semiconductor layer, the impurity concentration in the channel impurity concentration adjusting region provided in the lower part of the semiconductor layer is set so that an increase in electric potential in the lower corner portion of the semiconductor layer can be reduced as compared to a case where no channel impurity concentration adjusting region is provided in the lower part of the semiconductor layer (i.e. case where the impurity concentration in the channel impurity concentration adjusting region in the lower part of the semiconductor layer is replaced by N). At this time, the amount of reduction of an increase in electric potential in the lower corner portion of the semiconductor layer is preferably 60 mV or more typically in at least a part of the lower corner portion of the semiconductor layer).
(Gate Side Wall 14)
The gate side wall 14 may be a monolayer insulating film such as a SiO2 film or a Si3N4 film, or may be a multilayered film composed of an insulating film such as a SiO2 film or a Si3N4 film. The gate side wall 14 may be formed with a material having a dielectric constant lower than SiO2. The thickness of the gate side wall 14 is normally 20 nm to 150 nm, but may be 20 nm or less when miniaturization of the element is required.
(Silicide Layer 15)
The silicide layer 15 is composed of a material such as titanium silicide, cobalt silicide, nickel suicide or platinum silicide, but silicide other than these types of silicide may be used. The silicide layer 15 is formed by, for example, depositing a metal such as titanium, cobalt, nickel or platinum on source/drain regions by a deposition technique such as a sputtering method, and causing a silicide formation reaction to occur between the metal and the silicon layer by carrying out a heat treatment.
(Contact 17 and Interconnect 18)
The contact 17 and the interconnect 18 are formed by a normal contact formation step and a normal interconnect step. The contact 17 and the interconnect 18 are normally formed with a metal such as aluminum or copper, and other conductive materials such as TiN are combined as appropriate.
(Semiconductor Layer 38)
It is preferable that the semiconductor layer 38 is monocrystalline in terms of improvement of an on-current and inhibition of an off-current, but the on-current in a required specification is low or the off-current in a required specification is high, a material such as amorphous or polycrystalline other than monocrystalline materials may be used.
The semiconductor layer 38 may be replaced with a semiconductor layer other than silicon. The semiconductor layer 38 may be replaced with a combination of two or more types of semiconductors.
(Introduction of Impurity)
For the type and concentration of the impurity introduced by ion implantation, a donor impurity or acceptor impurity having in a concentration of 5×1018 cm−3 to 1×1021 cm−3 is typically introduced in high-concentration regions such as source/drain regions and the gate electrode. More typically, a donor impurity or acceptor impurity having in a concentration of 3×1019 cm−3 to 1×1020 cm−3 is introduced. Introduction of the impurity is carried out by, for example, ion implantation or gas phase diffusion. The typical douse amount during ion implantation is 1×1014 cm−12 to 3×1015 cm−2, more typically 3×1014 cm−12 to 1×1015 cm−2.
The net impurity concentration (the absolute value of a difference between the concentration of the first conductivity type impurity and the concentration of the second conductivity type impurity) in a low-concentration region such as the channel forming region excepting the channel impurity concentration adjusting region is typically 5×1017 cm−3 to 1×1019 cm−3, more typically 1×1018 cm−3 to 5×1018 cm−3.
However, even in a transistor having these typical impurity concentrations in main areas of the regions, these typical values may be exceeded locally depending on the condition of ion implantation.
For the first conductivity type impurity introduced into the source/drain regions and the first conductivity type impurity introduced into the gate electrode, a donor impurity having an n-type conductivity may be selected for the n-channel transistor and an acceptor impurity having a p-type conductivity may be selected for the p-channel transistor.
For the second conductivity type impurity introduced into the hollow region, an acceptor impurity having a p-type conductivity may be selected for the n-channel transistor and a donor impurity having an n-type conductivity may be selected for the p-channel transistor.
Typical examples of the n-type impurity include arsenic, phosphorous and antimony. Typical examples of the p-type impurity include boron and indium.
Activation of an ion-implanted impurity is performed by a heating treatment such as annealing by a normal electric oven or lamp annealing after ion implantation. A heat treatment for activating ions implanted into the channel region may be carried out just after ion implantation, or may be combined with a heat treatment for activating an impurity introduced into the source/drain regions.
For introduction of the impurity into the source/drain regions, a method in which the impurity is introduced into a region which is not covered with the gate electrode after formation of the gate electrode may be used, or a method in which the impurity is introduced into a region on which the source/drain regions are to be formed before formation of the gate electrode may be used.
(Arrangement of Source/Drain Regions 6, Contact 17 and Interconnect 18)
The arrangement of portions forming a semiconductor device, such as the source/drain regions 6, the interlayer insulating film 16, the contact 17 and the interconnect 18 in each embodiment, is similar to that in a normal FinFET. For example, an arrangement same as the arrangement shown in FIGS. 4(a) and 4(b) and
(Channel Type)
Each embodiment has been described mainly for the n-channel transistor, but the present invention is applied to both the n-channel transistor and the p-channel transistor. In the p-channel transistor, the same discussions hold if the polarity is reversed (for example, an increase in electric potential in the n-channel transistor is replaced by a decrease in electric potential in the p-channel transistor, a decrease in threshold voltage in the n-channel transistor is replaced by an increase in threshold voltage in the p-channel transistor, the description of “high voltage and electric potential” is replaced by the description of “low voltage and electric potential”, and the sign of an applied voltage such as a drain voltage is reversed).
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-024722 | Jan 2004 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP05/01207 | 1/28/2005 | WO | 7/28/2006 |
