Field effect transistor having its breakdown voltage enhanced

Abstract

Deterioration of the high frequency characteristics of a field effect transistor is prevented, and the on- and off-gate leakage currents are reduced. A field effect transistor comprises the fourth electrode 126 between the gate electrode 122 and the drain electrode 118. The fourth electrode is formed to satisfy the relationship of 0.25=(FP2−D)/Lgd=0.5, where Lgd represents a distance between the gate and drain electrodes and FP2−D does the distance between the drain and fourth electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the present invention will become more apparent from consideration of the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic cross-sectional view illustrating the structure of an AlGaN/GaN-HEMT in accordance with an illustrative embodiment of the present invention;

FIG. 2 plots the characteristics of the AlGaN/GaN-HEMT according to the illustrative embodiment shown in FIG. 1;

FIG. 3 plots the R versus Ig behavior for the AlGaN/GaN-HEMT according to the illustrative embodiment;

FIG. 4 schematically shows the electric potential distribution in the AlGaN/GaN-HEMT according to the illustrative embodiment;

FIG. 5 is a cross-sectional view, like FIG. 1, illustrating the structure of a MIS type of AlGaN/GaN-HEMT in accordance with an alternative embodiment of the invention;

FIG. 6 is a schematic cross-sectional view of the structure of a conventional AlGaN/GaN-HEMT;

FIG. 7 plots the transistor characteristics of the conventional AlGaN/GaN-HEMT shown in FIG. 6;

FIG. 8 is a schematic cross-sectional view illustrating the structure of the conventional AlGaN/GaN-HEMT with an FP electrode; and

FIG. 9 plots the FP electrode length versus Ig behavior for the conventional AlGaN/GaN-HEMT with the FP electrode shown in FIG. 8.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, with reference to the accompanying drawings, preferred embodiments of a field effect transistor (FET) according to the present invention will be described in detail. Those drawings are simplified schematic representations intended to generally illustrate the shape, size, and positional relationships of the various structural components to the extent that the present invention can be understood. The materials used, numerical conditions, and so forth given below are nothing but examples in the scope included in the essence of the invention, and the present invention is not limited to the specific description and illustration. Also, in order to make the figures easier to understand, the figures include portions without hatching to indicate across-section. The illustrative embodiments will be directed to an AlGaN/GaN-HEMT (High Electron Mobility Transistor) as an example of a field effect transistor.

FIG. 1 is a structural cross-sectional view of an AlGaN/GaN-HEMT in accordance with an illustrative embodiment of the invention. Description will first be made referring to FIG. 1. The illustrative embodiment include a semiconductor body 10, which includes a lamination or multiple layered structure similar to the conventional AlGaN/GaN-HEMT shown in FIG. 6. In the following, therefore, like elements and parts are designated by the same reference numerals, and those not directly pertinent to understanding the invention will not repetitively be described merely for simplicity except otherwise necessity.

In the illustrative embodiment, on the first principal surface 20 of the semiconductor body 10, silicon nitride film 114 as an example is deposited to a thickness of 50 nm as the first insulation film. The silicon nitride film 114 functioning as the first insulation film has openings 114a, 114b, and 114c formed therein for exposing therethrough part of the first principal surface 20. Further, as electrodes in ohmic contact with the part of the first principal surface 20 formed by the cap layer 110 and exposed through the openings 114a and 114b, formed are a source ohmic electrode 116 and a drain ohmic electrode 118.

In the illustrative embodiment, between the source electrode 116 and drain electrode 118, an additional electrode 126 is formed as the fourth electrode. The fourth electrode 126 is referred to as field pinning plate or simply FP2 electrode. The FP2 electrode 126 is formed on the silicon nitride film 114 as the first insulation film, for example, between a gate electrode 122 and the drain electrode 118.

Over the silicon nitride film 114 functioning as the first insulation film, the source electrode 116 and the drain electrode 118, silicon nitride film 120 is formed to a thickness of 50 nm as the second insulation film. The silicon nitride film 120 has an opening 120a cut which are identical in shape and size to, and in communication with, the opening 114c formed in the silicon nitride film 114 functioning as the first insulation film, thus allowing both of the openings to form a single opening 123 together. As an electrode made in Schottky contact with the part of the first principal surface 20 exposed through that opening 123 and formed by the cap layer 110, the gate electrode 122 is formed.

For example, the ohmic electrodes such as the source and drain electrodes 116 and 118 are a two-layered structure of Ti and Au films of 15 nm and 200 nm thick, respectively. Further, for example, the gate electrode 122 is a two-layered structure of Ni and Au films of 50 nm and 500 nm thick, respectively. As another example, the FP2 electrode 126 is a three-layered structure of Ti, Pt and Au films of 50 nm, 25 nm and 50 nm thick, respectively.

Now, the design rules of the AlGaN/GaN-HEMT with the FP2 electrode according to the illustrative embodiment are such that, for example, the gate-to-source electrode spacing (Lgs) is 0.75 μm, the gate length (Lg) 0.7 μm, the gate electrode length (GM) 1.0 μm, the gate width (Wg) 10 μm, not shown, and the gate-to-drain electrode spacing (Lgd) 4.0 μm. Further, the FP2 electrode has its length equal LFP2 to, e.g. 0.5 μm. The spacing between the edge of the FP2 electrode on the side of the drain electrode and the edge of the drain electrode on the side of the FP2 electrode will simply be referred to as “FP2-D” hereinafter. Further, the FP2 electrode 126 is wired so as to be in common to the source electrode 116.

Well, the electrical characteristics of the AlGaN/GaN-HEMT having the FP2 electrode according to the illustrative embodiment under the design rules described above will be described with reference to FIG. 2. FIG. 2 plots the Ids vs Vds characteristics and the gate leakage current behaviors at a temperature of 200° C. for the AlGaN/GaN-HEMT having the FP2 electrode described with reference to FIG. 1. In the figure, as apparent, those curves are looped due to the way of measurement.

FIG. 2 shows results of measurements on the AlGaN/GaN-HEMT where a ratio R of FP2-D to Lgd, i.e. (FP2-D)/Lgd, is equal to 0.5. The abscissa or horizontal axis represents the source-to-drain voltage Vds (unit:volt V), the left vertical axis represents the source-to-drain current Ids (unit: ampere A), and the right vertical axis represents the gate leakage current Ig (unit: ampere A) measured at the different source-to-drain voltages Vds. In this case, the gate voltage Vg varies from +1 V to −5 V in steps of 1 V, while the gate leakage current Ig is denoted as on-gate leakage current, curve E at a gate voltage of +1 V and the off-gate leakage current, curve F at a gate voltage of −5 V. It is noted that the off-gate leakage current curve F overlaps the Ids-Vds curve.

Those results reveal that at the temperature of 200° C., in comparison to the characteristics of the conventional AlGaN/GaN-HEMT plotted in FIG. 7, the on-gate leakage current, curve E, and the off-gate leakage current, curve B, are both reduced, thus demonstrating the beneficial effects of the inventive electrode design with the FP2 electrode. Particularly, the gate-off leakage current, curve B, is quite small. That is, the provision of the FP2 electrode substantially increases the gate breakdown voltage of the AlGaN/GaN-HEMT.

FIG. 3 shows how the gate leakage current of the AlGaN/GaN-HEMT having the FP2 electrode described with reference to FIG. 1 varies with the FP2-D at the temperature of 2000C. The abscissa axis represents the ratio R of the FP2-D to Lgd, i.e. (FP2-D)/Lgd and the vertical axis represents the gate leakage currents Ig in the form of current per gate width, mA/mm. In this case, the FP2 electrode is connected in common to the source electrode having its electrical potential fixed to 0 V. Curve G for the on-gate leakage current shows how the gate current Ig varies measured at the gate voltage Vg=+1 V and the source-drain voltage Vds=60 V. Further, curve H for the off-gate leakage current shows how the current Ig varies measured at Vg=−5 V and at Vds=60 V. It should be noted that the ratio R being closer to unity means the edge of the FP2 electrode on the side of the drain electrode resides closer to the gate electrode while the ration R being equal to unity means the FP2 electrode is not provided. In contrast, the ration R being closer to null means the edge of the FP2 electrode on the side of the drain electrode is provided closer to the drain electrode.

As shown in FIG. 3, if the upper limit of the allowable gate leakage current Ig is equal to about 1 mA/mm, it is then found that the off-gate leakage current, curve H, goes below the upper limit already when the ratio R of FP-D to Lgd is equal to or less than 0.75, whereas the off-gate leakage current, curve G, goes below the upper limit only when the ratio R of FP-D to Lgd is equal to or less than 0.5. Further, when the ratio R is less than 0.25, electrostatic breakdown occurred at the edge portion of the FP2 electrode on the side of the drain electrode.

A conclusion resulting from the above findings is that the AlGaN/GaN-HEMT with the FP2 electrode structure according to the invention requires that the FP2 electrode be provided with the ratio R of FP-D to Lgd equal to or more than 0.25 and not more than 0.5 in order to control or suppress the off- and on-gate leakage currents. Further, since the length LFP2 of the FP2 electrode is fixed, degradation in frequency characteristics of the transistor due to parasitic capacitance component is not observed.

From the above, it has been understood important that, according to the illustrative embodiment, the on-gate leakage current varies depending on the position of the edge of the FP2 electrode on the side of the drain electrode, i.e. the value of the ratio R, and hence the FP2 electrode is formed with the value of the ration R falling in the range from 0.25 to 0.5, both inclusive. In particular, when a higher voltage is applied between the gate and drain electrodes, an electric field induced is concentrated limitedly to the region between the FP2 and drain electrodes, which means it is important for an electric field concentration region to be far away from the edge of the gate electrode on the side of the drain electrode.

The above ideas will further be described with reference to FIG. 4. FIG. 4 depicts an electric potential distribution, simulated with a device simulator, across the cross section of the AlGaN/GaN-HEMT having the FP2 electrode 126 shown in FIG. 1 and configured to exhibit the value R equal to 0.5. The bias conditions used for the simulation are such that the drain voltage Vds is equal to 100 V and the gate voltage Vg+1 V.

In FIG. 4, the vertical axis represents, in units of μm, a depth in the direction from the first principal surface 20 of the semiconductor body 10 to the semi-insulating (SI)-SiC substrate 100, and the abscissa axis represents, also in units of μm, a distance in the direction parallel to the first principal surface 20 from the end of the source electrode 116 to the drain electrode 118 in the AlGaN/GaN-HEMT with the FP2 electrode. Beneath the first principal surface 20 is formed a two-dimensional electron gas layer 106, and between the source electrode 116 and drain electrode 118 are formed the gate electrode 122 and FP2 electrode 126. In this case, the ratio R of FP2-D to Lgd is equal to 0.5. Further, between the FP2 electrode and first principal surface is formed the silicon nitride film 114 as the first insulation film.

When a drain voltage Vds=100 V is applied, an electric potential distribution is made in such a way that the potential ranges from 0 V on the source electrode 116 to 100 V on the drain electrode 118. The potential distribution is divided into twelve zones from the region “a” on the side of the source electrode to the region “l” just below the drain electrode 118. The electric potentials of those regions are as follows. The potential of the region “a” is less than 0.0 V. The potential of the region “b” is more than 0.0 V. The potential of the region “c” is more than 10.0 V. The potential of the region “d” is more than 20.0 V. The potential of the region “e” is more than 30.0 V. The potential of the region “f” is more than 40.0 V. The potential of the region “g” is more than 50.0 V. The potential of the region “h” is more than 60.0 V. The potential of the region “i” is more than 70.0 V. The potential of the region “j” is more than 80.0 V. The potential of the region “k” is more than 90.0 V. The potential of the region “1” is more than 100.0 V.

A conclusion resulting from the simulation work is that when the equipotential regions “d” through “j”, i.e. the equipotential zones of 20.0 V through 80 V are close together on the edge of the FP2 electrode 126 on the side of the drain electrode 118. In particular, the transitional points of electric potential are far away from the edge of the gate electrode 122 on the side of the drain electrode, i.e. relatively close together at the edge of the FP2 electrode 126 on the side of the drain electrode, thereby avoiding the electric field concentration on the edge of the gate electrode.

An alternative embodiment of the present invention will be described which is directed to a MIS (Metal Insulator Semiconductor) type of AlGaN/GaN-HEMT having an FP2 electrode functioning as the fourth electrode.

FIG. 5 is a cross-sectional view illustrating the structure of the MIS type of AlGaN/GaN-HEMT having the FP2 electrode. The configuration of the semiconductor body 10 is the same as the conventional AlGaN/GaN-HEMT described with reference to FIG. 6, and therefore, the description thereof will not be repeated. Further, the electrical insulation films and electrodes formed on the semiconductor body 10 may be identical to those of the first embodiment described with reference to FIG. 1. The alternative embodiment is, however, different from the first embodiment in that silicon nitride film with a thickness of 2.5 nm is formed as gate insulation film 128 between the gate electrode 122 and the first principal surface 20 of the cap layer 110, thus establishing the gate structure of a MIS type of transistor. The primary design rules of the transistors of the illustrative embodiment may be identical to the first embodiment, and thus the description thereof will not be repetitive.

Like the first embodiment previously described, the MIS type of AlGaN/GaN-HEMT of the alternative embodiment also has the FP2 electrode 126 formed therein, and thus the electric field is concentrated on the edge of the FP2 electrode 126 on the side of the drain electrode. Accordingly, the MIS type of field effect transistor having the gate insulation film 128 formed just below the gate electrode 122 has a higher insulation breakdown voltage than the MIS type of field effect transistor without such an FP2 electrode corresponding to the electrode 126. Thus, it can be concluded that the provision of the FP2 electrode 126 allows the MIS type of field effect transistor having the gate insulation film 128 with a thickness of as thin as 2.5 nm to eliminate any reduction in insulation breakdown strength.

As described so far, according to the alternative embodiment, in the MIS type of AlGaN/GaN-HEMT having the FP2 electrode formed therein, the transitional points of electric potential lay relatively close together at the edge of the FP2 electrode on the side of the drain electrode, when a large voltage is applied to the drain electrode, in the same manner as the electric potential distribution previously described referring to FIG. 4. Accordingly, an electric field applied to the portion of the MIS structure just below the gate electrode is reduced, allowing the MIS type of field effect transistor having the MIS structure to accomplish a greater insulator breakdown voltage. Further, it is more advantageous that the FP2 electrode is formed in a position satisfying the relationship of 0.25=R=0.5. This is because the strength of an electric field applied across the MIS type of field effect transistor in the alternative embodiment depends upon the value of the ratio R similarly to the first embodiment. Further, since the length of the FP2 electrode is fixed, degradation in frequency characteristics of the transistors due to parasitic capacitance component is not observed.

The entire disclosure of Japanese patent application No. 2006-204694 filed on Jul. 27, 2006, including the specification, claims, accompanying drawings and abstract of the disclosure is incorporated herein by reference in its entirety.

While the present invention has been described with reference to the particular illustrative embodiments, it is nottoberestrictedbytheembodiments. Itistobeappreciated thatthoseskilledintheartcanchangeormodifytheembodiments without departing from the scope and spirit of the present invention.

Claims

1. A field effect transistor comprising a source electrode, a gate electrode and a drain electrode formed on a semiconductor substrate, said transistor further comprising an additional fourth electrode formed on the substrate between the gate electrode and the drain electrode,said additional electrode being disposed to satisfy a ratio of a distance between the drain electrode and said additional electrode to a distance between the gate electrode and the drain electrode falls in a range from 0.25 to 0.5, both inclusive.

2. The field effect transistor in accordance with claim 1, wherein said additional electrode is a field pinning plate electrode.

3. The field effect transistor in accordance with claim 1, further comprising an insulative layer under the gate electrode on the substrate to form a MIS (Metal Insulator Semiconductor) structure.

4. The field effect transistor in accordance with claim 1, wherein said field effect transistor is an AlGaN/GaN-HEMT (High Electron Mobility Transistor).