Patent Application
20240213338
The present disclosure generally relates to electrical devices, and more particularly, to a formation of non-self-aligned backside contact.
In semiconductor device manufacture, conventional methods use frontside contact schemes during wafer processing. In frontside contact schemes, the overlay margins involved in forming frontside contacts are fairly accurate and easy to align with features on the frontside of the device.
The fabrication process is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications. Some current fabrication techniques include forming features from both the frontside and the backside of a wafer. For example, processing features and other electronics can be powered by routing signals from a backside power delivery network.
According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a transistor device, including a source and drain region, and a gate region. A bottom dielectric isolation layer is on a backside of the transistor device. A buffer layer is on a backside of the bottom dielectric isolation layer. A first conductive contact is positioned on a backside of the transistor device in contact with a backside of the source and drain region, through the bottom dielectric isolation layer and through the buffer layer. A second conductive contact is in contact with the gate region from a frontside of the gate region.
According to another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a transistor device in a front end of line layer includes a source and drain region, and a gate region. A bottom dielectric isolation layer is in the front end of line layer and on a backside of the transistor device. A first sacrificial layer on a backside of the bottom dielectric isolation layer includes a first controlled opening. The semiconductor device also includes a middle of line layer. A back end of line layer is coupled to a frontside of the middle of line layer A first conductive contact positioned on a backside of the transistor device is in contact with a backside of the source and drain region, through the bottom dielectric isolation layer and through the first, controlled opening of the first sacrificial layer. A second conductive contact is in contact with the gate region from a frontside of the gate region and in contact with the back end of line layer. A backside power delivery network is coupled to a back side of the front end of line layer. A power rail in the backside power delivery network is in contact with a backside of the first conductive contact.
According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided. The method includes forming a transistor device including a source and drain region and a gate region. A bottom dielectric isolation layer is formed on a backside of the transistor device. A first opening in the bottom dielectric isolation layer is formed under a backside of the source and drain region. A sacrificial layer is formed on a backside of the bottom dielectric isolation layer. Material is selectively removed from the sacrificial layer. The formation of a second opening in the sacrificial layer is controlled from the selective removal of material. The second opening is positioned at least partly under the first opening. A conductive contact is formed from the backside of the sacrificial layer, in the first opening and in the second opening, in contact with the backside of the source and drain region, through the bottom dielectric isolation layer.
The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures.
The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
Some technologies related to semiconductor device manufacture increasingly use backside formed contacts. Forming contacts from the backside presents new challenges including, for example, where to position placeholder elements and how to remove some layers during the fabrication process to access elements above the target layers. In some applications, a backside contact provides an electrical connection to the source and drain of a transistor. The overlay margins for backside contacts can become more difficult to control when fabricating features from the backside of the wafer. Conventional techniques may fabricate a placeholder for the contact using a self-aligned contact technique. A source and drain may be grown over the placeholder. In this approach, the placeholder pre-defines the alignment with the source and drain for the eventual metal contact that is formed. The placeholder may be removed from the backside when the process is ready for metallization. The overlay margins near the connection to the source and drain can become harder to control when replacing the placeholder with the metal.
Embodiments of the semiconductor device technology disclosed herein address challenges related to protecting different device features while forming backside contacts during the fabrication process. Features of the subject semiconductor device and method of fabrication provide a backside contact by adding one or more buffer layers proximate the bottom dielectric isolation (BDI) layer adjacent the backside contact. The bottom dielectric isolation layer and transistor elements above the bottom dielectric isolation layer, (for example, the gate and source and drain) are protected by the buffer layers. In some aspects, the subject semiconductor device also avoids damage to the gate metal and to the bottom dielectric isolation layer that can sometimes occur during conventional contact formation from the frontside. In addition, the overlay misalignment for a backside contact is typically worse than the overlay for a frontside contact. If the overlay for a backside contact is bad enough, undesirable effects may occur including for example, short circuits between the backside contact and an adjacent transistor element, for example, gate or source/drain.
In some embodiments, the semiconductor device and method of fabrication disclosed below include one or more controllable buffer layers that are positioned below the source and drain. Areas in the buffer layers may be controllably opened to provide the contact access to the source and drain. The size and/or breadth of the openings may be selectively adjusted to control exposure to the BDI layer, which provides control over which elements above the BDI layer may be exposed to etching processes. The buffer layers protect the thin layer of BDI from the processes of forming the backside metallization for the contact. The material used for the buffer layers may be selected so that controlled removal of the material is accomplished to form a desired area for the backside contact. In some embodiments, insultation may be added to control the margin of error between the space in the buffer layers and the desired size of the backside contact. By using the insulation to fill in the space between the buffer and the metal, there is no need to use a self-alignment technique.
In some frontside methods, after the source and drain is formed, there is a recess down process that can cause pin holes in the source and drain material. During subsequent etching process, some of the chemistry can escape down the pin holes and attack the BDI layer compromising the integrity of an already thin layer.
As will be seen, features of the backside process disclosed below protect the BDI from backside process damage. The BDI layer is protected by the controllable buffer layers during any etching process during formation of the backside contact. The removal of buffer layer material is controllable when defining the area for the backside contact. So, the integrity of the BDI layer is not attacked by any of the chemistry or physical techniques used to remove material. In addition, it should be appreciated that the gate material above the BDI layer is also protected since the BDI layer does not have any compromised material that will subject the gate material to any chemistry during the formation of the backside contact.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based integrated circuits are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.
In one aspect, spatially related terminology such as “front,” “back, “frontside,” “backside,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the direction of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different directions, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different directions of the device in use or operation in addition to the direction depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. Similarly, an element described as “on top of” of another element may mean either that the element is positioned above and is not necessarily in direct contact with the underlying element. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other directions) and the spatially relative descriptors used herein should be interpreted accordingly.
As used herein, the terms “lateral”, “planar”, and “horizontal” describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, the “first surface” may be the top layer of a semiconductor device where individual circuit devices are patterned in the semiconductor material.
As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.
As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together. The phrase “electrically connected” does not necessarily mean that the elements must be directly in physical contact together—intervening elements may be provided between the “connected” or “electrically connected” elements.
Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. Nor does describing an element as “first” or “second”, etc. necessarily mean that there is an order or priority to any of the elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. It should be appreciated that the figures and/or drawings accompanying this disclosure are exemplary, non-limiting, and not necessarily drawn to scale.
It is to be understood that other embodiments may be used, and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
Front End of Line (FEOL) Layer: The FEOL is a section of a semiconductor device that includes active and/or passive electrical components including for example, transistor.
Middle of Line (MOL) Layer: The middle of line layer MOL is a section of a semiconductor device that includes source and drain contacts and a gate contacts that are used to connect the source and drain, and the gate to back end of line interconnects.
Back End of Line (BEOL): The back end of line is a layer of integrated circuit fabrication where the individual electronic components become interconnected with wiring on a wafer or other substrate. In embodiments below, the BEOL may be shown placed on the “frontside” of a layer of electrical components.
Back Side Power Delivery Network (BSPDN): A back side power delivery network is a layer of connections connecting electrical components from the back side of their layer or support structure. In embodiments disclosed below, the BSPDN may be on a side of the MOL opposite the BEOL.
Substrate: Reference to a substrate may refer to material that provides a support structure to features in or on top of the substrate material. As used below, there may be more than one substrate present in an embodiment shown. Also, since embodiments below are generally shown in cross-section, it should be understood that a substrate for a layer with patterned features may not be visible in the view so as to highlight the features for the layer.
Buffer layer: A buffer layer refers to a layer of material providing physical protection for one material from another adjacent material. The buffer layer may be insulative or conductive depending on the desired buffering between adjacent material.
Sacrificial layer: A sacrificial layer may refer to a layer of material that includes one or more concentrations of material, that may be mixed, whose rate of removal during an etching or other removal process can be controlled based on the concentration of materials present. Generally, sacrificial layers are designated for whole or partial removal during the fabrication process, to be replaced by another material. In the embodiments disclosed below, sacrificial layers of varying concentrations may be used. An example of a sacrificial layer mix includes the use of silicon and germanium. Some example mixes may use concentrations of germanium in the 25% to 35% range for one layer. Another layer may include a mix with a concentration of germanium in the 50% to 60% range. While silicon germanium is described in the examples below, other mixes may be used for the purposes of controllably removing material in some areas or layers of the device.
Referring now to
In one embodiment, the semiconductor device 100 generally includes a FEOL and MOL layer 160, a BPSDN layer 170 on a backside of the FEOL and MOL layer 160. In some embodiments, a BEOL layer 180 may be on a frontside of the FEOL and MOL layer 160. In some embodiments, a carrier wafer 190 may be on a frontside of the BEOL layer 180.
In one embodiment, the FEOL and MOL layer 160 includes one or more transistor devices 110. The transistor device 110 includes a source and drain region 120 and a gate region 130. In some embodiments, the transistor device 110 is a nanosheet type device that includes a plurality of stacked semiconductor channels 125.
On the backside of the transistor device 110, a bottom dielectric isolation (BDI) layer 142 insulates the source and drain region 120 and the gate region 130 from underlying electrical elements. Embodiments generally include a contact 150, formed from the backside of the FEOL and MOL layer 160, providing electrical contact access to the transistor device 110 through the BDI layer 142. Accordingly, the contact 150 may be referred to below as the “backside contact 150” to distinguish from other contacts (such as frontside contacts) that may be present in different embodiments. Embodiments may include one or more buffer layers adjacent the backside contact 150 as will be seen in the description of an example fabrication below. In an embodiment, a pair of buffer layers 144 and 146 may be positioned between the BDI layer 142 and an underlying backside interlayer dielectric (BILD) 148. The backside contact 150 extends to pass through the buffer layers 144, 146, the BILD 148 and the aforementioned BDI layer 142. In some embodiments, another buffer layer 174 may be positioned between the buffer layer 144 and a source and drain region adjacent the source and drain region 120 connected to the backside contact 150. The buffer layers 144 and 146 may be formed from an “etch controllable” material. In an embodiment, the buffer layers 144 and 146 may be semiconductor alloys. The alloy composition of each buffer layer 144 and 146 may be specifically chosen so that they may be etched selective to surrounding structures. More specifically, the alloy composition of buffer layer 144 is chosen so that it may be etched selective to the BDI layer 142 and the buffer layer 146. The alloy composition of buffer layer 146 is chosen so that it may be etched selective to the buffer layer 144 and the BILD 148. In some embodiments, both the buffer layer 144 and the buffer layer 146 are made from a silicon germanium (SiGe); however, each may have different concentrations of germanium so that one can be etched or removed faster than the other. Doing so results in a tapered or staggered wall from the different respective sized openings at each buffer layer. The resultant opening will be used to define the area that will receive metallization for the backside contact 150. In some embodiments, the backside contact 150 may include a tapered sidewall indexed to the walls of a tapered opening (or a staggered sidewall to index with the wall of a staggered opening) so that the tapered opening accommodates the tapered walls of the backside contact 150. For example, buffer layer 144 may include a concentration of 30% germanium. Buffer layer 146 may include a concentration of 50% germanium. If subjected to a wet etch process for the same amount of time, the buffer layer 146 with its higher concentration of germanium will indent more than the buffer layer 144. In some embodiments, insulation layers 152 and 154 may be positioned in the areas indented by the controlled removal of buffer material. As will be appreciated, by using the buffer layers 144 and 146 along with insulation layers 152 and 154, control of the overlay margin for the backside contact 150 can be improved over what is conventionally performed in the field of backside fabrication. The diameter of the overlay may range from approximately 10nm to 15nm, which is larger than conventional overlay techniques that use self-alignment. It should be further appreciated that the backside contact 150 can be placed anywhere in the buffer layers 144 and 146, which avoids landing on the BDI layer 142 (or exposing the BDI layer 142 to etching processes from the backside during fabrication), thus protecting the already thin BDI layer 142 from potential damage from the backside.
In the description of the method for fabrication below, one or more substrates may be present at any one stage. Substrates can be the same material or different materials. Substrates can be made of any suitable substrate material, such as, for example, monocrystalline Si, silicon germanium (SiGe), III-V compound semiconductor, II-VI compound semiconductor, or semiconductor-on-insulator (SOI). Group III-V compound semiconductors, for example, include materials having at least one group III element and at least one group V element, such as one or more of aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP) and alloy combinations including at least one of the foregoing materials. The alloy combinations can include binary (two elements, e.g., gallium (III) arsenide (GaAs)), ternary (three elements, e.g., InGaAs) and quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys.
In the following, a process describes a general method of forming a semiconductor device that protects a BDI layer and transistor elements above the BDI layer during backside formation of a contact is shown according to an embodiment.
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.
The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
