Claims
- 1. A method for forming features on a substrate, the method comprising the steps of:a) depositing a layer of hybrid resist on said substrate; b) exposing said hybrid resist layer in an exposure system through a mask containing at least one sub-critical dimension mask shape such that a first portion of said hybrid resist corresponding to said at least one sub-critical dimension shape is exposed to an intermediate exposure level; c) developing said hybrid resist layer such that said first portion of said hybrid resist is removed.
- 2. The method of claim 1 wherein said mask is an Nx reduction mask, where N is the amount of reduction, and wherein said sub-critical dimension shape has at least one dimension less than N times the maximum resolution of said exposure system, where the maximum resolution is defined to correspond to a Rayleigh k factor of 0.55 or less.
- 3. The method of claim 1 wherein said at least one sub-critical dimension mask shape comprises a sub-critical dimension protrusion extending from a larger mask shape.
- 4. The method of claim 1 wherein said at least one sub-critical dimension mask shape comprises a sub-critical dimension gap extending into a larger mask shape.
- 5. The method of claim 1 wherein said at least one sub-critical dimension mask shape comprises a gap between two mask shapes.
- 6. The method of claim 1 wherein said at least one sub-critical dimension mask shape comprises a plurality of sub-critical dimension shapes arranged together such that a region of said hybrid resist corresponding to said plurality of features receives an intermediate exposure.
- 7. A method for forming a feature on a semiconductor substrate, the method comprising the steps of:a) depositing a layer of hybrid resist on said semiconductor substrate; b) exposing said hybrid resist layer through a mask containing at least one mask shape, said mask shape including edges and at least one sub-critical dimension portion such that first portions of said hybrid resist corresponding to said mask shape edges and said at least one sub-critical dimension portion are exposed to intermediate exposure and become soluble in developer, and wherein second portions of said hybrid resist receive substantially no exposure and remain photoactive, and wherein third portions are fully exposed and become insoluble in developer; c) developing said hybrid resist layer such that said first portions of said hybrid resist are removed, said developing forming a patterned hybrid resist; and d) forming a feature with said patterned hybrid resist.
- 8. The method of claim 7 wherein said mask comprises an Nx reduction mask, where N is the amount of reduction and wherein said sub-critical dimension portion shape has at least one dimension less than N times the minimum feature dimension which can be accurately patterned by said exposure system, this exposure system limit being defined as corresponding to a Rayleigh k factor of 0.55 or less.
- 9. The method of claim 7 wherein said at least one sub-critical dimension portion comprises a sub-critical dimension protrusion extending from a larger mask shape.
- 10. The method of claim 7 wherein said at least one sub-critical dimension portion comprises a sub-critical dimension gap extending into a larger mask shape.
- 11. The method of claim 7 wherein said at least one sub-critical dimension portion comprises a gap between two mask shapes.
- 12. The method of claim 7 wherein said at least one sub-critical dimension portion comprises a plurality of sub-critical dimension shapes arranged together such that a region of said hybrid resist corresponding to said plurality of features receives an intermediate exposure.
- 13. The method of claim 7 wherein the step of forming a feature with said patterned hybrid resist comprises forming shallow trench isolation with said patterned hybrid resist.
- 14. The method of claim 13 wherein said shallow trench isolation includes a relatively wide isolation area corresponding to said at least one sub-critical dimension portion and relatively narrow isolation areas corresponding to said edges of said mask shape portion.
- 15. The method of claim 14 wherein said shallow trench isolation is part of a DRAM device.
- 16. The method of claim 7 wherein the step of forming a feature with said patterned hybrid resist comprises forming a gate conductor with said patterned hybrid resist.
- 17. The method of claim 16 wherein said gate conductor is part of a SRAM device.
- 18. The method of claim 16 wherein said gate conductor includes a contact area corresponding to said at least one sub-critical dimension portion and gate conductor areas corresponding to said edges of said mask shape, wherein the contact area is relatively wide compared to the gate conductor area.
- 19. The method of claim 7 wherein the step of forming a feature with said patterned hybrid resist comprises forming a local level interconnect with said patterned hybrid resist.
- 20. The method of claim 19 wherein said local level interconnect is part of a SRAM device.
- 21. The method of claim 20 wherein said local level interconnect includes a contact area corresponding to said at least one sub-critical dimension shape portion and local level interconnect areas corresponding to said edges of said mask shape, wherein the contact area is relatively wide compared to the local level interconnect area.
RELATED APPLICATIONS
This application is related to patent applications “Low ‘K’ Factor Hybrid Photoresist,” Ser. No. 08/715,288, Docket No. FI9-96-055; and “Frequency Doubling Photoresist,” Ser. No. 08/715,287, Docket No. BU9-96-047, both filed Sep. 16, 1996.
US Referenced Citations (12)