Claims
- 1. A GaAs semiconductor device comprising an enhancement-mode FET and a depletion-mode FET which have a heterojunction and at least one of which utilizes a two-dimensional electron gas, said semiconductor device comprising:
- a semi-insulating GaAs substrate;
- an updoped GaAs layer formed on said semi-insulating GaAs substrate;
- an N-type AlGaAs layer formed on said undoped GaAs layer and including an exposed portion;
- a first N-type GaAs layer formed on said N-type AlGaAs layer and having a groove formed therein;
- an etching stoppable N-type AlGaAs layer formed on said first N-type GaAs layer;
- a second N-type GaAs layer formed on said etching stoppable N-type AlGaAs layer and having a groove formed therein;
- a gate electrode of said enhancement-mode FET self-aligningly filling the groove formed in said first GaAs layer and formed on an exposed portion of said N-type AlGaAs layer for providing an electron supply layer for said enhancement-mode FET; and
- a gate electrode of said depletion-mode FET for self-aligning filling a groove formed in said second N-type GaAs layer and formed on an exposed portion of said etching stoppable AlGaAs layer, said etching stoppable layer, said first GaAs layer and said N-type AlGaAs layer providing an electron supply layer for said depletion-mode FET, said gate electrode of said enhancement-mode FET and said gate electrode of said depletion-mode FET being formed simultaneously.
- 2. A device according to claim 1, wherein a drain electrode of said enhancement-mode FET and a source electrode of said depletion-mode FET are in common.
- 3. A device according to claim 1, wherein all the electrodes of both said FET's are separated from each other.
- 4. The device of claim 1, comprising an isolation region for isolating said FETSs from each other, said isolation region extending to include the portion of said N-type AlGaAs layer underneath said depletion-mode GaAs FET, wherein only said enhancement-mode FET utilizes said two-dimensional electron gas.
- 5. The device of claim 1, comprising an isolation region for isolating said FETs, said isolation region extending to said substrate, wherein both said FETs utilize a two-dimensional electron gas.
- 6. The device of claim 1, comprising two source and drain electrodes of said FETs being provided by a single electrode.
Priority Claims (1)
Number |
Date |
Country |
Kind |
58-42007 |
Mar 1983 |
JPX |
|
Parent Case Info
This is a divisional of co-pending application Ser. No. 587,967 filed on Mar. 9, 1984.
US Referenced Citations (7)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0064370 |
Nov 1982 |
EPX |
Non-Patent Literature Citations (1)
Entry |
Hadis Morkoc et al., "The HEMT: a Superfast Transistor", pp. 28 to 35, IEEE Spectrum, Feb. 1986. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
587967 |
Mar 1984 |
|