Patent Application
20180019335
This patent document relates to semiconductor circuits and technologies based on wide bandgap semiconductor materials such as silicon carbide (SiC) and other semiconductor materials.
Semiconductor materials having wide bandgaps such as silicon carbide (SiC) semiconductor materials and others can exist in various crystalline forms and can be used to construct a range of circuits and devices. For example, in comparison with the commonly used silicon, SiC materials possess properties such as a wide bandgap structure and higher breakdown field. These properties make SiC materials attractive for a wide range of circuits and applications including high power electronics.
Techniques, systems, and devices are described for doping various regions of power circuits and devices, including circuits and devices based on SiC and GaN semiconductors and other semiconductors.
In an exemplary embodiment, a semiconductor device is disclosed. A semiconductor device comprises a doped substrate, a buffer layer, and an epitaxial layer. The buffer layer is formed over the doped substrate. The buffer layer is doped to exhibit a buffer doping profile. The epitaxial layer is formed over the buffer layer. The epitaxial layer is doped to exhibit a spatially varying epitaxial doping profile.
In an exemplary embodiment, another semiconductor device is disclosed. The semiconductor device comprises a substrate and an epitaxial layer formed over the substrate, where the epitaxial layer is doped according to an epitaxial doping profile.
Power circuits and devices can be designed and constructed to have certain properties in meeting application requirements. For instance, power circuits and devices may be constructed to exhibit a low resistance in the on-state (RON), a high resistance in the off-state, a low off-state capacitance, or a fast switching speed when switching between the on state and the off state. Semiconductors with large bandgaps, such as Silicon Carbide (SiC), may be used as alternatives to Silicon (Si) for forming power circuits and devices in many applications by offering a better trade-off in configuring these device parameters.
Power devices can be fabricated with an epitaxial drift region of constant doping. Non-uniform doping of this drift region can be used to optimize the trade-off between on-resistance and off-state blocking of a unipolar power device. A doping profile of epitaxial doping monotonically increasing away from the junction modeled as a particular infinite power series allows 11.5% reduction in cost through die-shrink. Such a non-uniform doping profile may be represented in Equation (1) below,
where Nd(x) is doping as a function of distance x from the semiconductor junction, EC is the critical electric field, VB is the blocking voltage, ε permittivity and q the electron charge.
One of the assumptions in arriving at Eq. (1) is that EC and bulk electron mobility are independent of doping. This assumption may introduce significant errors in modeling SiC or Gallium Nitride (GaN) power devices. Studies have empirically shown a wide variation of SiC breakdown and bulk mobility with doping. Accordingly, while an optimum graded epitaxy exists for SiC, the doping function can be different from Eq. (1).
The disclosed technology allows growth of the graded buffer layer 104 on the substrate 102, and the first epitaxial layer 106a formed over the graded buffer layer 104. A second epitaxial layer 106b can be further grown over the first epitaxial layer 106a. In some implementations, additional epitaxial layers can be formed over the second epitaxial layer 106b. Each of additional epitaxial layers may be formed with a doping lower than the previous epitaxial layer. The profile of buffer layer 104 doping can be optimized as a function of the distance x in the direction of growth from the doped substrate 102. The buffer layer 104 being of a desired thickness and with doping varying monotonically between epitaxial doping at the epi-buffer interface and substrate doping at the substrate-buffer interface. In an implementation, the doping of the epitaxial layer is lower than the substrate doping, and the doping of the buffer layer 104 decreases monotonically from the substrate-buffer interface to the epitaxial-buffer interface. The thickness of the buffer layer 104 and function of buffer layer doping are designed to maximize the conductivity of the device in the on-state while maintaining the off-state blocking voltage at a desired level. In addition, the buffer layer design may minimize the specific depletion capacitance of the semiconductor junction. One benefit of a reduced specific depletion capacitance is that a semiconductor device can switch between blocking and conducting states faster. This property benefits wide bandgap semiconductor devices, such as SiC and GaN, more than silicon devices because the former may operate at higher frequencies, and may have to switch between blocking and conducting states more often in a given time period. Thus, power loss due to switching may be a larger proportion in the wide bandgap semiconductor devices than power loss while in the blocking or conducting states. Thus, improving the specific depletion capacitance may reduce power switching loss which may reduce total energy loss in wide bandgap devices.
In some embodiments, the thickness of the buffer layer 104 may be lower than that of both the epitaxial layer and the substrate. Substrate thickness may vary from approximately 100 μm to 350 μm. The combined thickness of all epitaxial layers, including a single epitaxial layer, could vary from approximately 5 μm to 100 μm. The buffer layer may be approximately 0.5 μm to 2 μm. In some embodiments, the buffer layer 104 may be doped uniformly and sufficiently high to terminate reverse electric field within the buffer layer 104. The buffer layer 104 may have a lower doping concentration than the doping of the substrate.
The thickness of buffer layer 104 (“b”) such that a function of b may equal N, the doping of the first epitaxial layer 106a. The thickness of the first epitaxial layer 106a can be equal to the thickness “b” of the buffer layer 104. In some implementations, the first epitaxial layer may be doped less than the buffer layer, and the doping profile of the first epitaxial layer may monotonically decrease away from buffer layer. The rest of the epitaxial layer or the second epitaxial layer 106b may be grown at uniform doping. The first epitaxial layer 106a may have a smaller doping concentration than the doping of the buffer region to support reverse voltage in the epitaxial layer.
In an implementation, the doping of an epitaxial layer or the buffer is reduced by varying the dopant concentration in the epitaxial reactor as a function of time during the growth process. If the concentration of the dopant-containing gas is varied as a function of time, the concentration of the dopant as a function of distance from the substrate surface can be varied.
In some embodiments, a Silicon Carbide unipolar device may be manufactured with a substrate, buffer layer and epitaxial layer as shown in
In some embodiments, a Silicon Carbide unipolar device can be designed to exhibit epitaxial doping in a stepped fashion. Instead of monotonically increasing or decreasing doping, doping varies along a direction in steps, e.g., each step being higher doped than the one before but having constant doping within that step. For example, the epitaxial layer 206 of
A benefit of a SiC device with a stepped epitaxial doping is that it can reduce the resistance of the drift region (RDRIFT) below that achieved by an epitaxial layer with a constant doping. For example, in some embodiments, the drift resistance of a SiC device with a stepped epitaxial doping can be reduced by 7.34% compared to a drift resistance of a SiC device with a constant epitaxial doping. Another benefit of a SiC device with a stepped epitaxial doping is that, in some embodiments, it can permit shrinkage of approximately 3% of the die in typical commercial devices between 600 V and 1700 V while keeping the same electrical characteristics. At higher blocking voltage, for example, 10 kV, RDRIFT may be predominant in RON, and the shrink level will increase asymptotically to 7.34%.
The exemplary doping and thickness for two-step and three-step epitaxies are shown in
The top layer doping of the two-step epitaxy, N, can be determined using Equation (2):
where N2 is the equivalent one-step or constant doping, Nb is the bottom layer doping of the two-step, Wb is the bottom layer thickness of the two step, and W is the total thickness of the one and two step epitaxy. In an exemplary embodiment, Epi-step 2b may be chosen so that the width Wb of the bottom layer may be 3.05 μm with a doping Nb of 1.6×1016/cm3, and the width of the top layer may be 9.65 μm with a doping N of 7.5×1015/cm3.
where N2 is the equivalent one step doping, Nb1 is the middle layer doping, and Nb2 is the bottom layers doping, Wb1 and Wb2 are the middle and bottom layer thickness corresponding to Nb1 and Nb2, respectively, and W is the total thickness of the constant doped and three-step doped epitaxies. In an exemplary embodiment, epitaxy option 3b may be chosen so that the width Wb1 of the bottom layer may be 4.1 μm with a doping Nb1 of 1×1016/cm3, the width Wb2 of the bottom layer may be 2 μm with a doping Nb2 of 2×1016/cm3, and the width of the top layer may be 6.1 μm with a doping N of 7×1015. In another exemplary embodiment, epitaxy option 3e may be chosen so that the width Wb1 of the bottom layer may be 4.1 μm with a doping Nb1 of 1×1016/cm3, the width Wb2 of the bottom layer may be 2 μm with a doping Nb2 of 2×1016/cm3, and the width of the top layer may be 6.1 μm with a doping N of 6.7×1015/cm3. This would mean total thickness of 12.2 μm for each of the three-step epitaxy options 3b and 3e, which coincides with the thickness of the constant-doped epitaxy. In this embodiment, both the three-stepped epitaxy options 3b and 3e reduce the on-state voltage drop by 74 mV compared to the constant-doped epitaxy, while maintaining the same blocking voltage. While one of the two-stepped epitaxy option in
When the number of steps increases, the epitaxial design and advantage in characteristics will increase and tend towards the graded epitaxy. While increasing the number of steps reduces the resistivity of the SiC device in the ideal case, reducing the number of steps increases accuracy and precision of the epitaxy grown and improves uniformity.
Table 1 shows that three-step epitaxy exhibiting the same blocking performance (breakdown voltage and leakage current) as regular epitaxy while showing improved forward voltage drop (VF); translating to improvement in RDRIFT of 7.34% at room temperature and 5.47% at 175 C. The reverse leakage current and breakdown voltage are unchanged between the two cases, because peak electric field is designed not to change. Results in table-1 show that improvement in RDRIFT is a function of temperature, and reduces from 7.34% at room temperature to 5.47% at 175 C.
Table 2 shows the calculated improvement in VF and RDRIFT at 175 C for 600V, 1200V and 1700V JBS diodes. As voltage rating increases, the proportion of RDRIFT to RON increases. The resistance RON includes RDRIFT with other resistance components such as resistance from the substrate. Improvement in RON will hence increase with voltage rating and tend to 7.34%. 600V devices show additional RON improvement since Schottky diodes are superior at 600 V, and they have higher RDrift/RON. Reduction in RON translates to reduction in area of the device for the same static I-V parameters, under the assumption that increased current density doesn't significantly change junction temperature during operation. Reduction in die-size will be smaller than that reduction in active area because the overhead area of device termination is fixed. At higher voltage ratings, termination area overhead is higher, thus reducing die area savings further. Savings in die area are the highest for high current devices where most of die area is active area. Approximately 3% reduction in die-size can be achieved in commercial SiC JBS diodes in the 600 V-1700 V range by engineering the epitaxy as shown here. At higher voltage and current ratings, as RDRIFT/RON ratio increases, reduction in RON and die-size will rise with current and blocking voltage to asymptotically reach the reduction in specific RDRIFT, for example, 7.34%. ΔDie is smaller than ΔActive because die area is a sum of active area and termination area.
The disclosed technology can be applied to various wide bandgap semiconductors used to form vertical devices, for example, among others, SiC and Gallium Nitride (GaN).
The disclosed technology for the doping and thickness of the epitaxial layer in the exemplary vertical power devices can be used to achieve optimized electrical characteristics. For example, a vertical diode structure may have an optimum doping profile and thickness of the epitaxial layer to obtain the minimum drift resistance (RDRIFT) and/or minimum depletion capacitance at a constant reverse voltage. In addition, for the same graded or stepped epitaxy, different performance improvements will be achieved in different vertical power devices. For example, in a JBS diode, stepped epitaxy that lowers the doping near the anode has the added advantage of improving JBS shielding and helping lower off state leakage current. For this reason, the graded epitaxy design has to be separately optimized for each unipolar SiC device.
In addition to optimizing and reducing the on-state resistance of the device, the same scheme also reduces the off-state or depletion capacitance of the device. For the same graded or stepped epitaxy, different performance improvements will be achieved for on-resistance and off-capacitance. For example, one version of the graded or stepped epitaxy, such as shown in
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
This patent application claims the benefit of U.S. Provisional Patent Application No. 62/363,173, filed Jul. 15, 2016, entitled “GRADED AND STEPPED EPITAXY TO IMPROVE PERFORMANCE OF UNIPOLAR VERTICAL SIC POWER DEVICES”. The entire content of the before-mentioned patent application is incorporated by reference as part of the disclosure of this application.
| Number | Date | Country | |
|---|---|---|---|
| 62363173 | Jul 2016 | US |
