Patent Application
20140233297
Since the first isolation of graphene [1] in 2004, there has been an enormous amount of research done to investigate its properties. Graphene based field effect transistors (FET's) have a very high potential for electronics, especially in terms of high speed, flexibility and transparency. 100 Ghz transistors made of epitaxial graphene have already been shown by IBM [2], which is a speed beyond the theoretical upper limit for transistors using SiO2. Samsung has developed a touch screen using graphene as a transparent top conductor [3]. Ahn et al., also showed a flexible and transparent transistor using graphene [4]. There are a number of companies investing in graphene, and commercial products using graphene are expected to be produced.
Graphene can be quickly integrated into the FRAM (Ferroelectric Random Access Memory) concept, which is not very commonly used, although there is a growing interests in FRAM's. The key advantages of the FRAM are high data access time, low power consumption and high data reliability. High access times offer developers the ability to use FRAM's as cache (RAM) memories, so developers have the freedom to dynamically partition memory between cache (RAM), data storage and code space. Intel is working on a polymeric ferroelectric random access memory (PFRAM), in which the memory cells will be stacked on top of each other layer by layer. This method will decrease the device area and the production costs.
A non-volatile graphene-ferroelectric memory was developed in 2009 [5][8]. This memory comprises a graphene FET covered with an organic ferroelectric layer P(VDF-TrFE). By applying a gate bias on the ferroelectric, high and low resistance states are switched in graphene due to the electric dipole induced by the ferroelectric thin film. This switching is non-volatile because the electric dipoles in the ferroelectric film are non-volatile.
As a one-atom-thick single crystal, graphene's electronic properties [9] are closely related to its supporting substrates. SiO2 provides excellent optical contrast, the key in discovering graphene by micromechanical exfoliation, but with critical drawbacks, such as surface roughness, high concentration of surface impurity charges, surface optical phonons, hydrophilic surface properties, and low dielectric constant (κSiO2=3.9). Such drawbacks not only limit the carrier mobility but also the dielectric gating strength by the maximum polarizability Pmax=∈0κSiO2Emax≈1.7 μC/cm2, where Emax≈0.5V/nm is the breakdown field of SiO2. Substantial progress in replacing SiO2 has already been made, such as significant mobility enhancement of single-layer graphene on boron nitride [3], and non-volatile polymer (top) gating of single-layer graphene [5,10]. However, efforts in this direction are in general constrained by the difficulty of exfoliating and identifying in particular single and bilayer graphene on different substrates. The rapid progress in copper-based chemical-vapor deposition methods (Cu-CVD) has now made wafer-scale graphene synthesis and graphene transfer feasible both for single-layer graphene (SLG) [3,11] and bilayer graphene (BLG) [12], providing great advantages in substrate engineering of graphene for exploring new physics and functionalities [5, 13-17]. With respect to substrates, ferroelectric materials are unique both in non-volatile gating [5] and high polarizability up to 100 μC/cm2 (6×1014 cm−2 in charge density) [18], 60 times larger than SiO2. With such high gating strength, it is possible to heavily dope graphene beyond the linear band dispersion regime (˜1 eV) and reach the van Hove singularities [19]. Such high doping, which in contrast to electrolyte gating [20] is gate-tunable even at liquid-helium temperature, may also be of great importance for verifying the recent theoretical prediction of strong electron-phonon interactions and high-temperature superconductivity in graphane and related materials [21]. For graphene electronics, this level of gating strength may enable the opening of a sizeable non-volatile bandgap up to ˜300 meV [22] in bilayer graphene field effect transistors [23]. This may be important not only for achieving high current on-off ratio (such as >104 for logic operations) but also for improving ΔR/R for memory device applications. Equally importantly, it can significantly reduce the switching voltage to below 1V while exceeding the highest doping by SiO2 gating (1013 cm−2) [7].
In accordance with an embodiment of the invention, there is provided a graphene ferroelectric device. The device comprises a graphene transistor channel and a ferroelectric gate of the graphene transistor channel, the ferroelectric gate comprising a linear polarization at a first applied gate voltage less than a threshold voltage, and a hysteretic polarization at a second applied gate voltage greater than the threshold voltage.
In further, related embodiments, the ferroelectric gate may comprise lead zirconate titanate, such as Pb(Zro0.3 Ti0.7)O3. The threshold voltage may comprise about 1 V, i.e., an electric field of about 3 MV/m. The graphene transistor channel and the ferroelectric gate may comprise a transistor at the first applied gate voltage less than the threshold voltage and may comprise a non-volatile memory at the second applied gate voltage greater than the threshold voltage. The graphene transistor channel and the ferroelectric gate may comprise a transistor at the first applied gate voltage less than the threshold voltage, the graphene transistor channel and the ferroelectric gate being configured to control at least one memory array. The memory array may comprise at least one other graphene transistor channel and a ferroelectric gate of the other graphene transistor channel, the ferroelectric gate of the other graphene transistor channel comprising lead zirconate titanate, the at least one other graphene transistor channel and ferroelectric gate comprising a non-volatile memory at the second applied gate voltage greater than the threshold voltage. The graphene transistor channel and the at least one other graphene transistor channel may be included in an array of a plurality of graphene transistor channels on a ferroelectric substrate. The device may be configured to operate as a sensor.
In further, related embodiments, at least a portion of the device may be transparent. At least a portion of the device may be flexible. The device may comprise a flexible and transparent substrate. The graphene transistor channel may comprise a single layer of graphene. The device may comprise an on/off current ratio of at least about 10. The device may be configured to be dynamically switched by a gate bias voltage between operating as a transistor and operating as a non-volatile memory.
In further, related embodiments, the device may be configured to undergo optical switching of the graphene transistor channel between a high resistance state and a low resistance state in response to photoillumination of the device. The device may further comprise a polymer electrolyte layer. The device may be configured to enter a reversible resistance state in response to photoillumination. The photoillumination may comprise light of a wavelength from the group consisting of an ultraviolet wavelength, a visible wavelength and an infrared wavelength. A resistance of the graphene transistor channel may be configured to change in response to a wavelength of photoillumination of the device. The resistance of the graphene transistor channel may be further configured to return to a low resistance state in response to an applied gate voltage. The device may comprise a device from the group consisting of: an optically switchable non-volatile memory; a broadband wavelength detector and an optical-to-electrical data convertor.
In another embodiment according to the invention, there is provided a method of controlling the resistance state of a memory device. The method comprises exposing: at least one first selected element of the memory device, the at least one first selected element comprising at least one first graphene ferroelectric device, to photoillumination of a first selected wavelength, thereby performing a write operation of an on resistance state of the memory device. The at least one first graphene ferroelectric device comprises a first graphene transistor channel and a first ferroelectric gate of the first graphene transistor channel, the first ferroelectric gate comprising lead zirconate titanate. The method further comprises, while exposing the at least one first selected element to the photoillumination of the first selected wavelength, protecting at least one second selected element of the memory device from exposure to the photoillumination at the first selected wavelength, the at least one second selected element comprising at least one second graphene ferroelectric device comprising a second graphene transistor channel and a second ferroelectric gate of the second graphene transistor channel, the second ferroelectric gate comprising lead zirconate titanate; and exposing the at least one second selected element of the memory device to photoillumination of a second selected wavelength, while protecting the at least first selected element from exposure to the photoillumination of the second selected wavelength, thereby achieving an off resistance state of the memory device.
The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
A description of example embodiments of the invention follows.
In accordance with an embodiment of the invention, there is provided a device that can be used as a transistor and a memory simultaneously. This device comprises a graphene field effect transistor (GFET), gated with a special ferroelectric material. A graphene transistor channel has controllable resistance states that are used as binary zeroes and ones. This transistor can be used as a memory, if the ferroelectric is intentionally polarized in a non-volatile manner. A ferroelectric material such as Pb(Zr0.3Ti0.7)O3 (which is a type of lead zirconate titanate, called “PZT” herein) has a linear polarization at low gate voltages. At higher gate voltages it exhibits a large remnant polarization. By taking advantage of this property, a transistor gated with PZT can be used as a normal transistor which operates at low voltages, and if it is gated with higher voltage values it can be used a non-volatile memory. The dielectric constant of the ferroelectric material is very high compared to conventional dielectric materials that reduce the operating voltage dramatically. In other words, the ferroelectric gated transistors do not require high voltage for operation, because of the ferroelectric's high dielectric constant.
Typical memory devices include transistors to control the memory array. An embodiment according to the present invention provides a way of making memory-transistor combinations, because in terms of production, an embodiment according to the invention allows a device in which there is no difference between making a transistor or a memory.
In accordance with an embodiment of the invention, in order to be able to realize this transistor-memory duality, a special ferroelectric is used as a gate material, such as a type of lead zirconate titanate (PZT), in particular Pb(Zr0.3Ti0.7)O3 (see
In accordance with an embodiment of the invention, the ultra-high dielectric constant (κ) of PZT in the linear dielectric regime allows graphene field effect transistors to be switched on and off within ±1V (see first graph in
In accordance with an embodiment of the invention, the wafer-scale patterning and device operations of graphene-ferroelectric field effect transistors (GFeFETs) on PZT substrates have been demonstrated, integrating both transistor and non-volatile memory functionalities on the same chip by controlling the local ferroelectric polarization magnitude. In the linear regime of PZT, ultra-low-voltage operations of GFeFETs within ±1V have been demonstrated, which permits the GFeFETs to be used as controlling transistors for addressing and reading/writing of memory unit cells. After polarizing PZT, the hysteretic switching of GFeFETs is ideal for ultra-fast non-volatile data storage.
In conventional flash memories, dynamic random-access memories (DRAMs) or any other memories there is a need for transistors to control the memory arrays. An embodiment according to the present invention provides that transistors and memories can be manufactured side by side on the same chip based on the same substrate. There is no difference between making a transistor or memory, which can be used in a new device architecture in which transistors are put into the memory arrays, instead of in separate compartments as in the conventional architecture.
An embodiment according to the present invention can be used in sensors that record data. Each sensor unit can comprise a transistor, a memory array and a sensor. The memory transistor combination can be produced more easily and less expensively than prior devices, using an embodiment according to the present invention.
In an embodiment according to the present invention, the thickness of the PZT film may be less than 300 nm. At this thickness PZT is transparent and it is reported to be flexible as well [9]. Graphene, a single sheet of a carbon layer, is known to be transparent and flexible. In accordance with an embodiment of the present invention, a novel transparent and flexible transistor can be made by using these two materials (PZT and graphene).
In accordance with an embodiment of the invention, a logic cell that can be used as memory and transistor simultaneously can be used to provide a device that has a dynamic memory over transistor ratio. When there is a need for high data storage, this ratio can be increased, and when there is a need for a high speed this ratio can be decreased. Furthermore, an embodiment according to the invention may decrease production costs because both memory and the transistors can be produced by the same facility. An embodiment according to the invention provides a universal logic cell that can be used as a transistor, non-volatile memory and cache (RAM). Such a device may be used in a circuit architecture that fully benefits from the two different functionalities of each cell. With such a new architecture, cell blocks, like the page system in the NAND-flash memory, can be dedicated to memory-functions by increasing the gate bias, or can be dedicated to transistor functions by decreasing the gate bias. Graphene can increase the speed of the transistors to more than 100 GHz, and may give flexibility to the whole device.
An embodiment according to the invention is able to take advantage of graphene's unique properties as a FET channel material, such as high mobility (20,000 cm2/V*s) [7]. An embodiment according to the invention is also able to take advantage of the high dielectric constant of the ferroelectric material to decrease the operating voltage and the power consumption (in the linear dielectric regime). Further, an embodiment according to the invention is able to take advantage of the ferroelectric's two different dielectric regimes (linear and hysteric), and combines non-volatile memory and transistor properties in one device. An embodiment according to the invention provides the ability for there to be no difference in making a transistor or memory, so that devices which comprise both transistor and memory cells can be produced by one method.
An embodiment according to the invention provides a device that can be used in all electronic devices as a non-volatile memory and transistor. It can be used as a transparent, flexible memory and transistor. It can be used in sensor circuits, which may need flexibility, transparency or high speed. It can be used in memories where there is a need of transistors to control the memory. An embodiment according to the invention provides the ability for there to be no difference between transistor and memory, so that production of a memory will be easier.
Intrinsically, graphene has a low on/off current ratio, such as a ratio of about 20. This is a disadvantage in the transistor application. However, in accordance with an embodiment of the invention, there are many ways to open up a band gap in graphene that can lead to high on/off current ratios, such as about 105 or greater. One way is to make graphene be very short in one dimension; this confinement will lead to a band gap. Another way is to break the interlayer symmetry in bilayer graphene, which will lead to a band gap as well.
In one embodiment according to the invention, multilayer graphene FETs may be stacked on top of each other.
In another embodiment according to the invention, a flexible and transparent substrate may be used, and the entire device may be transparent and flexible.
In accordance with an embodiment of the invention, there are provided Cu-CVD single-layer and bilayer graphene field effect transistors on ferroelectric Pb(Zr0.3Ti0.7)O3 substrates. In a study in accordance with an embodiment of the invention, transistor and non-volatile memory operations have been realized by controlling PZT polarization magnitude. The ultra-high dielectric constant (κ) of PZT in the linear dielectric regime allows graphene field effect transistors to be switched on and off within ±1V with maximum doping exceeding 1013 cm−2. After polarizing PZT, the switching of graphene field effect transistors are characterized by a pronounced resistance hysteresis, ideal for ultra-fast non-volatile memory. Large-scale graphene used in a study in accordance with an embodiment of the invention was synthesized by the CVD method on pure copper foils [3,11]. By controlling the post-growth annealing time, graphene with high bilayer coverage of up to 40%, ideal for comparing the performance of both systems, was synthesized. Subsequently, CVD graphene was transferred to 360 nm PZT, using the method introduced by Li et al. [24,25]. Standard e-beam patterning and metallization was used to fabricate 3 μm size graphene ferroelectric graphene field effect transistors (GFeFETs). The GFeFETs were then electrically characterized from room temperature (RT) to 3K in vacuum in a four-contact configuration using lock-in amplifiers.
In a study in accordance with an embodiment of the invention, the surface morphology of PZT thin films was measured by atomic force microscopy (AFM). PZT has periodic thickness variations of ˜30 nm at a typical width of 35 μm. These are seen as stripes in optical microscopy. Cu-CVD graphene transferred on PZT shows selective enhancement in Raman 2D intensity due to multiple reflection interference [26]. Raman also indicates significant substrate-induced strain in Cu-CVD graphene on PZT. In a study in accordance with an embodiment of the invention, G peaks of Cu-CVD graphene on PZT showed a noticeable red shift of ˜10 cm−1 and broadening of full width at half maximum (FWHM), compared to CVD graphene on SiO2. Using the G red shift, the PZT-induced strain was estimated to be ˜0.2% [27]. This implies that Cu-CVD graphene adapts to the polycrystalline surface of PZT after transfer, which may provide a lithography free approach for substrate engineering of local strain in graphene [28]. Note that by reducing the thickness of PZT to 120 nm, SLG and BLG are both optically and Raman distinguishable. However, thin PZT films usually have much larger leakage currents.
In a study in accordance with an embodiment of the invention, Quantum Hall Effect (QHE) measurements were used to determine the layer number of graphene. Typical QHE for single layer and bilayer CVD GFeFET on PZT were determined. The characteristic quantization sequences of (N+1/2)4e2/h for SLG and 4Ne2/h for BLG demonstrated the high quality of the Cu-CVD graphene. In
In accordance with an embodiment of the invention, beyond the linear regime (VBG>1.1V), the polarization of PZT leads to a pronounced hysteresis in R vs. VBG (see
In accordance with an embodiment of the invention, the combination of high-quality Cu-CVD graphene and functional substrates may be used to greatly speed up the studies of all graphene-based electronics. In a study in accordance with an embodiment of the invention there has been demonstrated the wafer-scale patterning and device operations of Cu-CVD graphene-ferroelectric field effect transistors on PZT substrates, integrating both transistor and non-volatile memory functionalities on the same chip by controlling the local ferroelectric polarization magnitude. In the linear regime of PZT, ultra-low-voltage operations of GFeFETs within ±1V have been demonstrated, which can be used as controlling transistors for addressing and reading/writing of memory unit cells. After polarizing PZT, the hysteretic switching of GFeFETs in accordance with an embodiment of the invention can be used for ultra-fast non-volatile data storage. To fully utilize the switching speed of PZT, a constant doping may be used to electrostatically “bias” the symmetrical ferroelectric doping hysteresis and create two distinct resistance states [29]. This can be realized by non-destructive charge-transfer doping via the deposition of low work function materials on the top surface of GFeFETs [31].
In another embodiment according to the invention, a wavelength-dependent modulation of graphene resistance is achieved in a low-voltage graphene/PZT transistor on a PZT substrate under photo-illumination. This allows an enhancement of the carrier doping to be achieved in the graphene sheet by the optical release of trapped interfacial charges. With the addition of a top polymer electrolyte layer on the device, reversible resistance states can also occur during light pulses. Applications include optically switchable non-volatile memory, broadband wavelength detector and optical-to-electrical data convertor.
The present day (opto-)-electronics industry relies heavily on silicon-based inorganic technology. Recently, graphene—a one atom thick layer with hexagonally arranged carbon lattice—has been the focus of several research efforts directed at expanding the scope of the electronics industry. The remarkable physical properties of graphene, such as the electric-field effect, ultra-high charge carrier mobility, high optical transparency and mechanical flexibility make it particularly suitable for replacing conventional technology in several niche applications [9, 32]. The tuning of charge-carrier concentration by means of electrostatic doping in graphene shifts the Fermi level such that the resistance increases as it approaches the Dirac point where carriers change from electrons to holes [19]. While several approaches for using the graphene field-effect transistor in chemical-and-bio-sensing have been explored, [4, 33] the low voltage, non-volatile memory applications have not received sufficient attention [6]. Low voltage and non-volatile applications are useful in information storage and offer the advantage of low power consumption by the elimination of the refresh rate as with the case of flash memory. These applications will be useful for developing novel portable electronic devices and enhancing the performance of mobile phones, mp3 players, portable PCs and memory devices.
In the field of optoelectronics, non-volatile applications are relevant for optically programmable memory devices, photo-detectors and wavelength-detectors. Ferroelectric materials (e.g., PZT) have high dielectric constant with hysteretic dielectric response to an applied electric field. Electrical control of graphene transistors on ferroelectric substrates can be used for non-volatile memory applications [6]. The controllable remnant polarization of PZT shifts the Fermi level of graphene towards the Dirac point or away, leading to the realization of high and low resistance states, respectively.
Ferroelectrics fabrication techniques have progressed competitively for miniaturization while maintaining their core properties [34]. Epitaxially-grown lead zirconate titanate (PZT) substrates have also shown to enhance the mobility of graphene to 105 cm2V−1 s−1 in ambient conditions [35]. One approach to writing graphene/ferroelectric memories has been to use hysteresis loops of the ferroelectric to electrically write the “high” and “low” resistance states of the graphene channel, which, as those terms are used herein, correspond to the information storage bits of “1” and “0”, respectively.
In an embodiment according to the present invention, there is provided the optical control of the non-volatile, low-voltage operation of a Graphene-PZT transistor under photo-illumination in the ultra-violet, visible and/or infrared wavelength region (such as from about 200 nm to about 1 mm wavelength). This effect can be understood to result from the optical release of trapped interfacial charges at the graphene/PZT Schottky barrier interface allowing for modulation of ferroelectric-induced carrier doping in graphene. The influence of the switching of PZT-polarization under photo-illumination on graphene-based transistors, in accordance with an embodiment of the invention, can permit the optical writing of graphene/PZT memory devices. By choosing an appropriate wavelength of incident low-power optical pulse, a direct optical writing of the off state (“0”) and the on state (“1”) is possible for these memory devices. This high-resistance state persists even after illumination is turned off, implying a permanent change in the state of surface polarization for PZT. However, the device can be brought back to the low resistance “on” state by applying −2.5V (or another applied gate voltage) to the gate. Such device operations are useful for optical memory storage where a low power laser can be used to efficiently write the “on” or “off” state for individual memory devices in a large array, while a memory wipe or erase operation can be done with a single back gate sweep. The above phenomenon also has a strong wavelength-dependence, allowing for applications in broadband wavelength detectors and photo-detectors in the visible wavelength region.
Another embodiment of the invention comprises obtaining a reversible electrical response of graphene upon photo-illumination with a continuous optical pulse. This process allows an optical-to-electrical data conversion for the graphene/PZT memory device. In accordance with an embodiment of the invention, reversibility in the polarization changes of PZT following photo-illumination is produced, by using an additional top polymer electrolyte layer. During the processing of these devices, the higher mobility of positive Li+ ions in the polymer matrix results in the formation of a thin positively charged ionic layer adjacent to graphene [20]. The graphene gets n-doped when counter charges flow to balance the presence of ionic charges. In the presence of electrolyte ions, the interfacial built-in potential and the size of depletion zone in the ferroelectric are modified at the graphene/PZT Schottky barrier interface. The electric-field from the ions allows a return to the original polarization state when the incident optical pulse is in the off-state (or dark condition).
In yet another embodiment, incident blue-wavelength light on graphene/PZT transistors significantly enhances the maximum doping that can be achieved in graphene for a given value of voltage-range applied on the ferroelectric (it will be appreciated that other wavelengths can be used). This enhancement in the effective dielectric constant of PZT under photo-illumination with wavelengths close to the PZT band-gap represents a useful knob to achieve high-doping in graphene and to enhance the on-off ratios in graphene/ferroelectric memory devices.
The presently available graphene/ferroelectric memories only have an electrical control and readout. An embodiment according to the present invention allows for controlled manipulation of the resistance state by use of low power optical signals. This enhances the scope and application of these memory devices and can be used for the development of optical computers. A rapid writing process can be achieved, as follows. This procedure allows selected elements of the graphene/ferroelectric device array to be simultaneously exposed to incident optical pulse of selected wavelength (e.g., blue) to perform the write operation of “on” state. During this exposure, other devices can be protected from exposure by a pre-patterned mask array. These set of devices can then be simultaneously exposed to another wavelength (e.g., red) to achieve the “off” state while protecting the on-state devices from exposure by a complementary pre-patterned mask array. Besides this, when used in combination with the ferroelectric back-gate, much higher on-off ratios can be achieved in the active material (graphene) by optically enhancing the surface polarization state. In addition, the concept of optical-to-electrical data conversion will allow integration of optical and electrical components in a graphene/ferroelectric memory array, in accordance with an embodiment of the invention.
Several industrial applications of optically controlled graphene/ferroelectric memory devices in accordance with an embodiment of the invention include:
1. Optically programmable memory devices that do not require electrical voltage for writing the storage content.
2. Broadband photo-detectors operating in visible wavelength region.
3. Wavelength detectors in the visible wavelength region.
4. Next generation electronic devices with integrated optical and electrical components
5. Flexible optically controlled memory devices including flexible mobile phones, mp3 players and other storage media.
The foregoing
Polarization measurements were performed on these devices using a ferroelectric tester, in a study that was performed in accordance with an embodiment of the invention.
The addition of the polymer electrolyte layer results in graphene being heavily n-doped, as shown in
In a study in accordance with an embodiment of the invention, the changes in graphene/PZT device characteristics under photoillumination with wavelengths in different regions of the visible spectrum were investigated. In the absence of an applied gate bias, reproducible resistance changes were observed upon illumination of the device. This allows memory write operations to be realized by purely optical means for the graphene devices without a gate. For Vg=0 V, red wavelength illumination will write an “off” state while blue wavelength illumination will write an “on” state, as shown in
In addition to the above-discussed polarization-related permanent changes in the resistance of graphene upon photo-illumination of the device, it is also possible to induce reversible changes in graphene resistance under low frequency (0.05 Hz) optical pulses of different wavelengths, in accordance with an embodiment of the invention. This may be achieved by introducing a thin polymer electrolyte layer on top of the graphene device. The presence of the polymer-electrolyte layer partially reduces the intensity at the graphene/PZT interface. More importantly, the photo-illumination induced resistance changes in graphene are found to be reversible when this electrolyte layer is present. A time-dependent plot of the graphene resistance is shown in
In a study in accordance with an embodiment of the invention, to obtain insight on the reversibility of the photo-induced resistance change in the presence of the electrolyte, there was investigated the photocurrents generated at the interface for the electrolyte/graphene/PZT device under pulsed optical illumination. The sign of the generated photocurrents are positive or negative depending on the positive or negative polarization of the ferroelectric. Under red (blue) illumination, the steady-state photocurrent is positive (negative) while in the dark state, it tends towards zero, as shown in
In an experiment in accordance with an embodiment of the invention, Pb(Zr0.7, Ti0.3)O3 (PZT) films were prepared by sol-gel method on a sandwiched hetero-structure comprising of layers of 120 nm Pt, 20 nm Ti, 300 nm SiO2 on Si <100>substrate. CVD graphene grown on copper foil consisting of predominantly single layer sheet with scattered bilayers was spin coated with PMMA and etched in ammonium persulfate solution. Wet transfer of CVD graphene to PZT substrate was followed by the removal of PMMA using anisole followed by rinse in acetone and iso-propyl alcohol [3]. Graphene was isolated into (0.4 mm)2 squares by an etch mask created by standard electron beam lithography (EBL) and oxygen plasma etching followed by acetone removal of PMMA. Graphene was contacted by a subsequent EBL step followed by the thermal evaporation of 3 nm Cr/35 nm of Au lift off in acetone. A final etch was done to isolate a graphene channel between the contacts. The length and width of the graphene channel were 8 μm and 2 μm, respectively. An aqueous dispersion of polyethylene oxide: lithium perchlorate (1:0.12) was drop-cast on the device and baked dry on a hot plate at 80° C. for 5 mins.
In an experiment in accordance with an embodiment of the invention, aluminum wire leads were connected to the Au contacts by silver epoxy. All measurements were done in two terminal configuration. A Stanford SR830 lock-in amplifier sourced a constant current of 100 nA and a phase-sensitive detection of the sourcedrain voltage was also recorded. The back gate bias was applied and the gate current was monitored using Keithley 6430 sub-femtoamp sourcemeter. A function generator (DS 345) was used to source a square-wave pulsed output from the light-emitting diodes. Polarization measurements were performed using the Radiant Precision LC Ferroelectric tester.
The teachings of all patents, published applications and references cited herein are incorporated by reference in their entirety.
While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
This application claims the benefit of U.S. Provisional Application No. 61/540,593, filed on Sep. 29, 2011, and claims the benefit of U.S. Provisional Application No. 61/569,357, filed on Dec. 12, 2011. The entire teachings of the above applications are incorporated herein by reference.
This invention was made with U.S. government support under Grant No. N62909-10-1-7051 from the U.S. Office of Naval Research Global. The U.S. government has certain rights in the invention.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/SG2012/000366 | 10/1/2012 | WO | 00 | 3/21/2014 |
| Number | Date | Country | |
|---|---|---|---|
| 61540593 | Sep 2011 | US | |
| 61569357 | Dec 2011 | US |
