Patent Application
20200135898
The subject disclosure relates to hard mask replenishment for one or more etching processes, and more specifically, to replenishing a hard mask using thermal oxidation techniques to facilitate one or more etching processes.
The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements, or delineate any scope of the particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein methods that can replenish a hard mask for one or more etching processes are described.
According to an embodiment, a method is provided. The method can comprise replenishing an oxide layer onto a surface of a semiconductor substrate by thermally oxidizing the surface of the semiconductor substrate. The oxide layer can facilitate selective etching of the semiconductor substrate.
According to an embodiment, a method is provided. The method can comprise oxidizing a semiconductor substrate to form a hard mask layer on a first surface of the semiconductor substrate. The method can also comprise etching a trench into a second surface of the semiconductor substrate.
According to an embodiment, a method is provided. The method can comprise etching a semiconductor substrate. The etching can form a trench into the semiconductor substrate and can thin a hard mask layer positioned on the semiconductor substrate. The method can also comprise thermally oxidizing the semiconductor substrate to replenish the hard mask layer. Further, the method can comprise etching the semiconductor substrate to deepen the trench within the semiconductor substrate.
The following detailed description is merely illustrative and is not intended to limit embodiments and/or application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections, or in the Detailed Description section.
One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details. Additionally, cross-hatching and/or shading can be used throughout the drawings to denote like referenced materials, compositions, and/or features.
In high volume manufacturing of semiconductor devices, high etch rates can be preferred to improve manufacturing throughput. Traditional techniques that can increase etch rates during semiconductor device manufacturing can include, for example: increasing chemical reaction rates of the etching process (e.g., by increasing reaction temperatures), and/or increasing physical sputtering rates by using increased radiofrequency (“RF”) power on an electrode upon which a wafer of the semiconductor device is placed. However, traditional techniques for increasing etch rates can also decrease etch selectivity; thereby, increasing the etching of the one or more hard masks used to facilitate the etching process.
Challenges caused by the increased etching of the hard mask are traditionally met by increasing the thickness of the hard mask. For example, increasing the thickness of the hard mask can compensate for the reduced selectivity of the etch process that can result from the increased etch rates. However, as feature dimensions of the semiconductor devices shrink, increasing the thickness of the hard mask can result in high aspect ratio structures, which can collapse during subsequent manufacturing processes. Additionally, in reactive-ion etching, the increased thickness of the hard mask can also result in increasingly high aspect ratio trenches that ions have to locate to continue the etching process.
Various embodiments described herein can regard methods that facilitate one or more etching processes while minimizing the thickness of the hard masks; thereby reducing one or more aspect ratios exhibited by the semiconductor structure during manufacturing. For example, one or more embodiments described herein can regard the use of one or more thin hard masks that can be replenished after degradation by an etching process. For instance, the one or more hard masks can be replenished by oxidizing (e.g., thermally oxidizing) the semiconductor substrate that is subject to the one or more etching processes. In one or more embodiments, the semiconductor substrate subject to one or more etching processes can comprise silicon and/or can be thermally oxidized to form one or more silicon dioxide layers that can serve to protect one or more portions of the semiconductor substrate from subsequent etch processes (e.g., thereby replenishing the hard mask).
As shown in
The one or more hard mask layers 104 can comprise, for example, silicon dioxide (“SiO2”). An original thickness of the one or more hard mask layers 104 (e.g., represented by the “To” arrow shown in
The one or more etching processes can form the one or more trenches 202 at exposed portions of the top surface 106. In other words, the one or more etching processes can remove portions of the top surface 106 not protected by the one or more hard mask layers 104 to form the one or more trenches 202. In contrast, portions of the top surface 106 covered by the one or more hard mask layers 104 can be protected from the one or more etching processes.
Also shown in
The thinning of the one or more hard mask layers 104 can limit the depth to which the one or more trenches 202 can be formed into the semiconductor substrate 102; thereby limiting a first height (e.g., represented by the “H1” arrow shown in
As shown in
Additionally, in one or more embodiments the one or more protective layers 402 can be deposited more thickly within the one or more trenches 202 than on the top surface 106 located at the distal ends of the one or more columns 204. As shown in
As shown in
During the sixth stage, one or more etching processes can remove semiconductor material from the top surfaces 106 to shorten the one or more columns 204 from the first height (e.g., represented by the “H1” arrow in
During the seventh stage, the one or more hard mask layers 104 can be replenished by the replenishment process 100. For example, the semiconductor substrate 102 can be thermally oxidized to induce growth of an oxide at the distal ends of the one or more columns 204. For instance, wherein the semiconductor substrate 102 comprises silicon, thermal oxidation of the semiconductor substrate 102 can form one or more hard mask layers 104 comprising silicon dioxide. In one or more embodiments, thermal oxidation can comprise, for example: dry oxidation process, wet oxidation processes, mixed flow processes (e.g., wherein oxygen is mixed with an agent such as water, hydrochloric acid, and/or chlorine), a combination thereof, and/or the like. Further, the thermal oxidation can be performed at elevated temperatures (e.g., greater than or equal to 700 degrees Celsius (° C.) and less than or equal to 1500° C.).
As shown, in
The thermal oxidation can replenish the one or more hard mask layers 104 to a replenished thickness (e.g., represented by the “TR” arrow shown in
In one or more embodiments, the replenished thickness (e.g., represented by the “TR” shown in
In one or more embodiments, the one or more hard mask layers 104 can have the same, or substantially the same, composition at the first stage of the replenishment process 100 and the seventh stage of the replenishment processes 100. Alternatively, in one or more embodiments the one or more hard mask layers 104 can have a different composition at the first stage of the replenishment process 100 than the seventh stage of the replenishment processes 100.
For example, the one or more protective layers 402 can be etched away from the one or more trenches 202. Thus, the base 206 of the semiconductor substrate 102 can be exposed to the environment to facilitate one or more further manufacturing processes (e.g., one or more further etching processes). Additionally, removal of the one or more protective layers 402 can render the surfaces of the semiconductor substrate 102 that define the one or more trenches 202 exposed to the environment surrounding the semiconductor substrate 102; thereby facilitating one or more further developments to the one or more trenches 202 (e.g., a deepening of the one or more trenches 202 into the base 206 of the semiconductor substrate 102). Example etch processes that can facilitate the removal of the one or more protective layers 402 can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
For example, the replenished one or more hard mask layers 104 can protect the top surface 106 located at the distal ends of the one or more columns 204 from being subject to the one or more etching processes, while leaving the remaining surfaces of the semiconductor substrate 102 exposed to the one or more etching processes. For instance, the one or more etching processes can remove semiconductor material from the bottom of the one or more trenches 202; thereby diminishing the thickness (e.g., along the “Y” axis shown in
Further, the one or more etching processes that deepen the one or more trenches 202 (e.g., thereby increasing the height of the one or more columns 204) can also diminish the thickness of the one or more hard mask layers 104. For example, the diminishment of the one or more hard mask layers 104 is depicted in
The thinning of the one or more hard mask layers 104 can limit the depth to which the one or more trenches 202 can be formed into the semiconductor substrate 102; thereby limiting the fourth height (e.g., represented by the “H4” arrow shown in
Removal of the one or more hard mask layers 100 can facilitate further manufacturing processes of the subject semiconductor device. For example, the third stage through the ninth stage of the replenishment process 100 described herein can be repeated to further heighten the one or more columns 204. Advantageously, by replenishing the thickness of the one or more hard mask layers 104, the replenishment process 100 can facilitate formation of one or more columns 204 having large heights (e.g., the fourth height represented by the “H4” arrow shown in
At 1102, the method 1100 can comprise diminishing a thickness of an oxide layer, positioned on a surface of a semiconductor substrate 102, by one or more etching processes. For example, the diminishing at 1102 can be performed in accordance with the second stage of the replenishment process 100 described herein. For instance, the oxide layer can be one or more hard mask layers 104 utilized to facilitate one or more etching processes. Further, the one or more hard mask layers 104 can be positioned on the top surface 106 of the semiconductor substrate 102. Additionally, the one or more etching processes can diminish the one or more hard mask layers 104 from an original thickness (e.g., represented by “To” in
At 1104, the method 1100 can comprise replenishing the oxide layer (e.g., the one or more hard mask layers 104) onto the surface (e.g., the top surface 106) of the semiconductor substrate 102 by thermally oxidizing the surface of the semiconductor substrate 102, wherein the oxide layer can facilitate selective etching of the semiconductor substrate 102. For example, the replenishing at 1104 can be performed in accordance with the third, fourth, fifth, sixth, seventh, and/or eighth stages of the replenishment process 100 described herein. For instance, in one or more embodiments the replenishing at 1104 can comprise forming one or more protective layers 402 to protect the semiconductor substrate 102 from oxidation, while exposing the top surface 106 of the semiconductor substrate 102 to facilitate oxidation (e.g., and thereby formation of the oxide layer). For example, the one or more protective layers 402 can define the locations of oxidation and/or direct the growth of oxide. By replenishing the thickness of the oxide layer (e.g., the one or more hard mask layers 104), the method 1100 can facilitate one or more deep etching processes while using thin masking layers.
At 1202, the method 1200 can comprise diminishing a thickness of one or more oxide layers, positioned on a surface of a semiconductor substrate 102, by one or more etching processes. For example, the diminishing at 1202 can be performed in accordance with the second stage of the replenishment process 100 described herein. For instance, the oxide layer can be one or more hard mask layers 104 utilized to facilitate one or more etching processes. Further, the one or more hard mask layers 104 can be positioned on the top surface 106 of the semiconductor substrate 102. Additionally, the one or more etching processes can diminish the one or more hard mask layers 104 from an original thickness (e.g., represented by “To” in
At 1204, the method 1200 can comprise removing the one or more oxide layers (e.g., one or more hard mask layers 104) from the surface (e.g., the top surface 106) of the semiconductor substrate 102. For example, removing the oxide layer at 1204 can be performed in accordance with the third stage of the replenishment process 100 described herein. For instance, the one or more oxide layers can be removed by one or more etch processes, which can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
At 1206, the method 1200 can comprise depositing one or more protective layers 402 onto a fin structure of the semiconductor substrate 102, wherein the fin structure can comprise one or more columns 204 of the semiconductor substrate 102 extending from a base 206 of the semiconductor substrate 102. For example, the depositing at 1206 can be performed in accordance with the fourth stage of the replenishment process 100 described herein. For instance, the one or more protective layers 402 can be deposited more thickly in the one or more trenches 202 adjacent to the one or more columns 204 than on a top surface 106 of the semiconductor substrate 102, which can be located at the distal ends of the one or more columns 204. An example deposition method that can facilitate the varying thickness of the one or more protective layers 402 can be an ALD with post-dose treatment. Additionally, one of ordinary skill in the art will recognize that alternate deposition methods can also be employed to facilitate the depositing at 1206.
At 1208, the method 1200 can comprise etching away a portion of the one or more protective layers 402 from the one or more columns 204 of semiconductor substrate 102 to expose the surface (e.g., the top surface 106) of the semiconductor substrate 102. For example, the etching at 1208 can be performed in accordance with the fifth stage of the replenishment process 100 described herein. For instance, the etching at 1208 can thin entirety of the one or more protective layers 402; thereby removing the thinnest portions of the one or more protective layers 402 from the semiconductor substrate 102 (e.g., located on the top surface 106), while leaving the thicker portions of the one or more semiconductor substrate 102 (e.g., located within the one or more trenches 202).
At 1210, the method 1200 can comprise etching the surface (e.g., the top surface 106) of the semiconductor substrate 102 to shorten the one or more columns 204 of the semiconductor substrate 102. For example, the etching at 1210 can be performed in accordance with the sixth stage of the replenishment process 100 described herein. For instance, the etching at 1208 can form one or more recesses 602 into the top surface 106 of the semiconductor substrate 102 such that the one or more protective layers 402 can extend beyond the length of the one or more columns 204.
At 1212, the method 1200 can comprise replenishing the one or more oxide layers (e.g., one or more hard mask layers 104) by thermally oxidizing the surface (e.g., the top surface 106) of the semiconductor substrate 102, wherein the one or more oxide layers can facilitate selective etching of the semiconductor substrate 102. The thermal oxidization can form the one or more oxide layers. Also, the formation of the one or more oxide layers can be directed along a length (e.g., along the “Y” axis shown in
Optionally, the method 1200 can further comprise removing the one or more protective layers 402 from the semiconductor substrate 102 (e.g., in accordance with the eighth stage of the replenishment process 100 described herein) and/or subsequently etching the semiconductor substrate 102 to further define the one or more trenches 202 and thereby the one or more columns 204 (e.g., in accordance with the ninth stage of the replenishment process 100 described herein).
At 1302, the method 1300 can comprise oxidizing a semiconductor substrate 102 to form one or more hard mask layers 104 on a first surface (e.g., a top surface 106) of the semiconductor substrate 102. For example, the oxidizing at 1302 can be performed in accordance with the seventh stage of the replenishment process 100 described herein. For instance, the oxidizing at 1302 can be directed by one or more protective layers 402 to selectively position the replenishment of the one or more hard mask layers 104 onto the semiconductor substrate 102.
At 1304, the method 1300 can comprise etching one or more trenches 202 into a second surface of the semiconductor substrate 102 (e.g., into a base 206 of the semiconductor substrate 102). For example, the etching at 1304 can be performed in accordance with the ninth stage of the replenishment process 100 described herein. Thus, the semiconductor substrate 102 subject to etching can itself provide the materials to form the one or more hard mask layers 104, thereby alleviating a necessity to deposit additional hard mask materials.
At 1402, the method 1400 can comprise depositing one or more protective layers 402 on a first surface (e.g., one or more surfaces that can define one or more trenches 202 extending into the semiconductor substrate 102) of a semiconductor substrate 102, wherein the one or more protective layers 402 can be resistant to oxidation. For example, the depositing at 1402 can be performed in accordance with the fourth stage of the replenishment process 100 described herein. For instance, the one or more protective layers 402 can be deposited such that the one or more protective layers 402 have a greater thickness in the one or more trenches 202 adjacent to the one or more columns 204 than on a top surface 106 of the semiconductor substrate 102, which can be located at the distal ends of the one or more columns 204. An example deposition method that can facilitate the varying thickness of the one or more protective layers 402 can be an ALD with post-dose treatment. Additionally, one of ordinary skill in the art will recognize that alternate deposition methods can also be employed to facilitate the depositing at 1206.
At 1404, the method 1400 can comprise oxidizing a semiconductor substrate 102 to form one or more hard mask layers 104 on a second surface (e.g., a top surface 106) of the semiconductor substrate 102. For example, the oxidizing at 1302 can be performed in accordance with the seventh stage of the replenishment process 100 described herein. For instance, the oxidizing at 1302 can be directed by the one or more protective layers 402 to selectively position the replenishment of the one or more hard mask layers 104 onto the second surface (e.g., the top surface 106) of the semiconductor substrate 102.
At 1406, the method 1400 can comprise removing the one or more protective layers 402 from the first surface of the semiconductor substrate 102 (e.g., from the one or more trenches 202). For example, removing the one or more protective layers 402 can be performed in accordance with the eighth stage of the replenishment process 100 described herein. For instance, the one or more protective layers 402 can be removed by one or more etching processes, which can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
At 1408, the method 1400 can comprise etching one or more trenches 202 into the first surface of the semiconductor substrate 102. For example, the etching at 1408 can be performed in accordance with the ninth stage of the replenishment process 100 described herein. For instance, etching the one or more trenches 202 can comprise deepening one or more existing trenches 202 formed by one or more previous etching processes. Further, in one or more embodiments, the one or more previous etching processes could have diminished a thickness of the one or more hard mask layers 104, thereby necessitating the oxidizing at 1404 to replenish the thickness of the one or more hard mask layers 104 and facilitate the etching at 1408.
At 1502, the method 1500 can comprise etching a semiconductor substrate 102, wherein the etching can form one or more trenches 202 into the semiconductor substrate 102 and/or thin one or more hard mask layers 104 positioned on the semiconductor substrate 102. For example, the etching at 1502 can be performed in accordance with the second stage of the replenishment process 100 described herein. For instance, the depth of the one or more trenches 202 can depend on a thickness of the one or more hard mask layers 104. Example processes that can facilitate the etching at 1502 can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
At 1504, the method 1500 can comprise thermally oxidizing the semiconductor substrate 102 to replenish the one or more hard mask layers 104. For example, thermal oxidation at 1504 can be performed in accordance with the third, fourth, fifth, sixth, and/or seventh stage of the replenishment process 100 described herein. For instance, oxidizing the semiconductor substrate 102 can form one or more hard mask layers 104 having a thickness large enough to facilitate one or more subsequent etching processes. For example, the replenishment of the one or more hard mask layers 104 facilitated by the oxidizing at 1504 can result in the hard mask layers 104 having a thickness greater than or equal to their original thickness prior to the etching at 1502.
At 1506, the method 1500 can comprise etching the semiconductor substrate 102 to deepen the one or more trenches 202 within the semiconductor substrate 102. For example, the etching at 1506 can be performed in accordance with the ninth stage of the replenishment process 100 described herein. For instance, the oxidizing at 1504 can render one or more hard mask layers 104 thick enough to facilitate the etching at 1506. The etching at 1506 can remove oxide material from the one or more hard mask layers 104 in addition to semiconductor material from the semiconductor substrate 102; thus, a previous thickness of the one or more hard mask layers 104 (e.g., a thickness resulting from the thinning caused by the etching at 1502) can be insufficient to facilitate the etching at 1506 while properly protecting one or more select portions of the semiconductor substrate 102 (e.g., the one or more columns 204 defined by the one or more trenches 202). By replenishing the one or more hard mask layers 104 via the thermal oxidation at 1504, the method 1500 can facilitate deep etches into the semiconductor substrate 102 while minimizing the necessary thickness of the one or more hard mask layers 104. Further, by minimizing the necessary thickness of the one or more hard mask layers 104, the method 1500 can reduce various aspect ratios of the semiconductor substrate 102 during a manufacturing processes; thereby enhancing structural stability of the semiconductor substrate 102.
At 1602, the method 1600 can comprise etching a semiconductor substrate 102, wherein the etching can form one or more trenches 202 into the semiconductor substrate 102 and/or thin one or more hard mask layers 104 positioned on the semiconductor substrate 102. For example, the etching at 1602 can be performed in accordance with the second stage of the replenishment process 100 described herein. For instance, the depth of the one or more trenches 202 can depend on a thickness of the one or more hard mask layers 104. Example processes that can facilitate the etching at 1602 can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
At 1604, the method 1600 can comprise removing the one or more hard mask layers 104 from the semiconductor substrate 102. For example, removing the one or more hard mask layers 104 at 1604 can be performed in accordance with the third stage of the replenishment process 100 described herein. For instance, the one or more hard mask layers 104 can be removed from a top surface 106 of the semiconductor substrate 102 through one or more etching processes, which can include, but are not limited to: RIE, wet etching, dry etching, plasma etching, sputter etching, a combination thereof, and/or the like.
At 1606, the method 1600 can comprise forming one or more protective layers 402 within the one or more trenches 202 to define one or more exposed surfaces (e.g., a top surface 106) of the semiconductor substrate 102, wherein the one or more protective layers 402 can be more resistant to oxidation than the semiconductor substrate 102. For example, forming the one or more protective layers 402 at 1606 can be performed in accordance with fourth and/or fifth stage of the replenishment process 100 described herein. For instance, forming the one or more protective layers 402 can comprise depositing the one or more protective layers 402 onto the semiconductor substrate 102 and removing select portions of the one or more deposited protective layers 402. The one or more select portions can be located on the top surface 106 of the semiconductor substrate 102 located at the distal ends of the one or more columns 204 defined by the one or more trenches 202. Thus, the one or more protective layers 402 can be formed in the one or more trenches 202 through deposition and/or removal, wherein the absence of one or more protective layers 402 at one or more positions on the semiconductor substrate 102 can define the one or more exposed surfaces.
At 1608, the method 1600 can comprise thermally oxidizing the one or more exposed surfaces of the semiconductor substrate 102 to replenish the one or more hard mask layers 104. For example, thermal oxidation at 1608 can be performed in accordance with the sixth, and/or seventh stage of the replenishment process 100 described herein. For instance, oxidizing the semiconductor substrate 102 can form one or more hard mask layers 104 having a thickness large enough to facilitate one or more subsequent etching processes. For example, the replenishment of the one or more hard mask layers 104 facilitated by the oxidizing at 1608 can result in the hard mask layers 104 having a thickness greater than or equal to their original thickness prior to the etching at 1602. Additionally, the thermal oxidation at 1608 can be directed by the one or more protective layers 402 deposited at 1606.
At 1610, the method 1600 can comprise etching the semiconductor substrate 102 to deepen the one or more trenches 202 within the semiconductor substrate 102. For example, the etching at 1610 can be performed in accordance with the eighth stage and/or ninth stage of the replenishment process 100 described herein. For instance, the oxidizing at 1608 can render one or more hard mask layers 104 thick enough to facilitate the etching at 1610. The etching at 1610 can remove oxide material from the one or more hard mask layers 104 in addition to semiconductor material from the semiconductor substrate 102; thus, a previous thickness of the one or more hard mask layers 104 (e.g., a thickness resulting from the thinning caused by the etching at 1502) can be insufficient to facilitate the etching at 1610 while properly protecting one or more select portions of the semiconductor substrate 102 (e.g., the one or more columns 204 defined by the one or more trenches 202). By replenishing the one or more hard mask layers 104 via the thermal oxidation at 1608, the method 1600 can facilitate deep etches into the semiconductor substrate 102 while minimizing the necessary thickness of the one or more hard mask layers 104. Further, by minimizing the necessary thickness of the one or more hard mask layers 104, the method 1600 can reduce various aspect ratios of the semiconductor substrate 102 during a manufacturing processes; thereby enhancing structural stability of the semiconductor substrate 102.
One of ordinary skill in the art will recognize that the various features of the replenishment process 100 and/or the methods (e.g., method 1100, method 1200, method 1300, method 1400, method 1500, and/or method 1600) described herein can be repeated one or more times to facilitate one or more manufacturing processes of semiconductor devices. For example, the various features and/or processes described herein can be repeated to facilitate multiple etching processes while utilizing thin masking layers to minimize aspect ratios during the manufacturing process.
In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in the subject specification and annexed drawings should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms “example” and/or “exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an “example” and/or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.
It is, of course, not possible to describe every conceivable combination of components, products and/or methods for purposes of describing this disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of this disclosure are possible. Furthermore, to the extent that the terms “includes,” “has,” “possesses,” and the like are used in the detailed description, claims, appendices and drawings such terms are intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim. The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
