Patent Application
20240194561
The present invention relates to a hetero-junction bipolar transistor and a manufacturing method thereof.
An indium-phosphorus (InP)-based hetero-junction bipolar transistor (HBT) is a transistor with excellent high-speed and high-power characteristics that is suitable for integrated circuits for optical/wireless communication. In order to achieve a further increase in speed of the InP-based HBT, it is important to reduce a capacitance and shorten an electron traveling time by miniaturizing an element, while maintaining an operating current amount. In addition, in increasing the high-power characteristic, it is required to increase the number of emitters in a so-called multi-finger structure in which a plurality of emitters is integrated in a manner sharing a base or a collector and to reduce an interval between emitters.
On the other hand, since a thermal resistance of an element increases due to the miniaturization, a junction temperature of the element (an internal temperature of the element) increases due to the miniaturization. In addition, in the multi-finger structure, due to a heat generation of an emitter region disposed at an outer peripheral portion, a heat dissipation of the emitter region disposed at a center is hindered as compared with the HBT of a single finger, so that the junction temperature is further increased.
Since the junction temperature is a factor that greatly affects not only direct electrical characteristics such as current gain and high-frequency characteristics but also long-term reliability, heat dissipation measures are essential when increasing the HBT speed.
In order to improve the heat dissipation property of the HBT, a technique for forming an HBT structure on a support substrate having a high thermal conductivity, for example, has been proposed (NPL 1).
In the HBT structure in NPL 1, as shown in
This HBT structure is obtained by epitaxially growing each layer constituting the HBT on an InP growth substrate, then bonding the layer to the heat dissipation substrate 301 via the collector electrode layer 302, removing the unnecessary InP growth substrate, and processing each layer so as to form the HBT structure.
Generally, heat generated in the HBT is generally dissipated toward the substrate by heat conduction in a solid body. According to the above structure, because the layer under the collector contact layer 303 is made of a material having a higher thermal conductivity than a compound semiconductor constituting the emitter layer 306, the base layer 305, the collector layer 304, and the collector contact layer 303, the heat dissipation property of the HBT can be improved.
On the other hand, unlike a case where an HBT structure is formed on a typical InP substrate, a step of bonding the HBT structure to the heat dissipation substrate is required, and therefore, there is a concern that various problems may occur in various manufacturing methods as described later.
First, as shown in NPL 1, in order to realize the above-mentioned HBT structure on the heat dissipation substrate by one substrate bonding process, unlike the case where the HBT structure is formed on an ordinary InP substrate, an HBT crystal layer needs to be epitaxially grown in a reverse order (an order of the emitter layer, the base layer, and the collector layer from the side in contact with the InP substrate).
Usually, in epitaxial growth, an optimum temperature profile is set in consideration of the deterioration of the semiconductor crystal quality of the lower layer and the unintended thermal diffusion of constituent elements so as to obtain the best crystal quality of various materials. On the other hand, when the HBT crystal layer is epitaxially grown from the emitter layer side, the semiconductor materials of the lower layer and the upper layer are replaced with each other, so that the case where it is difficult to set the optimum temperature profile occurs.
In addition, InGaAs having a high In composition is often used for the outermost layer (layer in direct contact with the emitter electrode) of the emitter layer in order to reduce the contact resistance of the emitter. Since InGaAs having the high In composition is not lattice-matched with InP, it is generally difficult to form a high-quality crystal. However, since InGaAs having the high In composition is the outermost layer, it is not necessary to consider the crystal quality of the upper semiconductor material, and in addition, by controlling the thickness of the upper semiconductor material to be equal to or less than the critical film thickness, lattice relaxation is suppressed, thereby achieving the crystal quality capable of obtaining sufficient electrical characteristics.
However, when grown from the side of the emitter layer, the emitter layer, the base layer, and the collector layer to be lattice-unmatched are formed on InGaAs having the high In composition. Therefore, the crystal quality of the HBT crystal layer is deteriorated, or it is feared that it becomes difficult to introduce InGaAs having the high In composition into the emitter layer.
From the above, when the structure of the above-mentioned NPL 1 is realized by one substrate bonding process, there is a concern that the crystal quality of the HBT crystal layer is deteriorated or the composition is restricted.
The simplest method for solving the above problem is to carry out the substrate bonding process twice. First, after an HBT crystal growth layer is epitaxially grown, it is bonded to the support substrate by using some temporary adhesive layer, and the InP substrate is removed. In this case, the HBT crystal layers are formed on the support substrate in a state in which the order of the HBT crystal layers is reversed. Next, the HBT crystal layer on the support substrate and the heat dissipation substrate are bonded via a metal layer in the same manner as in NPL 1, and the unnecessary temporary adhesive layer and the support substrate are removed. Since the HBT crystal layer is transferred twice at this stage, the HBT crystal layer is formed on the heat dissipation substrate in the order of growth on the InP substrate. Finally, the HBT structure is produced by a known method, whereby the structure of NPL 1 can be obtained.
In this case, since the HBT crystal layer can be grown on the InP growth substrate in the normal order (in the order from the collector layer to the emitter layer), the crystal quality does not deteriorate in the epitaxial growth process. However, the substrate bonding process is simply required twice, so that not only is the process complicated but also there is a concern that the quality of the HBT crystal layer may be deteriorated in some cases.
In general, when some particle or local unevenness is generated on the surface to be bonded, it also depends on the physical properties of the material to be bonded, but there is a possibility that an unbonded region having 100 to 1,000 times or more of the size of the material to be bonded may be generated. Accordingly, as the number of bonding processes increases, the risk of occurrence of an unintended unbonded region increases, which may result in a potential reduction in yield.
Further, in the second bonding, bonding pressure is applied to the HBT crystal layer which is a thin layer (thickness of 1 μm or less) and extremely mechanically fragile and bonds the HBT crystal layer to the heat dissipation substrate. Although the HBT crystal layer is held on the support substrate by the temporary adhesive layer, there is a concern that the crystal quality is deteriorated and cracks are generated in the worst case due to the influence of minute deformation of the temporary adhesive layer due to the bonding pressure. Therefore, as an ideal temporary adhesive layer, a material easy to peel and hard to deform (high Young's modulus) is preferable, however, the high Young's modulus is a trade-off with bonding easiness, and it is not easy to select a temporary adhesive layer which satisfies all requirements in a well-balanced manner.
In order to avoid the above problem, a technique has been proposed for forming the HBT structure by a collector-up process with a single substrate bonding without changing the epitaxial growth order (NPL 2).
For example, as shown in
Further, a thermal via 410 made of Au in contact with the heat dissipation substrate 401 is formed on the extension of the emitter layer 405 in a transverse direction, and is connected to the first emitter electrode 403. Furthermore, the element part and the thermal via 410 are covered with a protective layer 411 made of BCB.
In this structure, the HBT element part including the first emitter electrode 403, the second emitter electrode 404, the emitter layer 405, the base layer 406, the collector layer 407, and the sub-collector layer 408 is formed on the InP substrate, and then is bonded to the heat dissipation substrate via the bonding layer 402.
After this bonding, the unnecessary InP growth substrate is removed to form a collector electrode 409 in the sub-collector layer 408. Finally, an opening is formed in the bonding layer 402 at the outer peripheral portion of the element part, the thermal via 410 is formed so as to be in contact with the heat dissipation substrate 401 and the first emitter electrode 403, and then the whole element part is covered with the protective layer 411.
By constituting the adhesive layer (bonding layer) of BCB having a low Young's modulus, the bonding layer can be bonded to the heat dissipation substrate under a relatively low bonding pressure condition as compared with a case where a metal is used for a material to be bonded, thereby avoiding a destruction of the HBT element part whose mechanical strength is fragile. In addition, in this structure, heat generated in the element part is dissipated toward the heat dissipation substrate through the Au thermal via, so that a higher heat dissipation property can be obtained as compared with the HBT structure on the InP substrate.
However, in the structure of NPL 2, since BCB having extremely low thermal conductivity exists just under the element part, the path from the emitter layer to the heat dissipation substrate is made to be long due to the length of the emitter electrode and the thickness of the Au thermal via. Therefore, compared with NPL 1 in which all portions immediately below the element part are made of a high thermal conductivity material, the effect of improving the heat dissipation property is limited.
Further, since the Au thermal via having a constant size is required for the heat dissipation between the HBT element part and the element part, when the multi-finger structure in which a plurality of emitters is disposed in parallel at a high density is formed, the emitter interval is restricted. This may be a serious problem particularly in increasing the high power of the HBT.
As described above, the existing technique has a problem that it is not easy to improve the heat dissipation property while suppressing the deterioration of the crystal quality and the deterioration of the integration density of the InP-based HBT.
Embodiments of the present invention were achieved in order to solve the foregoing problem, and an object of embodiments of the present invention is to further improve the heat dissipation property while suppressing the deterioration of the crystal quality and the deterioration of the integration density of the InP-based HBT.
A hetero-junction bipolar transistor according to embodiments of the present invention includes a heat dissipation substrate made of an insulating material having a thermal conductivity higher than that of InP, a first emitter electrode formed on the heat dissipation substrate, a second emitter electrode formed on the first emitter electrode with an area smaller than that of the first emitter electrode, an emitter layer made of a compound semiconductor and formed on the second emitter electrode, a base layer made of a compound semiconductor and formed on the emitter layer, a collector layer made of a compound semiconductor and formed on the base layer, a collector contact layer made of a compound semiconductor and formed on the collector layer, a collector electrode formed on the collector contact layer, a base electrode formed to be connected to the base layer, a protective layer formed on the heat dissipation substrate so as to cover a side of an element part constituted by the second emitter electrode, the emitter layer, the base layer, the collector layer, and the collector contact layer, the first emitter electrode, and the base electrode, an emitter contact electrode formed in contact with the top of the first emitter electrode around the element part and penetrating the protective layer, an emitter wiring connected to the emitter contact electrode and formed on the protective layer, a heat dissipation structure made of a metal having one end in contact with the top of the heat dissipation substrate around the element part and formed through the protective layer, a collector wiring formed on the protective layer in contact with the top of the heat dissipation structure and the collector electrode, a base contact electrode connected to the base electrode and penetrating the protective layer, and a base wiring connected to the base contact electrode and formed on the protective layer.
An manufacturing method of a hetero-junction bipolar transistor according to embodiments of the present invention is a manufacturing method for manufacturing the above mentioned hetero-junction bipolar transistor and includes a first process of performing crystal growth of an etch stop layer, a collector contact forming layer, a collector forming layer, a base forming layer, and an emitter forming layer in this order which are made of a compound semiconductor on a growth substrate made of InP, a second process of forming an element part by forming a second emitter electrode on the emitter forming layer, processing the emitter forming layer, the base forming layer, and the collector forming layer, forming the emitter layer, the base layer, and the collector layer, and forming the base electrode on the base layer around the emitter layer, a third process of forming a first structure body made of a metal on the growth substrate around the element part, a fourth process of filling a periphery of the element part and forming a first protective layer in which one end side of the first structure body and the second emitter electrode are exposed and a surface is flattened, a fifth process of forming a first adhesive metal layer on the flattened first protective layer, a sixth process of preparing a heat dissipation substrate made of an insulating material having higher thermal conductivity than that of InP and in which a second adhesive metal layer is formed on the surface, a seventh process of bringing the first adhesive metal layer of the growth substrate and the second adhesive metal layer of the heat dissipation substrate into contact with each other so as to face each other, forming an adhesive metal layer in which the first adhesive metal layer and the second adhesive metal layer are integrated, and laminating the growth substrate and the heat dissipation substrate, an eighth process of removing the growth substrate and the etch stop layer, bringing the element part into a state of being formed on the heat dissipation substrate in a state where the second emitter electrode is disposed on a side of the heat dissipation substrate, and exposing the collector contact forming layer, a ninth process of forming a collector electrode on the collector contact forming layer, a tenth process of forming a collector contact layer by processing the collector contact forming layer, and further removing a part of the collector layer and the base layer, and forming a contact hole reaching a part of the base electrode, an eleventh process of forming a first emitter contact electrode constituting a part of the emitter contact electrode and a first heat dissipation structure made of a metal and constituting a part of the heat dissipation structure, and forming the base contact electrode on the first structure body, a twelfth process of forming an emitter contact layer by processing the first structure body and forming a second emitter contact electrode connecting to the first emitter contact electrode, forming a second heat dissipation structure constituting a part of the heat dissipation structure and connected to the first heat dissipation structure, forming the first emitter electrode by processing the adhesive metal layer, and forming a third heat dissipation structure connected to the second heat dissipation structure to form the heat dissipation structure constituted by the first heat dissipation structure, the second heat dissipation structure, and the third heat dissipation structure, a thirteenth process of forming a second protective layer on the first protective layer to form a protective layer constituted by the first protective layer and the second protective layer, and a fourteenth process of forming an emitter wiring, a base wiring, and a collector wiring.
As described above, according to embodiments of the present invention, since the protective layer covering the element part or the like is formed on the heat dissipation substrate, and the heat dissipation structure is provided which is made of metal and has one end in contact with a top of the heat dissipation substrate around the element part so as to penetrate the protective layer, it is possible to suppress the deterioration of the crystal quality and the deterioration of the integration density of the InP-based HBT to improve the heat dissipation property.
Hereinafter, a hetero-junction bipolar transistor according to an embodiment of the present invention will be described with reference to
The hetero-junction bipolar transistor includes a heat dissipation substrate 101 made of an insulating material having a thermal conductivity higher than that of InP, a first emitter electrode 102 formed on the heat dissipation substrate 101, and a second emitter electrode 103 formed on the first emitter electrode 102 with an area smaller than that of the first emitter electrode 102.
In addition, this hetero-junction bipolar transistor includes an emitter layer 104 formed on the second emitter electrode 103, a base layer 105 formed on the emitter layer 104, a collector layer 106 formed on the base layer 105, and a collector contact layer 107 formed on the collector layer 106. These layers (crystal layers) are made of a compound semiconductor (for example, a group III-V compound semiconductor).
In addition, this hetero-junction bipolar transistor includes a collector electrode 108 formed on a collector contact layer 107, and a base electrode 109 formed so as to be connected to the base layer 105. Further, this hetero-junction bipolar transistor includes a protective layer 110 formed on the heat dissipation substrate 101 so as to cover the side of the element part, the first emitter electrode 102, and the base electrode 109. The element part is a part including the second emitter electrode 103, the emitter layer 104, the base layer 105, the collector layer 106, and the collector contact layer 107.
In addition, this hetero-junction bipolar transistor is formed on the first emitter electrode 102 around the element part and includes an emitter contact electrode 112 penetrating the protective layer 110, and an emitter wiring 113 connected to the emitter contact electrode 112 and formed on the protective layer 110.
In addition, this hetero-junction bipolar transistor includes a heat dissipation structure 114 made of metal whose one end is in contact with the heat dissipation substrate 101 around the element part, and which is formed so as to penetrate the protective layer 11o. The heat dissipation structure 114 is formed in the shape of a pillar.
Also, this hetero-junction bipolar transistor includes a collector wiring 115 formed on the protective layer 110 in contact with the heat dissipation structure 114 and the collector electrode 108, a base contact electrode 116 connected to the base electrode 109 and penetrating the protective layer 110, and a base wiring 117 connected to the base contact electrode 116 and formed on the protective layer 110.
Further, this hetero-junction bipolar transistor is made of an insulating material having a thermal conductivity higher than that of the collector layer 106 and the emitter layer 104, and includes an insulating layer 118 formed on the peripheral surface of the element part.
Here, in this example, a plurality of element parts is provided on the first emitter electrode 102, each of the plurality of element parts is formed in a rectangular shape in a plan view, and the plurality of rectangular cells is disposed in the direction of short sides (short sides) of the rectangular cells. This is a so-called multi-finger structure. In the embodiment, a plurality of emitter layers 104 (second emitter electrodes 103) and collector layers 106 (collector contact layers 107 and collector electrodes 108) are provided. Note that
In addition, in the plurality of element parts, the collector layer 106 is formed to have an area larger than that of the emitter layer 104. Further, in each element part, the collector layer 106 and the emitter layer 104 are in a state where their centers overlap each other in a plan view. In the process of the current flowing from the emitter layer 104 to the collector layer 106, the current spreads after exiting the emitter layer 104, so that the collector layer 106 is formed to have a larger area.
According to the embodiment, heat generated in the element part is dissipated to the heat dissipation substrate 101 via the second emitter electrode 103 and the first emitter electrode 102. In addition, heat is dissipated to the heat dissipation substrate 101 from the collector layer 106 side via the collector electrode 108 made of a metal having high thermal conductivity, the collector wiring 115, and the heat dissipation structure 114. As a result, according to the embodiment, the heat dissipation property of the heat generated in the element part can be improved as compared with the conventional structure.
Further, as will be described later, since the layers of the respective crystals constituting the element part are formed by epitaxial growth in the same order of lamination as that of the conventional hetero-junction bipolar transistor, the deterioration of the crystal quality can be avoided.
In addition, the junction process necessary for manufacturing the hetero-junction bipolar transistor according to the embodiment in which the element part (the second emitter electrode 103, the emitter layer 104, the base layer 105, the collector layer 106, the layer to be used as the collector contact layer 107, and the base electrode 109) is formed, and then is bonded to the heat dissipation substrate only once. Therefore, as compared with the case where substrate bonding is performed twice, the deterioration of the crystal quality and the yield caused by the bonding process can be suppressed.
Further, as will be described later, in the manufacture of the hetero-junction bipolar transistor according to the embodiment, the element part and the heat dissipation substrate are bonded via an adhesive metal layer made of Au or Cu having a high thermal conductivity. In this case, a relatively high bonding pressure is required because of its high Young's modulus compared to the case of bonding by a resin layer such as benzocyclobutene (BCB). However, according to the embodiment, since a metal structure for constituting the emitter contact electrode 112 and the heat dissipation structure 114 is formed around the element part, local concentration of a bonding load to a crystal layer constituting the element part through the second emitter electrode 103 is suppressed, thus, they can be prevented from being destroyed in the bonding process.
Further, in the hetero-junction bipolar transistor according to the embodiment, since heat can be dissipated from the first emitter electrode 102 toward the heat dissipation substrate 101 immediately below, there is no need to diffuse the heat in the emitter short direction as in the case of NPL 2. Accordingly, according to the embodiment, as long as the accuracy of the processing technique allows, the emitter layer 104 and the second emitter electrode 103 are disposed in parallel with each other at high density without sacrificing the heat dissipation property, and a so-called multi-finger structure can be formed. Thus, the hetero-junction bipolar transistor which achieves both high heat dissipation property and high-power performance can be obtained.
Further, since the hetero-junction bipolar transistor according to the embodiment has a collector-up structure, only the area of the collector layer 106 can be relatively easily processed to be selectively smaller than that of the base layer 105. Thus, since collector parasitic capacitance can be reduced without reducing the contact area between the base electrode 109 and the base layer 105 (without increasing the base contact resistance), high-frequency characteristics can be improved.
As described above, according to the present embodiment, it is possible to improve the heat dissipation property by suppressing the deterioration of the crystal quality and the deterioration of the integration density of the InP-based HBT. Further, according to the embodiment, the HBT having the multi-finger structure with the high heat dissipation property can be formed by one bonding process, and an excellent effect can be obtained in which high speed and high-power performance can be improved and long-term reliability can be improved.
Next, a manufacturing method of the hetero-junction bipolar transistor according to an embodiment of the present invention will be described with reference to
First, as shown in
For example, the etch stop layer 122 can be formed of a laminated structure of a non-doped InGaAs layer and a non-doped InP layer. The collector contact forming layer 127 can be made of n-type InGaAs doped with Si at a high concentration. The collector forming layer 126 can be made of n-type InP doped with Si at a low concentration. The base forming layer 125 can be made of P-type GaAsSb doped with C at a high concentration. The emitter forming layer 124 can be made of n-type InP doped with Si at a low concentration.
Each layer of the group III-V compound semiconductor described above can be formed by crystal (epitaxial) growth using, for example, an organic metal vapor deposition method or a molecular beam epitaxy method. Since each of the above-mentioned crystal layers can be epitaxially grown on the growth substrate 121 made of InP in a lattice-matched state, good crystallinity with less transformation and defects can be obtained. Further, although not shown, by forming an emitter cap forming layer of InGaAs of a high In composition having a thickness equal to or less than a critical film thickness on the emitter forming layer 124, it is possible to reduce the contact resistance with the emitter electrode.
Next, as shown in
Note that the parallel number of the second emitter electrodes 103 and the emitter layers 104 can be appropriately selected in accordance with the amount of output current required in the integrated circuit. The respective layers and the electrodes can be formed by using well-known semiconductor patterning techniques, film forming and etching techniques, and the like. The base electrode 109 forms a portion which becomes a so-called base pad electrode in one of the emitter longitudinal directions and whose width is wider than that of the other. This is used to facilitate the connection with the base wiring, as will be described later.
Next, as shown in
Further, since the interval between the first structure body 131 and the element part influences the area occupied by the final HBT and the parasitic capacitance, the optimum interval is set in a view of the process accuracy and the electrical characteristics.
In addition, the thickness (height) of the first structure body 131 is made equal to the sum of the thicknesses of the second emitter electrode 103, the emitter layer 104, the base layer 105, and the collector layer 106. Thus, as will be described later, the bonding pressure applied when bonding the growth substrate 121 and the heat dissipation substrate 101 is uniformly applied to the second emitter electrode 103 and the first structure body 131, and the deterioration of the crystal quality and the crack of the element part due to excessive pressure concentration can be suppressed.
Next, as shown in
As will be described later, the first insulating layer 132 serves to assist heat conduction of the element part and to protect the element part from an etchant when the first structure body 131 is etched to form a part of the heat dissipation structure. Therefore, it is desirable that the material of the first insulating layer 132 is made of a silicon nitride film (SiN) or alumina (Al2O3) having relatively high thermal conductivity and high chemical stability. The first insulating layer 132 made of these materials can be formed by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). Since the thickness of the first insulating layer 132 depends on the size and film quality of the element part, the thickness for obtaining the above-mentioned effect is appropriately set. Typically, the first insulating layer 132 has a thickness of about 10 nm to 100 nm, which is sufficient to obtain the above effect.
Next, as shown in
For example, benzocyclobutene (BCB) is applied to the entire surface of the growth substrate 121 to form a coating film, and after the upper surface of the coating film is flattened, the coating film is etched back. In the etch-back process, the first insulating layer 132 on the second emitter electrode 103 and the first structure body 131 is removed together with a part of the coating film by a dry etching method. At this time, when the dry etching time is lengthened in order to surely expose the surface of the second emitter electrode 103, the height of a formation region of the first protective layer 133 on the element part becomes low, and there is a situation in which a region where the first protective layer 133 is formed is not bonded to the heat dissipation substrate 101.
Also in this state, the effect of embodiments of the present invention can be obtained. However, by using chemical mechanical polishing as a substitute for dry etching, for example, the surface of the second emitter electrode 103 and the surface of the first protective layer 133 are flattened so as to become in a state in which heights of the surface of the second emitter electrode 103 and the surface of the first protective layer 133 are aligned (the surface of the second emitter electrode 103 and the surface of the first protective layer 133 form the same plane), and the occurrence of the non-bonded region can be suppressed.
Next, as shown in
For example, the first adhesive metal layer 134 and the second adhesive metal layer 135 can be made of Au or Cu. Further, in order to improve adhesion with a first protective layer 133 made of a resin such as BCB and to suppress thermal diffusion of Au and Cu to the element part, a layer made of Ti, Mo, Ni, W, or these compounds can be inserted between the first protective layer 133 and the first adhesive metal layer 134.
The thicknesses of the first adhesive metal layer 134 and the second adhesive metal layer 135 can be set in view of the easiness of processing and the electric resistance in forming the first emitter electrode 102, as will be described later. Typically, these thicknesses do not affect the processability and provide a sufficiently low electric resistance, provided as long as they are from 100 nm to 500 nm.
Next, as shown in
If the outermost surfaces of the first adhesive metal layer 134 and the second adhesive metal layer 135, which are the contact surfaces, are made of Au, they can be bonded at a temperature of 150° C. or lower in any bonding technique. This temperature does not affect the crystallinity of the element part. In bonding, a bonding pressure may be applied to correct warpage and global roughness of each substrate. This bonding pressure is dispersed not only in a region where the second emitter electrode 103 is formed but also in a region where the first structure body 131 is formed. Therefore, pressure is not locally concentrated on the second emitter electrode 103, and the risk of occurrence of deterioration of the crystal quality and cracks of the crystal layer constituting the element part immediately below the second emitter electrode 103 can be reduced.
Next, the growth substrate 121 and the etch stop layer 122 are removed, as shown in
The growth substrate 121 can be removed, for example, by known mechanical polishing. In addition, the removal of the growth substrate 121 can be performed, by utilizing well-known wet etching using a hydrochloric acid-based chemical. Further, the etch stop layer 122 may be removed by known wet etching. By using the etch stop layer 122, the growth substrate 121 can be reliably removed, and damage to the collector contact forming layer 127 can be avoided when the growth substrate 121 is removed.
Next, as shown in
The same number of collector electrodes 108 as the number of emitter layers 104 are formed in parallel so as to coincide with the central axis of each of the plurality of formed emitter layers 104. The width of each collector electrode 108 (length in the short side direction in a plan view) is wider than the width of each emitter layer 104, and each (adjacent) collector electrode 108 can be designed not to contact. In addition, the length of the collector electrode 108 (length in the long side direction in a plan view) can be designed at least within a range not reaching directly above the first structure body 131.
Next, as shown in
For example, the collector contact forming layer 127 made of InGaAs can be etched using a citric acid-based etchant. By using this etching, the collector contact layer 107 can be formed. In addition, the base layer 105 made of GaAsSb can be etched using the citric acid-based etchant, and the collector layer 106 made of InP can be etched using a hydrochloric acid-based etchant. By using this etching, the contact hole 116a can be formed.
Further, the collector contact layer 107 and the collector layer 106 are additionally etched to divide the collector contact layer 107 and the collector layer 106 as shown in
Next, as shown in
The first emitter contact electrode 136 is formed on the first structure body 131 on both sides of the element part in the short side direction in a plan view (
Next, as shown in
In the formation of the first emitter electrode 102 and the third heat dissipation structure 140, the adhesive metal layer outside the element forming region is completely removed. In addition, in the formation of the second emitter contact electrode 138 and the second heat dissipation structure 139, the first structure body 131 outside the element forming region is completely removed. Note that
For example, a region where the second emitter contact electrode 138, the second heat dissipation structure 139, and the first emitter electrode 102 is formed, and a top of the base contact electrode 116 are covered with a resist mask, and in this state, the first structure body 131 and the adhesive metal layer are wet-etched using an appropriate etchant, thereby forming each portion. When the adhesive metal layer and the first structure body 131 are made of Au, wet etching can be performed by using an iodine-based etchant, for example. In this etching, the first insulating layer 132 prevents an etchant from contacting the element part, and can prevent unintended etching from occurring in the element part.
Next, as shown in
Next, as shown in
For example, BCB is applied to the entire surface to form a coating film, and after the upper surface of the coating film is flattened, the coating film is etched back. In etch-back, the dry etching method is used, and the collector electrode 108, the emitter contact electrode 112, the base contact electrode 116, and the second insulating layer 141 on the heat dissipation structure 114 are removed together with a part of the coating film, and the second protective layer 142 is formed in a state where the upper surface of each part is exposed.
Thereafter, an emitter wiring 113, a base wiring 117, and a collector wiring 115 are formed (fourteenth step), whereby the hetero-junction bipolar transistor according to the embodiment is obtained.
In the above-described manufacturing method, an example in which laminating of the growth substrate 121 and the heat dissipation substrate 101 is carried out by bonding via an adhesive metal layer is shown, but the embodiments of the present invention are not limited to this, the same structure can be formed without impairing the effect of embodiments of the present invention by another laminating technique (bonding technique).
For example, after the element part is formed as described with reference to
Also, by this method, since both substrates are bonded with their surfaces flattened, local application of bonding pressure to the second emitter electrode can be prevented, and deterioration of crystallinity of the element part can be suppressed.
Note that although an npn-type InP/GaAsSb-based HBT on a heat dissipation substrate that is promising in terms of realizing a very high-speed integrated circuit is described in detail in the above, a similar effect is also valid for other HBTs.
As described above, according to embodiments of the present invention, since the protective layer covering the element part or the like is formed on the heat dissipation substrate, and the heat dissipation structure is provided which is made of metal and has one end in contact with the top of the heat dissipation substrate around the element part and formed through the protective layer, it is possible to suppress the deterioration of crystal quality and the deterioration of integration density of the InP-based HBT to improve the heat dissipation property.
Note that it is clear that the embodiments of the present invention are not limited to the embodiments described above and within the technical concept of the present invention, many modifications and combinations can be implemented by those skilled in the art.
This application is a national phase entry of PCT Application No. PCT/JP2021/018000, filed on May 12, 2021, which application is hereby incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/018000 | 5/12/2021 | WO |
