The present disclosure generally relates to fabrication methods and structures for semiconductor devices, and more specifically, to techniques for forming high density backside capacitors and inductors of a semiconductor device.
Advances in semiconductor IC (integrated circuit) chip fabrication and packaging technologies have enabled development of highly integrated semiconductor IC chips and compact chip package structures (or electronic modules). Passive components such as capacitors, resistors and inductors are fundamental circuit components that are commonly used in chip fabrication/packaging designs.
Capacitors are fundamental components for constructing semiconductor integrated circuits including, for example, memory arrays, charge pumps, RC filters, peaking amplifiers and various types of analog integrated circuits. In conventional designs, capacitors are implemented as discrete, off-chip components that are mounted inside a chip package module or on an electrical board (e.g., printed circuit board) on which a chip is mounted. Continuing advances in semiconductor IC chip fabrication and packaging technologies, however, has allowed for the development of high-performance IC chips and chip package structures with increasingly higher levels of integration density, and lower fabrication costs. In this regard, IC chip and package designs utilize on-chip capacitors, for example, to reduce chip package cost and to reduce module size. Moreover, the use of on-chip capacitors, for example, allows for higher performance designs as on-chip capacitors are more effective in reducing noise in power and ground lines when placed closer to the relevant loads.
Inductors are typically used in analog and mixed signal chip designs for constructing various circuits such as voltage controlled oscillators (VCOs), low-noise amplifiers (LNAs), mixers, filters and other integrated circuits. Passive components such as inductors can be fabricated as off-chip or on-chip components. By way of example, inductor components can be fabricated as off-chip components as part of a chip package or disposed at some other location (e.g., printed circuit board). In such off-chip designs, the inductors can be connected to on-chip integrated circuits through C4 contacts or other chip-package contacts such as wire bonds, etc, which can significantly increase the series resistance and degrade circuit performance. Moreover, off-chip designs may not be suitable for high-density integration designs.
Another conventional method for implementing inductors as circuit elements includes constructing inductors as part of the frontside integrated circuit. For instance, on-chip inductors can be fabricated as part of the BEOL (back-end-of-line) wiring structure, which provides interconnects between frontside integrated circuit components. The inductor coils can be patterned in the wiring metallization levels, or patterned in metallization levels that are specifically designed for inductors.
According to one embodiment of the present invention, a method includes forming one or more backside metal (BSM) stacks in one or more layers of dielectric material. The one or more BSM stacks are in contact with one or more backside electrical contacts located on a backside of a semiconductor substrate, and the one or more backside electrical contacts are in contact with one or more source/drain regions of a first device located on a front side of the semiconductor substrate. The method further includes forming an inductor that is integrated with a first BSM stack of the one or more BSM stacks. Forming the inductor includes: depositing one or more additional layers of dielectric material on top of the one or more BSM stacks, forming a plurality of inductor via and line openings in the one or more additional layers of dielectric material; and depositing a first conductive metal material in the plurality of inductor via and line openings.
According to another embodiment of the present invention, a semiconductor device includes a first device located on a frontside of a semiconductor substrate. The semiconductor device further includes an inductor located on a backside of the semiconductor substrate and integrated with a first backside metal (BSM) stack. The semiconductor device further includes a first electrical contact located between the frontside and the backside of the semiconductor substrate. A first end of the first electrical contact is connected to the first BSM stack and a second end of the first electrical contact is connected to a first source/drain region of the first device.
According to another embodiment of the present invention, a semiconductor device includes a device located on a frontside of a semiconductor substrate. The semiconductor device further includes a capacitor located on a backside of the semiconductor substrate and integrated with a backside metal (BSM) stack. The semiconductor device further includes a first electrical contact located between the frontside and the backside of the semiconductor substrate. A first end of the first electrical contact is connected to the BSM stack and a second end of the first electrical contact is connected to a source/drain region of the device.
Embodiments of the present invention recognize that depending on the particular application, the use of on-chip capacitors and inductors can be problematic. Capacitors and inductors integrated in current back-end-of-the-line (BEOL) designs occupy a lot of area, making the BEOL wiring very challenging. For example, with high-density chip designs, there can be limited space during the BEOL process for building the integrated capacitors, resulting in practical limitations in integration density. Similarly, the need for inductor wires to be spaced sufficiently apart to minimize self-capacitance results in the fabrication of an inductor structure during the BEOL process with a relatively large footprint.
Accordingly, embodiments of the present invention provide for a semiconductor device having capacitors and inductors located on the backside of the chip by integrating the capacitors and inductors with the back side power delivery network (BSPDN). This ultimately results in a significant decrease in the footprint of on-chip capacitors and inductors without reducing their size, thereby maintaining the necessary performance requirements of these passive elements. Further, depending on the particular circuit needs, capacitors and inductors can be placed both on the frontside and backside of the chip to meet the necessary performance requirements of these passive elements.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it is to be understood that embodiments of the invention may be practiced without these specific details. As such, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
As described below, in conjunction with
For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is focused on the distinctive features or elements of various embodiments of the present invention.
As used herein, terms such as “depositing,” “forming,” and the like may refer to the disposition of layers, or portions of materials, in accordance with a given embodiment. Such processes may or may not be different than those used in the standard practice of the art of microcooler device fabrication. Such processes include, but are not limited to, atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), limited reaction processing CVD (LRPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition, sputtering, plating, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination of those methods.
As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure and/or composition of one or more layers of material or portions of materials in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, exposure to a specific frequency or range of frequencies of electromagnetic radiation, ion implantation techniques, and/or chemical/mechanical polishing (CMP). As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure of one or more layers of material, or portions of material(s), by removal of a quantity of material, in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, micromachining, microetching, wet and/or dry etching processes, plasma etching processes, or any of the known etching processes in which material is removed.
Those skilled in the art understand that many different techniques may be used to add, remove, and/or alter various materials, and portions thereof, and that embodiments of the present invention may leverage combinations of such processes to produce the structures disclosed herein without deviating from the scope of the present invention.
The present invention will now be described in detail with reference to the Figures.
Referring now to
In some embodiments, the starting substrate of
The surface semicondcutor layer 120 may have a thickness in a range between less than 100 nanometers (nm) to greater than a micron. In some embodiments, the surface semiconductor layer 120 has a thickness between 10 and 300 nanometers (nm). A thickness of the BOX layer 115 may vary depending on the specific application. In some embodiments, the BOX layer 115 has a thickness between 30 and 200 nm. The thickness of the silicon substrate 110 may vary widely depending on the specific application. For example, the silicon substrate 110 may have a thickness similar to that of a typical semiconductor wafer (e.g., 100-700 microns), or the silicon substrate 110 may be thinned and mounted on another substrate.
In assembly 300 of
The Si layers 315-1, 315-2, 315-3 and SiGe layers 310-1, 310-2, 310-3 may be epitaxially grown above the sacrificial isolation layer 325 (or above the BOX layer 115). As used herein, the term “epitaxially grown” means the growth of a semiconductor (crystalline) material on a deposition surface of another semiconductor (crystalline) material, in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial growth process, chemical reactants provided by source gases, as well as system parameters, are controlled to cause the depositing atoms to arrive at the deposition surface with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface will take on a {100} orientation. In some embodiments, epitaxial growth processes are selective to forming on semiconductor surfaces, and generally do not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.
The SiGe layers 310-1, 310-2, 310-3 may have any suitable atomic percentage of Ge. For convenience and ease of understanding, SiGe layers having a relatively lesser atomic percentage of Ge (such as the SiGe layers 310-1, 310-2, 310-3) will be referred as SiGe(x). In some embodiments, the SiGe(x) layers have a Ge concentration (x) from 5 atomic percent to 50 atomic percent. In some embodiments, the SiGe(x) layers have a Ge concentration from 10 atomic percent to 40 atomic percent. In some embodiments, the SiGe(x) layers have a Ge concentration from 20 atomic percent to 30 atomic percent.
In some embodiments, the layers of the nanosheet stack 305 have a thickness less than or comparable to that of the sacrificial isolation layer 325. In some embodiments, the Si layers 315-1, 315-2, 315-3 have a thickness of 4 to 10 nm, and the SiGe(x) layers 310-1, 310-2, 310-3 have a thickness of 8 to 15 nm. In one non-limiting example, the sacrificial isolation layer 325 has a thickness of about 10 nm, the Si layers 315-1, 315-2, 315-3 have a thickness of about 6 nm, and the SiGe(x) layers 310-1, 310-2, 310-3 have a thickness of about 10 nm.
The sacrificial isolation layer 325 may be an SiGe layer with a relatively greater Ge concentration than the SiGe(x) layers 310-1, 310-2, 310-3. In some embodiments, the sacrificial isolation layer 325 may be a SiGe(x+25) layer having a Ge concentration that is at least 25 atomic percent greater than the SiGe(x) layers. In some embodiments, the nanosheet stack 305 may include one or more SiGe(x+25) layers in addition to the SiGe(x) layers. The greater Ge concentration in the SiGe(x+25) layers provides an etch selectivity greater than or equal to 30:1 relative to the lesser Ge concentration SiGe(x) layers. For example, the SiGe(x+25) layers may be selectively removed using HCl vapor etch chemistry.
In some embodiments, the nanosheet stack 305 is formed by growing epitaxy layers above the silicon substrate 100 (
In some embodiments, the nanosheet stack 305 is formed (
In assembly 400 of
After that, conformal deposition of a low-K spacer material forms the dielectric isolation layer 430 and gate spacers 420-1, 420-2. Some examples of the low-K spacer material include silicon boron carbide nitride (SiBCN), SiO, SiOC, SiOCN, and so forth. Thus, the dielectric isolation layer 430 in
In assembly 500 of
In assembly 510 of
In some embodiments, the sacrificial material 605-1, 605-2 includes a dielectric material, such as silicon dioxide, SiC, SiOC, AlOx, etc. In this case, the sacrificial material 605-1, 605-2, extends through the regions 610-1, 610-2 and the semiconductor material used to form the source/drain regions 620-1, 620-2 is deposited above and contacts the sacrificial material 605-1, 605-2. In some embodiments, the semiconductor material of the source/drain regions 620-1, 620-2 includes SiGe having a Ge concentration greater than that of the SiGe(x), such as SiGe(x+25), although other types of semiconductor materials are also contemplated.
In some embodiments, the sacrificial material 605-1, 605-2 includes a semiconductor material, such as SiGe(x+25), and a different semiconductor material is deposited in the regions 610-1, 610-2 to form semiconductor buffers 630-1, 630-2 that separate the sacrificial material 605-1, 605-2 from the semiconductor material of the source/drain regions 620-1, 620-2 when deposited. In this case, the source/drain regions 620-1, 620-2 contact the semiconductor buffers 630-1, 630-2. In some embodiments, the semiconductor buffers 630-1, 630-2 are formed of Si, although other types of semiconductor materials are also contemplated.
In some embodiments, the one or more gate materials 705-1, 705-2, 705-3 include a gate dielectric layer and a conductive gate metal. For example, the one or more gate materials 705-1, 705-2, 705-3 may form a high-k/metal gate. In some embodiments, the gate dielectric layer comprises a high-dielectric constant (high-k) material, such as hafnium oxide (HfO2), that is conformally deposited into the opening formed between the gate spacers 420-1, 420-2. Other types of high-k materials are also contemplated, and in some cases may include dopants. The high-k material thus conforms to the profile of the opening and the channel regions of the nanosheet stack 305 (depicted in
The conductive gate metal of the one or more gate materials 705-1, 705-2, 705-3 may be formed by depositing an electrically conductive material into the opening formed between the gate spacers 420-1, 420-2. The conductive gate metal may be formed of any suitable conducting material, such as a semiconductor material, a metal, a conductive metallic compound, carbon nanotubes, conductive carbon, graphene, or any suitable combinations thereof. In some cases, the conductive material may further include dopants. Conductive metal comprises work function metals such as TiN, TiAlC, TiC, etc, and optionally low resistance capping metals, such as W, Al, etc.
In some embodiments, the conductive gate metals of the gates 715-1, 715-2, 715-3 are partially recessed to form a cavity, which is then backfilled with dielectric material, such as silicon nitride (SiN), to form the gate caps 710-1, 710-2, 710-3. In alternate embodiments, the conductive gate metals extend to a top of the gate spacers 420-1, 420-2, and may be formed using a chemical-mechanical planarization (CMP) process to remove excess material from the upper surface. Accordingly, the conductive gate metal surrounds the entire circumference of the active layers of the nanosheet stack 305 (depicted in
In some embodiments, the one or more FEOL processes include depositing a dielectric material after forming the source/drain regions 620-1, 620-2, and before removing the hard mask gate cap 415 and the dummy gate material 410 of the dummy gates 405-1, 405-2, 405-3. In some embodiments, the one or more FEOL processes comprise depositing the ILD layer 720 above the gates 715-1, 715-2, 715-3 and forming one or more electrical contacts, such as electrical contact 725-1 (that is, an electrical contact located on a frontside of semiconductor 100, 110) through the ILD layer 720 to the source/drain region 620-2. The ILD layer 720 may be formed of any suitable dielectric material, such as silicon dioxide.
In some embodiments, the one or more BEOL processes include forming one or more layers 730 above the ILD layer 720. In some embodiments, the one or more layers 730 include a plurality of metal via and line layers separated by a plurality of dielectric layers. The one or more layers 730 provide interconnection between various components of the semiconductor device, e.g., connecting to the source/drain region 620-2 through the electrical contact 725-1. In some embodiments, a carrier wafer 740 is bonded to a top surface 735 of the one or more layers 730 to accommodate further handling and processing of the semiconductor device. Any suitable materials and bonding techniques for the carrier wafer 740 are contemplated and will be understood by the person of ordinary skill in the art.
In SOI-based implementations such as assembly 820 of
In assembly 900 of
In SOI-based implementations such as assembly 950 of
In either the assembly of 900 or 950, the metal contact material 910 may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Jr), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy.
As depicted in
In the exemplary fabrication process discussed below, a first BSM layer 1050-1 is formed using a standard via first dual damascene process, wherein the via openings and line openings (not depicted) of vias 1015-1, 1025-1 and lines 1020-1, 1030-1 to be formed are sequentially etched in a layer of ILD material 1010 in alignment with the electrical contacts 925-1, 925-2, and wherein the via openings and the line openings are filled with a conductive metal material 1030 in a single metal deposition process (e.g., copper electroplating) to form the first backside metal layer 1050-1. However, it is to be understood that other standard processes such as single damascene, a standard line first dual damascene process, or subtractive etch techniques may be used to form the first backside metal layer 1050-1.
The layer of ILD material 1010 is deposited onto the surface of assembly 950 of
A photoresist material (not depicted) is then deposited onto the surface of the hard mask layer. The photoresist material can be applied by any suitable techniques, including, but not limited to, coating or spin-on techniques. A photomask (not depicted) patterned with shapes defining the via openings to be formed is placed over the photoresist material, and the photomask pattern is transferred to the photoresist material using a lithographic process, which creates recesses in the uncovered regions of the photoresist material. The resulting patterned photoresist material is subsequently used to create the same pattern in the hard mask layer. Dry etch techniques (for example, an anisotropic etch process, such as reactive ion etch) may be employed to selectively remove portions of the hard mask layer to form the patterned hard mask. After formation of patterned hard mask, the photoresist material may be stripped from the patterned hard mask by ashing or other suitable processes. The resulting structure may be subjected to a wet clean.
The resulting patterned hard mask, which acts as an etch mask, is formed such that the portions of the underlying layer of ILD material 1010 corresponding to the via openings to be formed are left exposed, while the remaining portions of the underlying structure of the layer of ILD material 1010 is protected by the patterned hard mask. During patterning of the layer of ILD material 1010 using the patterned hard mask, the physically exposed portions of the layer of ILD material 1010 are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching. The etch removes the exposed portions of the layer of ILD material 1010 that are not protected by the patterned hard mask to form the via openings. The depth(s) of the via openings can be controlled using a timed etching process.
After forming the via openings, another patterned hard mask (not depicted) is formed on the exposed surface of the layer of ILD material 1010. The patterned hard mask may be formed using the same processes and materials for forming the via openings as described above. The resulting patterned hard mask, which acts as an etch mask, is formed such that the portion of the underlying structure of the layer of ILD material 1010 corresponding to the line openings to be formed is left exposed, while the remaining portions of the underlying structure of the layer of ILD material 1010 is protected by the patterned hard mask. The portions of the layer of ILD material 1010 left uncovered by the patterned hard mask are removed by an anisotropic etching process.
A metal liner (not depicted) is conformally deposited on the exposed surfaces of the patterned layer of ILD material 1010. The metal liner may include one or more thin layers of material such as, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN) manganese (Mn), manganese nitride (MnN) or other liner materials (or combinations of liner materials) such as RuTaN, Ta/TaN, CoWP, NiMoP, or NiMoB which are suitable for the given application. The thin metal liner serves as a barrier diffusion layer and adhesion layer. A conformal layer of the metal liner may be deposited using known techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating. The thickness of the metal liner may vary depending on the deposition process used, as well as the material employed. In some embodiments, the metal liner may have a thickness from 2 nm to 50 nm. However, other thicknesses that are less than 2 nm, or greater than 50 nm can also be employed in embodiments of the present invention, as long as the metal liner does not entirely fill the via and line openings.
In some embodiments, an optional plating seed layer (not depicted) can be formed on the metal liner as well. The optional plating seed layer is employed to selectively promote subsequent electroplating of a pre-selected conductive metal or metal alloy. The optional plating seed layer may be composed of Cu, a Cu alloy, Jr, an Jr alloy, Ru, a Ru alloy (e.g., TaRu alloy) or any other suitable noble metal or noble metal alloy having a low metal-plating overpotential. Typically, a Cu or Cu alloy plating seed layer is employed when a Cu metal is to be subsequently formed within the via and line openings. The optional plating seed layer can be formed by a conventional deposition process including, for example, CVD, PECVD, ALD, or PVD. The thickness of the optional plating seed layer may vary depending on the material of the optional plating seed layer, as well as the technique used in forming the same. Typically, the optional plating seed layer may have a thickness from 2 nm to 80 nm. However, other thicknesses that are less than 2 nm, or greater than 80 nm can also be employed in embodiments of the present invention, as long as the optional plating seed layer does not entirely fill the via and line openings.
The via and line openings are filled with the conductive metal material 1030 until the conductive metal material 1030 is at least substantially coplanar with the bottom surface of the layer of ILD material 1010. In an embodiment, the conductive metal material 1030 may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Jr), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy. In those embodiments in which a thin conformal copper (Cu) seed layer (not depicted) is deposited over the surface of the metal liner using, for example, PVD, the metal material 1030 is subsequently formed by electroplating of Cu to fill the via and line openings. In those embodiments in which the metal liner is not used, the conductive metal material 1030 is deposited directly onto the exposed surfaces of the patterned layer of ILD material 1010. The conductive metal material 1030 can be formed utilizing a deposition process such as, for example, CVD, PECVD, sputtering, chemical solution deposition or plating.
In an embodiment, the conductive metal material 1030 is formed within and filling the via and line openings by depositing the conductive metal material 1030, followed by a thermal annealing. For example, the thermal annealing can be a furnace anneal, rapid thermal anneal, flash anneal, or laser anneal. In an embodiment, for furnace anneal and rapid thermal anneal, the annealing temperature can range from 150° C. to 450° C. for furnace anneal and rapid thermal anneal and the anneal duration can range from 10 minutes to one hour. In an embodiment, for flash anneal/laser anneal, the annealing temperature can be higher (e.g., from 450° C. to 1000° C.), but the anneal duration is much shorter (e.g., ranging from 100 nanoseconds to 100 milliseconds).
A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of the metal liner, the optional plating seed layer (not depicted), and the conductive metal material 1030 (collectively referred to as “overburden material”) that is present below the bottom surface of the layer of ILD material 1010 to form the vias 1015-1, 1025-1 and the lines 1020-1, 1030-1, respectively. The planarization stops at the bottom surface of the layer of ILD material 1010, such that the metal liner, the optional plating seed layer (not depicted), and the conductive metal material 1030 are substantially coplanar with the bottom surface of the layer of ILD material 1010.
For simplicity sake, only the formation of the first BSM layer 1050-1 has been described. However, it should be understood that the formation of any number of additional BSM layers (e.g., the BSM layers 1050-2, 1050-3, including the vias 1015-2, 1015,3, and 1025-2, 1025-3, and the lines 1020-2, 1020-3 and 1030-2, 1030-3) as depicted in
As further depicted in
In assembly 1100 of
After the via opening is formed, another patterned hard mask (not depicted) is formed on the exposed surface of the layer of ILD material 1010 such that the portion of the underlying layer of ILD material 1010 corresponding to the line opening to be formed is left exposed, while the remaining portions of the underlying layer of the ILD material 1010 are protected by the patterned hard mask. The portions of the layer of the ILD material 1010 left uncovered by the patterned hard mask is similarly removed by an anisotropic etching process.
A metal liner (not depicted) is conformally deposited on the exposed surfaces of the patterned layer of ILD material 1010, followed by the deposition of the conductive metal material 1030 on the exposed surfaces of the metal liner until the via and line openings are filled with the conductive metal material 1030. The metal liner can be formed using the same processes and materials as described above with reference to the metal liner of
A planarization process may subsequently be performed to remove portions of the metal liner and the conductive metal material 1030 (collectively referred to as “overburden material”) that is present below the bottom surface of the layer of ILD material 1010 to form the via 1015-4 and the line 1120-1.
For simplicity sake, only the formation of a first inductor layer has been described. However, it should be understood that the formation of any number of additional inductor layers, including the vias 1115-1, 1115-2, 1115-3 and the lines 1120-2, 1120-3, 1120-4 as depicted in
As further depicted by assembly 1100 of
In the exemplary FEOL fabrication processes discussed below with respect to assembly 1200 of
In assembly of 1200 of
After the via opening is formed, another patterned hard mask (not depicted) is formed on the exposed surface of the layer of ILD material 1010 such that the portion of the underlying layer of ILD material 1010 corresponding to the line opening to be formed is left exposed, while the remaining portions of the underlying layer of the ILD material 1010 are protected by the patterned hard mask. The portions of the layer of the ILD material 1010 left uncovered by the patterned hard mask is similarly removed by an anisotropic etching process.
The conductive metal material 1030 is then deposited on the exposed surfaces of the patterned layer(s) of the ILD material 1010 until the via opening is filled with the conductive metal material 1030, thereby forming the via 1025-4. Then the conductive metal material 1210 is conformally deposited on the exposed surfaces of the patterned layer(s) of the ILD material 1010 and the via 1025-4 to form the first capacitor electrode 1220, followed by the conformal deposition of the dielectric isolation layer 1230, and then another conformal deposition of the conductive metal material 1210 on the exposed surfaces of the dielectric isolation layer 1230 (collectively referred to as “overburden material”) that is present below the bottom surface of the layer(s) of the ILD material 1010 to form the second capacitor electrode 1240.
The metal material 1210 can be deposited using the same processes and materials as described above with reference to the conductive metal material 1030 of
Following the formation of the inductor 1160 and the capacitor 1250, additional BSM layers may be formed depending on the particular requirements of the semicondcutor. For example, via 1025-5 may additionally be formed using any generally known damascene processes to connect the capacitor 1250 to one or more additional BSM layers.
In assembly 1300, the capacitor 1250 may be formed utilizing the same processes and materials as described with reference to
Following the formation of the capacitor 1250 and the inductor 1360, additional BSM layers may be formed depending on the particular requirements of the semiconductor. For example, vias 1025-7, 1025-8 may additionally be formed using any generally known damascene processes to connect the capacitor 1250 and the inductor 1360 to one or more additional BSM layers.
The method optionally begins at block 1402, where a multi-layer stack is arranged above a semiconductor substrate. In some embodiments, the multi-layer stack comprises a nanosheet stack arranged above a dielectric isolation layer. In some embodiments, the nanosheet stack comprises an alternating arrangement of Si layers and SiGe layers. In some embodiments (e.g., as shown in
At block 1404, a plurality of dummy gates are formed above active channels. At block 1406, one or more contact placeholders are formed between the plurality of dummy gates. In some embodiments, forming the one or more contact placeholders comprises (at block 1408) forming one or more line openings between the plurality of dummy gates, (at block 1410) depositing sacrificial material in the one or more line openings, and (optionally, at block 1412) depositing a semiconductor buffer above the sacrificial material. In some embodiments, each of the dummy gates comprises gate material between gate spacers, and forming the one or more trenches comprises etching through the nanosheet stack between gate spacers of respective dummy gates.
At block 1414, one or more source/drain regions (epitaxy) are formed above the contact placeholders. For example, semiconductor material may be deposited in the one or more line openings to form the one or more source/drain regions. At block 1416, one or more additional front end of line (FEOL) processes are performed, and one or more back end of line (BEOL) processes are performed to the semiconductor device.
At block 1418, a carrier wafer is bonded to a top surface defined by the one or more BEOL processes. At block 1420, the carrier wafer is inverted. At block 1422, the bottom surface of the one or more source/drain regions are exposed (e.g., removing the contact placeholder(s)). At block 1424, one or more self-aligned backside electrical contacts are formed. In some embodiments, forming the one or more self-aligned backside electrical contacts comprises (at block 1426) removing sacrificial material from the one or more contact placeholders, and (at block 1428) filling the trenches resulting from the removal of the sacrificial material with a backside contact metallization material to form the one or more backside electrical contacts.
At block 1430, one or more backside metal (BSM) stacks that are connected to the one or more electrical contacts is formed. In some embodiments, forming the one or more BSM stacks comprises (at block 1432) forming one or more via and line openings in one or more layers of an interlayer dielectric (ILD) material, optionally depositing (at block 1434) a metal liner material in the one or more via and line openings, depositing (at block 1436) a conductive metal material in the via and line openings to form one or more vias and lines. In some embodiments, the one or more BSM stacks are in vertical alignment with, and connected to one or more source/drain regions through one or more electrical contacts.
In some embodiments, the method proceeds from block 1436 to path
“A” of
In some embodiments, at block 1446, a capacitor that is parallel to the inductor and connected to a second BSM stack is formed. In some embodiments, forming the capacitor that is parallel to the inductor comprises (at block 1448) forming a line opening in one or more layers of an interlayer dielectric (ILD) material above the second BSM stack, depositing (at block 1450) a conductive metal material to form a first capacitor electrode, conformally depositing (at block 1452) a dielectric isolation layer on the first capacitor electrode, and depositing (at block 1454) the conductive metal material on the dielectric isolation layer to form a second capacitor electrode.
In other embodiments, the method proceeds from block 1436 to path “B” of
At block 1470, an inductor is formed in series with the capacitor. In some embodiments, forming the inductor comprises (at block 1472) depositing one or more additional layers of an interlayer dielectric (ILD) material on top of the capacitor, forming (at block 1474) one or more inductor via and line openings in the one or more layers of the ILD material above the capacitor, and depositing (at block 1476) a conductive metal material in the inductor via and line openings. In some embodiments, the inductor is in vertical alignment with, and connected to, a source/drain region through the capacitor, the first BSM stack, and the first electrical contact.
It should be appreciated that although the method steps 1460-1476 describe an inductor formed above a capacitor in series with one another, alternative method steps may similarly be applied to a capacitor formed above an inductor in series with one another.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the aspects, features, embodiments and advantages discussed herein are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.