HIGH DENSITY, HIGH FREQUENCY MEMORY CHIP MODULES HAVING THERMAL MANAGEMENT STRUCTURES

Abstract

The present invention features an ultra high density, high frequency, three-dimensional electronic circuit package suitable for constructing high capacity, high speed computer memory cards and the like. A demountable contact system allows easy test and/or burn-in. A memory card has a number of electrical receptacles adapted to receive a daughter card. The daughter card has memory devices attached to it and a corresponding number of electrical connectors placed along at least one edge, adapted to detachably mate with the electrical receptacles of the memory card. The demountable connectors allow easy rework of the package before optional, permanent solder attach. Bare dies or thin packages are mounted onto daughter cards, which in turn are mounted onto either a motherboard or memory card using pin/hole technology.

Description

FIELD OF THE INVENTION

[0002] The present invention relates to high density electronic memory components and packages and, more particularly, to an ultra high density memory package featuring demountable memory chip carriers and integrated thermal management features.

BACKGROUND OF THE INVENTION

[0003] In semiconductor devices, operating efficiency is one of the ultimate benchmarks of performance. Electrical signals are switched on and off relative to a particular voltage level within these devices, resulting in patterns which are considered “data”. One measure of operating efficiency is the voltage required to operate the semiconductor device, because electrical power is proportional to the square of the voltage.

[0004] Another benchmark of performance for semiconductor devices is operating speed. In other words, performance gains may be achieved by operating switching devices at increased switching speed, generally referred to as clock rate (i.e., the speed of switching of the electrical signal by which other signals are synchronized). Clock rates, in turn, are dependent on semiconductor fabrication processing techniques. Moreover, increased clock rates generally also result in increased operating temperatures due to the physics of electron motion.

[0005] At high clock speeds, signal integrity may be affected largely by the electric noise, due mostly to inductive and capacitive coupling effects that lead to signal reflection, distortion and delay. Inductance and capacitance may be controlled by suitably located ground planes. For example, a stripline configuration or a pin grid array (PGA) connector with grounded pins around the signal pin can be used. More specifically, to reduce signal reflection, the impedance along the signal path must be matched (e.g., to 28 ohms) as is the present practice in most sophisticated circuits on printed circuit boards (PCBs). Also, to control the signal delay, signal path lengths should be matched so that signals to different memory chips arrive in phase (at the same time).

[0006] In the area of electronic packaging, high speed semiconductor devices are interconnected one to another by the shortest possible signal path to minimize signal delays and thereby increase overall system performance. Such is the case with memory devices placed near one or more processing or logic units (processors or CPUs).

[0007] The amount of memory available to a processor is limited practically, however, by the capacity of the memory device and the density with which multiple memory devices can be stacked together in close proximity to the processor. By increasing both clock frequency and stacking density of the memory chips, system performance may be improved (i.e., speed increased), but with the aforementioned, detrimental result: more heat is generated and signal integrity becomes a concern. The heat problem, as well as the noise problem, are exacerbated by the fact that the heat-generating devices are now packaged in relatively smaller confines.

[0008] Therefore, it is the goal of high performance package designs to maximize packing density while providing effective thermal management and maintaining signal integrity. Widely accepted practices for practically achieving these goals are to miniaturize package sizes and thicknesses or profiles. Commonly used forms include thin, small-outline packages (TSOPs), chip-scale packages (CSPs), and chip-on-board (COB) structures. Decreasing package size allows for both shorter signal lengths as well as shorter thermal paths. The chip packages are generally mounted flush and one-high onto a PCB. This layout practice provides the lowest profile, but unfortunately also dictates low packing density.

[0009] One implementation of highly dense memory is the dual inline memory module (DIMM). The DIMM is constructed by soldering TSOP devices onto one or both sides of a length of memory circuit board. Electrical contacts along an edge of the circuit board allow mounting the DIMM circuit board in a mating socket, generally perpendicular to the surface of a motherboard. The TSOPs are thereby aligned into a maximum configuration of eight or nine packages on either side of the DIMM, for a total of sixteen to eighteen packages, hard-soldered to the DIMM circuit board.

[0010] The relatively long wire bonds of the TSOPs, however, cause high levels of inductance, which results in crosstalk and signal delays. Both crosstalk and signal delays may severely limit performance at high frequencies. While the DIMM itself is socketable, which allows for upgrading when desired, individual TSOP modules require hot rework if a device fails.

[0011] DIMMs can be considered natural heat fins, but cooling efficiency is low due to the lack of an effective thermal transfer medium from the die to the air.

[0012] A high density implementation of memory chip packaging has been proposed by Nippon Electric Company (NEC). In the NEC Concurrent RAMBUS approach, the edge of a thin, edge-leaded package is the surface-mounted memory chip module. A number of these edge packages may be mounted in this manner, creating a stack of discrete packages. While the NEC approach offers a method of high density packaging, it does not easily allow for impedance matching, effectively controlling noise, or controlling signal propagation delay.

[0013] Soldered connections of the NEC implementation are limited also by processing requirements of surface mount devices. The edge leads require relatively large interlead spacing to allow reliable soldering to the board. The structure does not provide an adequate thermal solution because it does not allow for efficient airflow or thermal dissipation. Reworking soldered connections is challenging.

DISCUSSION OF THE RELATED ART

[0014] U.S. Pat. No. 5,572,065 for HERMETICALLY SEALED CERAMIC INTEGRATED CIRCUIT HEAT DISSIPATING PACKAGE; issued Nov. 5, 1999 to Carmen D. Burns, describes methods by which packages similar in form to TSOPs can be fabricated and mounted atop one another to achieve higher packing density and to dissipate heat. Designs such as described by Burns show that a silicon chip can be lapped thin, stacked on a thermally conductive lead frame, and electrically connected with rails at common sites, resulting in a stacked package that can be permanently bonded to a PCB (i.e., a motherboard or an add-on board). While such an approach can pack chips at a higher density, it results in a packaging structure inherently expensive and difficult to rework, should any portion of the aggregate device fail to work properly. The primary means for heat removal is inefficient and relies on thermal conduction through the body of the stack into a thermal slug or sink. Most importantly, these stacked memory devices cannot easily or inexpensively be adapted for high frequency operation which would require controlling electrical noise, impedance matching and signal delay matching (skew minimization).

[0015] U.S. Pat. No. 5,367,766 for ULTRA HIGH DENSITY INTEGRATED CIRCUIT PACKAGES METHOD; issued Nov. 29, 1994 to Carmen D. Burns, et al., discloses an integrated circuit package whose conduction rails also function as heat fin structures to radiate heat generated within the package. Although such a design attempts to improve thermal management, it does not allow easy high frequency design.

[0016] In U.S. Pat. No. 5,566,051; issued Oct. 15, 1996 to Carmen D. Burns, a lead frame itself is utilized as a thermal structure that can be placed in contact with a heat sink. This design also suffers from a limited thermal path, further interrupted by perforations in the frame that are necessary to reduce thermal stress.

[0017] The thermal structures of the inventive package provide both thermal paths and radiating surfaces, which are optimized for both thermal conduction and radiation, permitting maximum circuit density while controlling heat build-up in the module.

[0018] None of the aforementioned prior art structures provides for high frequency operation with structures such as signal lines, ground planes, dielectrics, connectors, etc. specifically included to reduce signal noise and delay, or to control signal path impedance utilizing lengths. Neither do these prior art structures provide for reliable packaging of a stacked, integrated circuit module because they each require a second level of interconnect between the singular devices making up the module stack and the PCB on which the stack is mounted. Variations or flaws in the intermediate interconnect layer may drastically affect electrical and mechanical reliability as more devices are added to the stack.

[0019] In addition, efficient and effective thermal conduction becomes even more crucial as heat is added to the stacked system, which already has narrow thermal paths. The final stack structure requires hot processing temperatures and extremely careful techniques, making both assembly and rework very expensive.

[0020] Nothing in the aforementioned prior art references or any other prior art known to the present inventors is seen to teach or suggest the high-density, high frequency, thermally-managed packaging structure of the instant invention.

[0021] It is, therefore, an object of the invention to provide an extremely high density vertically stacked daughter card package.

[0022] It is another object of the invention to provide a memory daughter card optimized for high frequency operation with specific structures for controlling and matching impedance, controlling and matching signal delays and reducing electrical noise.

[0023] It is a further object of the invention to provide a packaging structure having integrated thermal management structure to effectively maintain a reasonable operating temperature within the packaging structure.

[0024] It is yet another object of the invention to provide such a packaging structure with integrated thermal management in a low profile configuration.

[0025] It is an additional object of the invention to provide a high density daughter card packaging structure wherein individual daughter cards may be temporarily interconnected for testing.

[0026] It is yet another object of the invention to provide a high density daughter card package wherein individual daughter cards may be permanently interconnected after testing indicates that all daughter cards are functional.

[0027] It is still another object of the invention to provide a high density circuit daughter card package wherein daughter card rework may be easily and inexpensively performed without excessive exposure of daughter cards to damage by heat or handling during rework.

[0028] It is yet another object of the invention to provide a high density circuit daughter card package wherein electrical connectors both on daughter cards and external to the daughter card minimize electrical inductance to provide stable high frequency performance.

SUMMARY OF THE INVENTION

[0029] The present invention features an ultra high density, three-dimensional electronic circuit package suitable for constructing high capacity, high speed computer memory cards and the like. A high density connector system allows narrow contact-to-contact spacing, thereby permitting more discrete electrical connections within a given space than have heretofore been available. The small physical size of the contact system minimizes inductance and crosstalk, both on daughter cards carrying the memory devices as well as on the memory board, thus making the inventive packaging system suitable for high speed/high frequency applications. Furthermore, the daughter cards carrying the actual memory devices may be equipped with structures such as ground planes, etc. to minimize electrical noise, and designed to control and match impedances and signal path lengths, and maintain signal synchronization (i.e., controlling skew). In addition, the novel, demountable contact system allows easy test and/or burn-in.

[0030] A memory card has a number of electrical receptacles adapted to receive a daughter card. The daughter card has memory devices attached to it and a corresponding number of electrical connectors placed along at least one edge, adapted to detachably mate with the electrical receptacles of the memory card. The demountable connectors also allow easy rework of the module before optional, permanent solder attach.

[0031] The inventive daughter card may accommodate bare dies or variations of thin packages such as TSOPs, CSPs, COBs, etc., described hereinabove and/or well known to those skilled in the circuit packaging art. These dies or packages are mounted onto daughter cards, which in turn are mounted onto either a motherboard or memory card using pin/hole technology. Such a daughter card based structure provides a convenient way to mount thermal management structures of a variety of designs to maximize heat dissipation and to minimize cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when taken in conjunction with the detail description thereof and in which:

[0033] FIG. 1 a is a schematic view showing a CSP mounted on a daughter card;

[0034] FIG. 1 b is a schematic view showing a silicon chip mounted directly on a daughter card;

[0035] FIG. 2 is a schematic view of a memory card having a plurality of daughter cards mounted via pluggable contacts perpendicular to the memory card surface;

[0036] FIG. 3 is a side, schematic view of a memory card showing daughter cards attached in both a perpendicular and an angular arrangement;

[0037] FIG. 4 is a cross-sectional, schematic view of a memory daughter card incorporating a thermal management structure;

[0038] FIG. 5 is a schematic view showing the thermal management structure extends beyond the outline of a daughter card;

[0039] FIG. 6 is a schematic view illustrating a preferred method for attaching pins to a daughter frame utilizing lead frame technology;

[0040] FIG. 7 is a schematic view showing pin attachment to a daughter card;

[0041] FIG. 8 a is a schematic view illustrating pin attachment to both sides of a daughter board;

[0042] FIG. 8 b is a schematic, front plan view of a bent pin attachment;

[0043] FIG. 8 c is a side schematic view of the bent pin attachment shown in FIG. 8a; and

[0044] FIG. 9 is a schematic view of a daughter card with a memory chip and wiring traces.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0045] Generally speaking, the invention is an ultra high density, three-dimensional electronic circuit package suitable for constructing high capacity, high frequency, high speed computer memory cards and the like. A demountable contact system allows easy test and/or burn-in. A memory card has a number of electrical receptacles adapted to receive at least one daughter card. The daughter card has memory devices attached to it and a corresponding number of electrical connectors placed along at least one edge, adapted to detachably mate with the electrical receptacles of the memory card. The demountable connectors allow easy rework of the module before optional, permanent solder attach. Bare dies or thin packages are mounted onto daughter cards, which in turn are mounted onto either a motherboard or memory card using pin/hole technology. The inclusion of both strategically placed ground and/or power planes for impedance control, noise reduction, and the matching of signal path lengths, allow the design of daughter cards which operate reliably at high bus/clock speeds. Thermal structures mounted on and within the daughter card control temperatures, even in the densely-packed structure of the invention.

[0046] Referring first to FIGS 1a and 1b, there are shown two possible daughter card constructions. FIG. 1a shows a chip scale package (CSP) 14 mounted to a small daughter card 16. A variety of attachment techniques well known to those skilled in the art may be used for attaching the CSP 14 to the card 16. Leads 12 facilitate electrical connection of daughter board 16 to the memory card.

[0047] FIG. 1 b shows a silicon chip 18 mounted directly on a small daughter card 16. A variety of chip attachment techniques may be used, such as flip-chip (both solder and adhesive bond), and wire bonding, as well as other techniques also well known to those skilled in the art. Once again, leads 12 facilitate electrical connection of the daughter board 16 to the memory card.

[0048] The daughter cards 16 are generally composed of PCB materials such as an epoxy-glass such as FR-4 for matching the coefficient of thermal expansion (CTE) of the daughter card 16 to the motherboard and to conductive layers of material such as copper or copper alloy for signal, power and ground planes. In high frequency applications, other dielectric materials may be used, such as tetrafluoroethylene (TFE) and polyimide or other materials also known to those skilled in the art. Pins 12 may be formed in a variety of ways including: etching, stamping, or otherwise forming.

[0049] It should be understood that these two examples are by no means exhaustive; other methods for packaging daughter cards may also be employed to fit a particular operating circumstance or environment.

[0050] A preferred embodiment entails flip-chip bonding a bare die to a daughter card. The short connections of the instant invention replace the longer, traditional wire bonds of CSP and TSOP packages. These short connections greatly reduce inductance and therefore reduce electrical parasitics such as crosstalk. Since parasitic effects limit the frequency at which modules perform reliably without error, high frequency performance is improved by these reduced connection lengths. Bonding a bare die directly to a daughter card creates an efficient chip-carrying package. In addition to the advantage of reducing parasitics, the bare die has a lower profile (height) than does a die already in a package, enabling higher density daughter card stacks.

[0051] Parasitics may also be reduced by using striplines or microstrip lines when possible in the daughter card and in the memory cards themselves.

[0052] The inventive memory daughter cards may also contain thermal management structures contacting the chips, which conduct heat away from the chips. Such structures may be constructed by interleaving heat-spreading fins between the individual chip components and/or daughter cards. These fins may be made from materials that are thermally tailored to the device package. The construction of the memory daughter card, including thermal management structures, is described in detail hereinbelow.

[0053] The inventive contact systems in the memory card or motherboard can be used for either temporary connection during testing of the memory card, or for permanent attachment. If the connection is temporary, permanent attachment may be made after testing. This can be done for example by soldering at the connection itself.

[0054] Permanent attachment of the daughter cards to the memory board may be made after testing by soldering the pins of the daughter cards into the memory card. This works well since the holes in the memory card are plated through holes and the solder readily wicks up the pins forming a good mechanical and electrical connection between the pin and the plating of the hole.

[0055] A preferred connector to accomplish the above is the inventive PGA/receptacle described in the copending U.S. patent application, Ser. No. ______ [HCD-102]. As described therein, the short length of the connector and the capability to build in a ground plane improve performance, and the demountability improves manufacturing efficiency and rework.

[0056] Referring now to FIG. 2, there is shown a memory card 20 equipped with embedded contact holes 22 adapted to receive pins 12 from the daughter cards shown in FIGS. 1a and 1b. Pins 12 allow each of the these daughter cards to be inserted perpendicularly into embedded connection holes 22 in a memory card 20 or into a motherboard (not shown). The contact hole 22 can be a simple plated-through-hole structure of conventional practice, or the receptacle type described in the copending U.S. patent application, Ser. No. ______ [HCD-102].

[0057] Referring now to FIG. 3a, there is shown a schematic, side view of a memory card 20. Height profile 24 is lower than height profile 26 for perpendicular daughter cards. The lower profile 24 is achieved by bending the pins 12 either before or after insertion. An increase 28 in the overall length of card 20 compensates for the decrease in profile. Bending the pins 12 decreases the profile, enabling ultra-high density memory in low profile devices, such as notebook computers, that have previously been limited in memory.

[0058] Referring now to FIG. 4, there is shown a cross-sectional, schematic view of a daughter card 20 incorporating a thermal management structure such as a heat spreader or fin 42. Individual memory devices 46, in any side-mounted form, can have a specially-shaped thermal path or heat spreading fin 42 mounted permanently or non-permanently to its surface. A physically conformal, heat-conducting material 44 may be placed between the heat spreader 42 and the memory devices 46 to increase the area of the thermal path between the device 46 and the spreader 42. For those familiar with the art, the shape and size of the heat spreader 42 or fin 42 can be optimized to maximize the heat dissipation.

[0059] Referring now to FIG. 5, there is shown a front plan view of the daughter card 20 shown in FIG. 4. Heat spreader 42 may extend beyond any combination of three edges of daughter card 20 as may be required for a good thermal design.

[0060] Referring now to FIG. 6, there is shown a preferred method of attaching the pins 12 to the daughter card. Pins 12 for attachment to a daughter card are first stamped, etched, or otherwise formed, with one end left attached to lead (handling) frame 48 which is disjoined after pin attachment.

[0061] Referring now also to FIG. 7, the pins 12 in the frame 48 are next placed onto the pads 52 of the daughter card 20 with solder or solder paste (not shown) either on the pins 12 or on the pads 52. The pins 12 are then reflow-attached to the pads 52. After removal of the frame 48, the pins 12 remain attached to the daughter card 20. Pins 12 can have a slight point or taper 56, for ease of insertion.

[0062] Referring now to FIGS. 8a, 8b and 8c, pins 12 and 60 can optionally be mounted on respective sides of the daughter card 20. Pins 12 may be staggered, some pins 12b being bent away from the daughter card 20, while other pins 12a remain unbent. While a pattern of alternating straight and bent pins 12a and 54b is depicted, many other patterns of bent/straight pins may be utilized to meet a particular operating condition or circumstance. Both approaches of pins 12 and 60 (i.e., pins on both sides of daughter card 20, and bending certain pins 12b) allow the pins 12, 54a, 54b and mating holes (not shown) to be separated by greater distances, thereby reducing electrical parasitic effects.

[0063] Referring now to FIG. 9, daughter card 20 is shown with a mounted chip or chip carrier 46. Signal traces 65 may be on either external or internal layers (not shown). They are preferably of the stripline structure optimized for high frequency design due to the ground planes of the stripline structure. The daughter card 20 also readily allows the additional advantage for high frequency design, as depicted in FIG. 9 by substantial matching of signal lengths 65. This particular advantage in daughter card design is not easily shared by other package designs of prior art.

[0064] An immediate benefit of the inventive daughter card may be seen by examining the currently emerging RAMBUS memory architecture. Conventional RAMBUS configuration is usually implemented on up to three RIMM cards, each containing eight or sixteen chips. The high-density memory package of the instant invention allows placement of a full channel of thirty-two chips per RIMM, so that potentially two to four times as much memory may occupy the same area on the motherboard. This lowers memory cost and provides a new upper limit for the amount of memory which may be provided on a motherboard.

[0065] Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, this invention is not considered limited to the example chosen for purposes of this disclosure, and covers all changes and modifications which does not constitute departures from the true spirit and scope of this invention.

[0066] Having thus described the invention, what is desired to be protected by Letters Patent is presented in the subsequently appended claims.

Claims

1. A high-density, high frequency memory package comprising: a) a memory card having a plurality of electrical receptacles adapted to receive a daughter card; and b) a daughter card having at least one memory device attached thereto and a plurality of electrical connectors adapted to mate with said electrical receptacles, said plurality of electrical connectors being disposed along at least one edge of said daughter card.

2. The high-density, high frequency memory package as recited in claim 1, wherein said plurality of electrical connectors is adapted to detachably mate with said electrical receptacles.

3. The high-density, high-frequency memory package as recited in claim 2, wherein said daughter card comprises a multi-layer printed circuit board (PCB).

4. The high-density, high frequency memory package as recited in claim 1, wherein said memory device is packaged at least in one from the group of: bare chip, thin, small-outline packages (TSOP), and chip-scale packages (CSP).

5. The high-density, high frequency memory package as recited in claim 4, wherein said attachment of said unpackaged or packaged memory devices to said daughter card is accomplished by at least one process from the group: flip-chip attachment, wire bond attachment and direct soldering.

6. The high-density, high frequency memory package as recited in claim 1, wherein said electrical receptacles comprise a plurality of holes disposed in said memory card.

7. The high-density, high frequency memory package as recited in claim 6, wherein at least one of said plurality of holes comprises a plated through hole.

8. The high-density, high frequency memory package as recited in claim 7, wherein at least one of said plurality of holes further comprises a conductive member protruding radially into said hole.

9. The high-density, high frequency memory package as recited in claim 8, wherein said electrical connectors comprise pins adapted to fit into said holes, said pins being mechanically, detachably retained in said holes by said conductive members, whereby an electrical connection between said daughter card and said memory card is established.

10. The high-density, high frequency memory package as recited in claim 9, wherein said daughter card comprises a front surface and a rear surface and said pins are disposed along at least one edge on both said front and said rear surface.

11. The high-density, high frequency memory package as recited in claim 10, wherein at least one of said pins is offset from at least one adjacent pin.

12. The high-density, high frequency memory package as recited in claim 10, wherein said pins have a cross-section having a shape from the group: round, oval, square, rectangular and polygonal.

13. The high-density, high frequency memory package as recited in claim 12, wherein said pins are substantially cylindrical.

14. The high-density, high frequency memory package as recited in claim 13, wherein said daughter card has a predetermined thickness and said pins have a length approximately equal to said thickness.

15. The high-density, high frequency memory package as recited in claim 14, wherein the distal end of said pins is pointed.

16. The high-density, high frequency memory package as recited in claim 12, wherein said pins are tapered.

17. The high-density, high frequency memory package as recited in claim 16, wherein a distal end furthest from said daughter card is substantially pointed.

18. The high-density, high frequency memory package as recited in claim 2, wherein said at least one memory device comprises memory devices from the group of bare memory chips and packaged memory chips.

19. The high-density, high frequency memory package as recited in claim 18, further comprising: c) heat transfer means attached to at least one of said plurality of said memory devices.

20. The high-density, high frequency memory package as recited in claim 19, wherein said heat transfer means comprises thermally conductive heat fins in contact with said memory devices.

21. The high-density, high frequency memory package as recited in claim 20, wherein said at least one daughter card comprises a plurality of cards adjacent to, substantially parallel to, and in contact with one another on said memory card.

22. The high-density, high frequency memory package as recited in claim 21, wherein said at least one of said thermally conductive heat fins is interspersed between said plurality of daughter cards.

23. The high-density, high frequency memory package as recited in claim 1, wherein conductive traces are on the surfaces and internal to daughter cards, with ground planes on the surfaces and internal to said daughter cards, wherein said ground planes and traces are arranged in stripline and microstrip structures.

24. The high-density, high frequency memory package as recited in claim 23, wherein said signal trace path lengths are substantially matched.

25. A method for assembling a high-density memory package, the steps comprising: a) attaching a plurality of memory devices to at least one daughter card having a plurality of pins along at least one edge thereof, said pins being respectively and operatively connected to said plurality of memory devices; b) providing a memory board having a plurality of plated through holes adapted to detachably receive said plurality of pins; c) after said attaching step (a), testing each of said at least one daughter card connected to said memory board; d) detaching and replacing any daughter card failing said test performed in step (c); e) retesting said replaced daughter card; and f) repeating said detaching and replacing step (d) and said retesting step (e) until a completely functional memory package is obtained.

26. The method for assembling a high-density memory package as recited in claim 25, the steps further comprising: g) soldering said at least one daughter card to said memory board upon successful completion of said testing step (c) and retesting step (e).

27. The method for assembling a high-density memory package as recited in claim 24, the steps further comprising: h) placing at least one heat transfer means between predetermined ones of said daughter cards.