This application claims priority from European patent application No. 06425396.6, filed Jun. 13, 2006, which is incorporated herein by reference.
An embodiment of the present invention relates, in general, to a MOS device and to the manufacturing process thereof. In particular, an embodiment of the invention relates to a MOS device that can be used as power amplifier for radio-frequency (RF) applications.
As is known, in applications at high frequency (for example, between some hundreds of MHz and some GHz) and high power, where the individual MOS devices supply powers comprised between fractions of a watt and some hundreds of watts, it is convenient to operate with supply voltages that may exceed 30 V. More in general, it is convenient, as the power requirement increases, to increase the voltage range across the device during operation. This range is limited by the drain-to-source breakdown voltage (Bvdss). For example, in amplifiers that operate in “class A” or “class B”, the “instantaneous” drain-to-source voltage of the power MOS device may reach values that are twice that of the supply voltage. This implies that the drain-to-source breakdown voltage of the device must be in the region of 70 V, which may impose dimensional constraints on some important regions of the device.
Said constraints contrast, however, with the achievement of high dynamic performances. In fact, to achieve these performances may require the use of sub-micrometric gate lengths. These lengths are in fact commonly used for the same purpose in other technologies, such as, for example, CMOS technology, where, however, the above geometrical parameter is normally reduced at the expense of the supply voltage. A similar problem arises for the light-doped drain (LDD) region, which often is rendered longer, at the expense of the resistance that it offers to the passage of current, to withstand high voltages.
In addition to these contrasting requirements, operating at the high voltages referred to, well-known phenomena of electrical degradation, due to hot-carrier injection (HCI), may arise, which render it even more difficult to reach the compromise between the various requirements and which set a limit to the dynamic performance of the device.
In order to improve the dynamic performance, one may reduce the reaction capacitance Cgd between the gate and the drain of the device. In fact, by reducing this capacitance, it is possible to obtain an improvement in the figure of merit fmax (maximum oscillation frequency) or more in general in the power gain. In addition, the minimization of the variation in capacitance as the drain voltage varies reduces the intermodulation distortion generated by the device while amplifying a modulated signal. Since the power gain decreases as the operating frequency increases, a top limit is set to the frequency at which it is still convenient to use the device. In order to operate usefully at higher frequencies, it is then necessary to design the device so that it initially has a higher gain. Thereby, also at the maximum oscillation frequency fmax, it is able to operate with desired power gain.
Solutions are known to the art for reducing the intrinsic capacitive coupling between the gate electrode and the drain region and minimizing the hot-carrier phenomena, which, by causing charge trapping near the gate region, degrade the electrical performance of the device.
For example, the article “Novel LDMOS Structures for 2 GHz High Power Basestation Application” by H. F. F. Jos, 28th European Microwave Conference Proceedings, Amsterdam, NL, vol. 1, Oct. 6, 1998, which is incorporated by reference, describes a structure for reducing the gate-to-drain capacitance Cgd, which comprises a metal path referred to as “shield metal”, which is defined, with a lithographic process, simultaneously to the gate metal and to the drain metal. This solution sets constraints on the length of the drain-extension region, since the shield-metal region must be defined within this space. In addition, the known solution does enable reduction of the capacitance between the drain metal and the gate metal, but is far from effective in reducing the intrinsic capacitance between the polysilicon gate electrode and the drain-extension region, which contributes also to the total gate-to-drain capacitance Cgd.
WO 00/49663 and EP-A-1 635 399, which are incorporated by reference, describe the formation of shield regions of a conductive material deposited only on one side of the gate region, on top of the drain region, thereby enabling a drastic reduction in the capacitive coupling between the gate electrode and the drain region.
In both solutions, it is disadvantageous that, when the drain-extension region is slightly depleted and consequently the neutral drain region is close to the gate electrode, there is an increase in the gate-to-drain parasitic capacitance, which is worsened by the fact that the thickness of the gate oxide, which separates the two regions referred to above, is normally of some tens of nanometers.
In the known solutions, then, the drain region is found in the proximity of the channel region underneath the gate region, when the latter is biased. The voltage applied to the drain has a marked influence on the channel region and consequently modulates the current of the device, giving rise, should the gate length not be sufficient, to the well-known short-channel effects.
An embodiment of the invention overcomes one or more of the disadvantages presented by known solutions by providing a device having a high power gain and capable of operating properly at high operating frequencies.
One or more embodiments of the invention are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:
In detail, the device 1 of
A gate region or gate electrode 10 extends on top of the surface 7, overlying the channel 5, and is insulated from the body 2 by a gate-oxide layer 11. In particular, the gate region 10 is aligned on one side to the source region 4, and, on the opposite side, a conductive region 12 is set alongside it, electrically separated therefrom by a dielectric wall 14. An insulating layer 15 coats the body 2 and is passed by a drain metallization 16 in electrical contact with the drain region 3, and by a source metallization 17 in electrical contact with the source region 4.
As may be noted from
In the geometrical conditions described and if the conductive region 12 is left floating or is connected to the drain metallization 17, which often constitutes the zero reference voltage, the device 1 is not able to operate properly and its electrical output characteristics are markedly penalized as compared to the case where the channel region 5 extends only underneath the gate region 10. Consequently, according to one embodiment of the invention, the conductive region 12 is biased at a voltage Vx other than zero. In this way, it is possible to restore proper operation of the device 1 and simultaneously achieve the advantages resulting from its performances. In the particular case shown in
Since, in order to bias the conductive region 12, an electrical connection of a finite length is provided, accompanied by a parasitic inductance, represented in the equivalent electrical circuit of
In
The voltage source 19 can be constant or variable. If the voltage source 19 is variable (as shown in
At sufficiently low voltages of the drain region 3, such that this region is only slightly depleted, the positive biasing of the conductive region 12 can create an inversion layer densely populated by electrons within the portion 5a of the channel region 5 that extends underneath the conductive region 12. In this case, the conductive region 12 consequently operates like the gate of a MOS device of an enhancement type, which, in turn, is connected in series to the MOS transistor that has as a gate the gate region 10, providing continuity to the current flow of the resulting structure. In these conditions, the device 1 is thus comparable to a known dual-gate device.
As indicated, the density of the portion 5a can be modulated by suitably varying the voltage Vx, and its lateral distance from the gate region 10 can also be controlled by suitably varying the geometry of the system, for example, by changing the thickness of the dielectric wall 14 throughout the height of the wall or on a part thereof.
By increasing, for example, the thickness of the dielectric wall 14, the parasitic capacitance between the gate region 10 and the conductive region 12, which is connected dynamically to ground, is reduced, to the advantage of the total input capacitance Ciss of the device 1. By so doing, however, the inversion layer moves away from the gate region 10, penalizing the static performance of the device 1, whose current is reduced and can be maintained at the desired levels only by further increasing the voltage applied to the conductive region 12.
If the drain voltage 3 is increased so as to laterally deplete its portion close to the conductive region 12, then the inversion region created within the portion 5a of the channel region 5 cannot be formed, leaving, however, a drift region, which is able to collect the electrons coming from the side of the source region 4.
In practice, according to the specific application and the particular requirements, it is possible to define the geometrical parameters of the device 1 of
In particular,
The MOS transistor 40 is formed in a body 2 comprising a substrate 21 of a P+ type and an epitaxial layer 22 of a P type. The epitaxial layer accommodates a body region 23, of a P+ type, which extends underneath the gate region 10 up to the source metallization 17. The body region 23 accommodates the source region 4, of an N+ type. The epitaxial layer 22 moreover accommodates a drain-extension region 24 of an N− type, similar to the drain region 3 of
A dielectric layer 27, for example of silicon oxide, surrounds the gate region 10 and forms the dielectric wall 14 of
Indicatively, the thickness of the dielectric layer 27 can be chosen between 20 and 60 nm, the height of the conductive region 12 is approximately the same as that of the gate region 10, for example approximately 400 nm, and the width of the conductive region 12, in a horizontal direction, is between 200 and 500 nm and is, for example, approximately 300 nm.
The MOS device 40 of
Epitaxial region 22 is grown on the substrate 21, having a resistivity comprised between a few units and some tens of mΩcm, for example, between 5 mΩcm and 20 mΩcm, dopant concentrations in the range 1014-1015 cm−3 and thicknesses such that, at the end of all the thermal processes, the residual thickness of the epitaxial region 22 is in the range of a few microns.
In a per se known manner, the gate-oxide layer 11 (having a thickness of not more than 40 nm in one embodiment) and the gate region 10 are obtained on the surface of the body 2. The gate region 10 is obtained by depositing a single polysilicon layer or using a polysilicon/silicide double layer.
After defining the gate-oxide layer 11 and the gate region 10, the body region 23 is implanted on one side of the gate region 10 within the epitaxial layer 22, in a self-aligned way to the gate region 10, with implantation doses in the range of 2-9×1013 cm−2. Next, the source region 4 and the drain-contact region 25 are implanted. For example, As is implanted at doses in the range of 1015 cm−2 so as to minimize the contact resistance with the source metallization 17 and the drain metallization 16. The thermal processes necessary for activating and diffusing the implanted species can be performed at the end of each implantation process so as to maximize, for example, the degrees of freedom in forming the junctions. In particular, the contour of the body region 23 does not constitute a well defined boundary in so far as this portion is provided with a species that is homologous to that of the epitaxial region 22. In this way, thanks to the process of body ionic implantation and to the corresponding diffusion process, the semiconductor region underneath the gate region 10 is enriched with respect to its pre-existing background concentration.
Next, a dielectric layer 27, conveniently of silicon oxide, is deposited on the surface of the body 2 and has a thickness of a few tens of nanometers. In this way, the structure of
Then (
According to EP-A-1 635 399, during anisotropic etching for forming the conductive region 12, it is possible to provide contact regions 33 (visible in
Next (
Next, using a photolithographic process, an LDD mask 32 is provided, which covers the entire the surface of the body 2 except for the area where the drain-extension region 24 is to be implanted. Then, an implantation is performed with a species homologous to that of the source region 4 and drain region 25 using doses in the range of 0.5-4×1012 cm−2, as represented schematically in
Finally, the insulating layer 15 is deposited and a photolithography is performed to open the source contact 35, the drain contact 36, and the gate contact 37 (
In order to minimize the parasitic capacitance between the conductive region 12 and the gate region 10 and simultaneously maintain the functionality of the MOS device, it is possible to modify the manufacturing sequence with respect to what described with reference to
In particular, according to this second embodiment, the same steps described previously with reference to
Consequently, using one of these techniques, as shown in
The subsequent steps are similar to those described with reference to
In this way, thanks to the variable thickness of the dielectric layer 27′ on the lateral wall of the gate region 10 at the side of the conductive region 12, the parasitic capacitance between the conductive region 12 and the gate region 10 is reduced as compared to the first embodiment (
Finally, it is clear that numerous modifications and variations can be made to the MOS device and to the manufacturing process described and illustrated herein, all of which fall within the scope of the invention.
In particular, the solution presented can be applied also to MOS devices of different type, with P channel (in which case the biasing voltage to be applied to the conductive region 12 is of an opposite sign with respect to the case described). For example, the present solution can be used for obtaining an NMOS transistor with CMOS technology.
One or more of the above-described transistors may be part of an electronic circuit, such as an amplifier, which may be part of a system such as a cell phone or wireless modem.
Number | Date | Country | Kind |
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06425396 | Jun 2006 | EP | regional |
Number | Name | Date | Kind |
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4189737 | Horninger | Feb 1980 | A |
4290077 | Ronen | Sep 1981 | A |
5789297 | Wang et al. | Aug 1998 | A |
6090693 | Gonzalez et al. | Jul 2000 | A |
6222229 | Hebert et al. | Apr 2001 | B1 |
20060054954 | Santangelo et al. | Mar 2006 | A1 |
Number | Date | Country |
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1 635 399 | Mar 2006 | EP |
WO 0049663 | Aug 2000 | WO |
Number | Date | Country | |
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20070284673 A1 | Dec 2007 | US |