Patent Application
20240351863
The present disclosure generally relates to monolithic integrated CMOS-MEMS devices. More particularly, the disclosure relates to monolithic integrated CMOS-MEMS devices with highly sensitive MEMS sensors. The highly sensitive MEMS sensors are free-standing MEMS sensors, such as free-standing MEMS infrared sensors.
The demand for uncooled infrared detectors is continually growing due to the increased demand from numerous applications. These applications, just to name a few, include air conditioning systems, handphones, autonomous driving cars, the internet of things (IoT), fire-fighting and traffic safety.
Conventional uncooled infrared detectors have been implemented using microbolometers. However, microbolometers require mechanical components for calibration purposes. As an example, microbolometers require mechanical shutters for offset correction. The required mechanical components for microbolometers increase manufacturing complexity. Such complexity increases cost. In addition, the need for mechanical components for microbolometers makes it difficult to produce small or compact devices as well as being more susceptible to reliability issues.
The present disclosure is directed to cost-effective and compact infrared detectors with high sensitivity and response time integrated with CMOS components.
Embodiments of the present disclosure generally relate to devices and methods of forming thereof. In one embodiment, a device is disclosed. The device includes a substrate with a complementary metal oxide semiconductor (CMOS) region and a microelectromechanical systems (MEMS) region. The CMOS region includes transistor regions with transistors. The MEMS region includes a lower sensor cavity and a free-standing sensor disposed over the lower sensor cavity. The free-standing sensor is devoid of a support dielectric between the sensor and the lower sensor cavity. The free-standing sensor improves response time and sensor sensitivity. A pre-metal dielectric layer with pre-metal contacts is disposed on the substrate over the CMOS and MEMS regions. A back-end-of-line (BEOL) dielectric is disposed on the pre-metal dielectric layer. The BEOL dielectric includes a plurality of inter-metal dielectric (IMD) layers with metal and via levels disposed over the pre-metal dielectric. The metal levels include metal lines and the via levels include via contacts for interconnecting the components of the device via the pre-metal dielectric layer.
In another embodiment, a method for forming a device is disclosed. The method includes providing a substrate prepared with a complementary metal oxide semiconductor (CMOS) region and a microelectromechanical systems (MEMS) region. The CMOS region is processed to form first and second types of transistors in first and second transistor regions. The MEMS region is processed to form a lower sensor cavity trench filled with a cavity trench fill. A sensor support dielectric layer is formed over the lower sensor cavity on top of the trench fill. A sensor is formed on the sensor support dielectric layer. A pre-metal dielectric layer with pre-metal contacts connected to the CMOS and MEMS components of the device is formed on the substrate. A back-end-of-line (BEOL) dielectric is formed on the pre-metal dielectric layer. The BEOL dielectric includes a plurality of inter-metal dielectric (IMD) layers with metal and via levels, the metal levels include metal lines and the via levels include via contacts for interconnecting the CMOS and MEMS components of the device via the pre-metal dielectric layer. The BEOL dielectric and pre-metal dielectric are patterned to form a sensor opening in the dielectric layers. The patterning of the dielectric layers also forms release openings to expose the cavity trench fill. A first release is performed to remove the cavity trench fill to form the lower sensor cavity followed by a second release to remove the sensor support dielectric. This results in the sensor being a free-standing sensor. The free-standing sensor improves sensor sensitivity and response time.
These and other advantages and features of the embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
The accompanying drawings, which are incorporated in and form part of the specification in which like numerals designate like parts, illustrate preferred embodiments of the present disclosure and, together with the description, serve to explain the principles of various embodiments of the present disclosure.
Embodiments generally relate to devices, for example, semiconductor devices or integrated circuits (ICs) with thermoelectric-based infrared detectors. The IC, for example, is a complementary metal oxide semiconductor (CMOS) device. As for the infrared detector, it is, for example, a micro-electrical mechanical system (MEMS) detector. The MEMS detector is embedded into the IC with high CMOS integration. Furthermore, the MEMS detector is compatible with CMOS processing. The devices can be incorporated into products, such as thermal imagers. For example, a device may include a plurality of MEMS sensors which can be configured to form a sensor array for a thermal imager. The sensors may be used for other types of applications, such as single-pixel or line array temperature or motion sensors.
The fabrication of devices may involve the formation of features on a substrate that makes up circuit components, such as transistors, resistors, capacitors and MEMS sensors. The components are interconnected, enabling the device to perform the desired functions. To form the features and interconnections, layers are repeatedly deposited on the substrate and patterned as desired using lithographic techniques. For example, a wafer is patterned by exposing a photoresist layer with an exposure source using a reticle containing the desired pattern. After exposure, the photoresist layer is developed, transferring the pattern of the reticle to the photoresist layer. This forms a photoresist etch mask. An etch is performed using the etch mask to replicate the pattern on the wafer below, which may include one or more layers, depending on the stage of the process. In the formation of the devices, numerous reticles may be used for different patterning processes. Furthermore, a plurality of devices may be formed on the wafer in parallel.
The wafer includes an active surface 111 on which a device 115 is formed. A plurality of devices may be formed on the wafer in parallel. The devices, for example, are arranged in rows along a first (x) direction and columns along a second (y) direction. Separating the devices are dicing channels. After processing is completed, the wafer is diced along the dicing channels to singulate the devices into individual chips.
The device includes a substrate 205. The device, for example, may be a part of the wafer, as described in
As shown, the CMOS region includes first and second CMOS component regions 220. The first component region may be a first type component region and the second component region may be a second type component region. The first type component region may be a p-type component region and the second type component region may be an n-type component region. The component regions, for example, accommodate metal-oxide field effect transistors (MOSFETs) 222. For example, the component regions are transistor regions. Providing component regions for other types of components may also be useful. In one embodiment, the first transistor region is a p-type transistor region for a p-type transistor and the second transistor region is an n-type transistor region for an n-type transistor.
A transistor region includes a transistor well 221. The transistor well is an oppositely doped well. For example, if the transistor region is a p-type (first type) transistor region, the well is an n-type (second type) doped well. The transistor well serves as the body of the transistor. The transistor includes a gate disposed above the substrate between the first and second first type heavily doped source/drain (S/D) regions 2241-2 disposed in the transistor well.
The gate of the transistor may include a gate electrode 234 over a gate dielectric 232. The gate electrode may be polysilicon and the gate dielectric may be thermal silicon oxide. Other types of materials or configurations of gates may also be useful. For a p-type MOS transistor, the device well is an n-type well and the S/D regions are heavily doped p-type regions. On the other hand, an n-type transistor has a p-type device well and heavily doped n-type S/D regions. The S/D regions may include lightly doped extension regions. The lightly doped extension regions are lightly doped with the same polarity type dopants as the heavily doped S/D regions. The sidewalls of the gate may include dielectric spacers. The spacers facilitate aligning the S/D and lightly doped extension regions. The transistor well may include a well contact 228 which is heavily doped with the same polarity type dopants as the transistor well.
The CMOS region, as shown, may be a logic region which includes first and second transistors. However, the logic region may include numerous transistors. In addition, the logic region may include regions for transistors having different operating characteristics or voltages. For example, low voltage transistors may be provided in a low voltage (LV) region, intermediate or medium voltage transistors may be provided in a medium voltage (MV) region and high voltage transistors may be provided in a high voltage (HV) region. Other types of device regions may also be included. For example, a memory region may be included in which a memory array is disposed.
Isolation regions 280 are provided to isolate the component regions. For example, isolation regions are provided to isolate the first and second transistor regions as well as the sensor region. In addition, isolation regions may be provided to isolate a well contact from an S/D contact. The isolation regions may be field oxide (FOX) isolation regions. Other types of isolation regions, such as shallow trench isolation (STI) regions, may also be useful.
As shown, the sensor region includes a sensor 250, such as a CMOS compatible sensor. For example, the sensor region is configured for one sensor. In one embodiment, the sensor is a MEMS infrared sensor. Other types of sensors may also be useful. As shown, a lower sensor cavity 260 is disposed in the substrate below the sensor. The lower sensor cavity, in one embodiment, is disposed below the surface of the substrate. For example, the lower sensor cavity is a trench that has been etched into the substrate. The lower sensor cavity may have a square or rectangular footprint or shape. Other shapes for the lower sensor cavity may also be useful. The bottom and sides of the lower sensor cavity are defined by the substrate.
A reflector 262 is disposed at the bottom of the lower sensor cavity. The reflector reflects infrared radiation. The reflector may be formed from a conductive material. In one embodiment, the reflector is a conductive metal silicide reflector. The metal silicide reflector may be a titanium silicide (TiSix), a tungsten silicide (WSix) or an aluminum silicide (AlSix) reflector. Other types of metal silicide reflectors may also be useful. Alternative types of reflectors may also be useful. For example, the reflector may be a conductive reflector layer. The conductive reflector layer may be a doped reflector layer, such as a doped polysilicon layer. The doped reflector layer may be heavily doped with p-type or n-type dopants. For example, the dopant concentration of the doped reflector layer may be about 1021 dopants/cm3. The conductive properties of the surface of the doped region are attributed to the high concentration of dopants being applied, thereby enabling the reflection of the incoming infrared radiation. In other embodiments, the reflector may be a non-conductive reflector, such as a photonic crystal reflector. For example, a photonic crystal layer is formed by etching the surface of the lower sensor cavity. The photonic crystal layer may include a grating pattern configured to reflect incident infrared radiation. For example, different grating patterns of varying depths may be etched from the surface of the photonic crystal layer to adjust the wavelengths and properties of the reflected infrared radiation. Other types of reflectors may also be useful.
In one embodiment, the sensor is a free-standing infrared MEMS sensor suspended over the lower sensor cavity. The infrared MEMS sensor, in one embodiment, is a thermopile infrared sensor. The free-standing MEMS sensor does not have a support dielectric layer disposed below it. For example, the support and protection dielectric layer are removed in the second release process. The free-standing sensor defines a top of the lower sensor cavity.
In some embodiments, the free-standing sensor includes an absorber layer (not shown) on its surface. In such cases, the free-standing sensor includes an absorber layer over it. The absorber layer, for example, is configured to absorb incident infrared radiation. In one embodiment, the absorber layer is disposed on a central portion of the sensor body. The absorber layer is thermally coupled to a center of the sensor body. The absorber layer may be a silicon nitride (SiN) layer. Other types of absorber layers may also be useful. For example, the absorber layer may be a doped polysilicon layer, nickel-chromium (NiCr) layer or titanium nitride (TiN) layer. In the case of a conductive absorber layer, it is electrically and thermally coupled to the hot end of the sensor. A protective layer may be provided to protect the absorber layer. The protective layer may be removed by the second release process.
In one embodiment, the absorber is part of an interferometric absorption system. For example, the absorber may be integrated as part of an interferometric system to improve absorption efficiency or performance. In one embodiment, the interferometric absorption system is configured or tuned to efficiently absorb incident infrared radiation at the desired wavelength. For example, the absorption system may be tuned to absorb greater than 80% of incident infrared radiation having a wavelength of 8-14 μm. Providing any other configurations may also be useful. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2-5 μm. For example, another harmonic of the interferometric absorber may be used. In one embodiment, the interferometric absorption system includes the absorber and reflector configured with a ¼ wavelength spacing therebetween. For example, the desired wavelength is the center wavelength of the desired range of wavelengths to be absorbed. The highly efficient interferometric absorber layer improves sensor sensitivity.
In one embodiment, the lower sensor cavity has a depth which is selected for optimal reflection of infrared radiation by the reflector. For example, the lower sensor cavity is part of the interferometric absorption system. In one embodiment, the depth of the cavity is sufficient to ensure ¼ wavelength optical distance between the absorber and reflector. For example, the optical distance may be about 2-3 μm for detecting infrared radiation having a wavelength of 8-12 μm. Other distances may also be useful, depending on the wavelength to be detected. For example, by decreasing or increasing the optical distance, infrared radiation with smaller or larger wavelengths can be detected respectively. The optical distance is defined as the distance where the infrared radiation wave possesses an optical path going through several layers.
In one embodiment, the sensor includes a sensor body with first and second body segments 251P and 251N. The first and second body segments, in one embodiment, are doped with first and second polarity type dopants. For example, the first body segment is doped with p-type dopants and the second body segment is doped with n-type dopants. The sensor body, for example, is patterned to form first and second body segments. The sheet resistance of the sensor body is adjusted to match the ambient sheet resistance, which is about 377 Ω/square. This advantageously enables the sensor body to also serve as an absorber. For example, no additional absorber layer is necessary. In one embodiment, the sensor body is a polysilicon sensor body. Other types of materials which are stable under high temperatures having thermoelectric properties may also be used to serve as the sensor body. For example, such materials may include silicon germanium (SiGe), gallium nitride (GaN) or a 2D material, such as graphene, black phosphorus or molysulfide.
In one embodiment, the sensor body is configured to be resistant to the second release process (second release etchant). In the case that an absorber layer is provided over the sensor body, the absorber layer should also be resistant to the second release etchant. If not, a protective layer is provided over the absorber layer.
Patterning and doping the sensor body, for example, may be achieved using mask and doping and mask and patterning techniques. As for the doping of the body segments, it may be integrated with the S/D doping processes of the p-type and n-type transistors. Other techniques for doping the body segments may also be useful.
The patterning of the sensor body forms sensor body segments with main segments and lead segments. For example, the patterning of the sensor body forms a p-doped body segment with a p-doped main segment and a p-doped lead segment and an n-doped body segment with an n-doped main segment and an n-doped lead segment. The ends of the first and second lead segments serve as first and second sensor terminals. The first and second terminals, for example, are cold ends or cold terminals of the thermoelectric sensor. The patterning of the sensor body also forms openings or spaces 254 within the sensor body. For example, the spaces are disposed between the sensor body main and lead segments. Other configurations of the spaces, sensor body main and lead segments may also be useful. The openings facilitate a release process for forming the lower sensor cavity. In one embodiment, the patterning also forms undoped body spacers (not shown) which are in contact with both the first and second body segments. The spacers enhance the mechanical stability of the free-standing sensor body.
The first and second body segments, in one embodiment, have about the same surface area to produce about symmetrical heat dissipation between the segments. Variations in processing may occur, causing variances in the surface areas of the first and second body segments. Preferably, the variance is less than about ±5%. Other variances which produce acceptable differences in heat dissipation between the body segments may also be useful. For example, the surface area differences may be less than about ±20%. In one embodiment, the first and second body segments are essentially mirror images of each other. Other configurations of the body segments may also be useful.
In one embodiment, the sensor is a double-released sensor. For example, a first release process is used to create the lower sensor cavity while the second release process is used to create the free-standing sensor by removing the support and protection dielectric layer. The second release forms a step 268 in a contact dielectric layer 271.
In one embodiment, a sensor body contact 255 couples the first and second body segments. The body contact may be disposed at the interface of the first and second body segments, interconnecting them. As shown, the sensor body contact includes sensor body via contacts 257 connected to the body segments and a second body interconnect 256 interconnecting the sensor body via contacts. In one embodiment, the sensor body contact should be a high-temperature contact. For example, the sensor body contact can sustain subsequent process temperatures. The components of the sensor body contact may be formed of titanium (Ti), aluminum (Al) or a combination thereof. Other types of high-temperature metals which are CMOS process compatible may also be used to form the components of the sensor body contact. In one embodiment, the sensor body via contacts are closed-loop sensor body via contacts. For example, the closed loop via contacts traps dielectric within the closed loops, even after the second release process. This provides additional mechanical stability for the free-standing sensor body.
A pre-metal interlayer dielectric (ILD) layer 271 disposed on the substrate over the CMOS components. As shown, the pre-metal ILD layer includes pre-metal contacts 272 which are connected to contact regions of the components. For example, the pre-metal contacts are connected to S/D regions, transistor gates and well contacts. The pre-metal contacts, for example, may be tungsten (W) contacts. Other types of contacts may also be useful. The pre-metal ILD layer may be formed from multiple dielectric layers. Various dielectric materials, such as silicon oxide (SiO2), may be used to form the pre-metal ILD layer. The pre-metal contacts may be formed by a single damascene process. Other techniques for forming the pre-metal contacts may also be useful.
Forming the CMOS components, such as transistors, the sensor and the ILD layer with pre-metal contacts may be considered a part of the front-end-of-line (FEOL) processing. After FEOL processing, back-end-of-line processing commences. Other configurations of FEOL and BEOL may also be useful.
A back-end-of-line (BEOL) dielectric layer 270 is provided over the ILD layer. In one embodiment, the BEOL dielectric is formed by BEOL processing. In one embodiment, the BEOL dielectric layer includes a plurality of intermetal dielectric (IMD) layers 274 disposed over the pre-metal ILD layer. An IMD layer includes a metal-dielectric level or layer 274M below a via dielectric level 274V. The dielectric layers of the IMD layer may be SiO2. Other types of dielectric materials or combinations of dielectric materials or layers may also be useful to form the IMD layer. The metal level includes metal lines 277 in the metal-dielectric layer and the via level includes via contacts 273 in the via dielectric layer. The metal lines and via contacts may be formed using damascene techniques, such as a single or a dual damascene process. In the case of a single damascene process, the contacts and metal lines are formed in separate processes. In the case of a dual damascene process, the metal lines and contacts are formed in the same process.
In some embodiments, the metal lines may be formed using a reactive ion etching (RIE) process. For example, a metal layer is formed and patterned by RIE using an etch mask to form the metal lines. The different IMD layers may employ different processes. For example, one IMD layer may employ separate single damascene processes to form the contacts and metal lines, another may employ a dual damascene process to form the contacts and metal lines, and yet another may employ a single damascene process to form the contacts followed by an RIE process to form the metal lines.
The IMD layers may be planarized to form a planar top surface over the CMOS region and the MEMS region. For example, CMP is performed on the substrate. Providing any other planarization techniques such as spin-on-glass (SOG) to fill the gaps or planarize the surface of the substrate may also be useful. The overall thickness of the IMD layers over the structure may be from 100-400 nm. Providing any other thicknesses for the IMD layers over the structure to define the depth of the vias for subsequent standard CMOS processes may also be useful.
A passivation layer 278 is disposed above the top metal level of the BEOL dielectric layer. The passivation layer may be a silicon nitride layer. Other types of passivation layers may be used. The passivation layer may serve as an etch stop and top protection layer. In some embodiments, the passivation layer may be a passivation stack having multiple passivation layers, such as a combination of silicon oxide and silicon nitride layers. As shown, a dielectric layer is provided over the top metal dielectric layer. The dielectric layer may be considered as a top via dielectric layer below the passivation layer. In some cases, the dielectric layer may be considered a part of the passivation stack. In yet other cases, a dielectric layer may be disposed over the passivation layer but is removed during processing. Other configurations of the passivation layer may also be useful. The passivation layer serves as a protection layer for the BEOL dielectric layer during the double-release processing for forming the sensor.
The top metal level of the top BEOL dielectric serves as a pad level. Bond openings 276 are provided in the passivation layer to expose the bond pads below. For example, the top metal level of the BEOL dielectric layer is covered by the passivation stack. The top metal level does not include a via level. The bond pads provide external access to the internal components of the device. For example, input, output and power signals may be provided via the bond pads. Bond pads are provided in the periphery of the device. As shown, bond pads are provided on one side of the device which is the opposite side of the sensor region. Bond pads may also be provided on one or more of the other sides of the device.
As shown, the BEOL dielectric layer includes 2 IMD layers which include metal layers M1 and M2. A top metal level M3 is provided over V2. The top metal level is covered by the passivation stack. The metal level M1 is the bottom metal level and the metal level M3 is the top metal level. Providing other numbers of IMD layers may also be useful. The number of IMD layers may depend on the CMOS process employed. Typically, the pre-metal ILD level is formed using a single damascene process. For example, pre-metal contacts are formed in contact openings of the pre-metal ILD layer to couple to various terminals of the components. The pre-metal contacts may contact S/D regions of the transistors, well contacts and terminals of the sensor. The first metal level of the first IMD layer may employ a single damascene or an RIE process. As for M2 metal lines of the second metal dielectric layer and V1 via contacts of the first via dielectric layer, they may be formed by a dual damascene process. Likewise, M3 metal lines and V2 via contacts may be formed by a dual damascene technique. Other configurations of processes for forming the various IMD layers may also be useful.
The BEOL provides interconnections between the CMOS components and sensor region to operate the sensor. For example, the CMOS components provide power to the sensor, switching it on and off. In addition, the CMOS components enable storing and reading out information from the sensor. The CMOS components may also be configured to perform other functions.
In some embodiments, the sensor region includes a sensor array with a plurality of sensors arranged in a matrix with rows and columns of sensors. Each sensor corresponds to a pixel of an array of pixels. The CMOS components, for example, may include select switches, row and column decoders and readout circuits. Other CMOS components may also be included. The CMOS components are configured to read out each pixel of the array. Once the full array of sensors is read out, an image may be reconstructed. The image, for example, is one frame corresponding to the sensors of the array.
In one embodiment, the BEOL and pre-metal dielectric material in the sensor region is removed to expose the sensor. For example, the removal of the dielectric over the sensor forms an upper sensor or BEOL cavity 264. In one embodiment, metal lines and vias may be provided in the BEOL to facilitate structuring the profile of the cavity. For example, the metal lines and vias may form a dam structure surrounding the sensor region, preventing the dielectric layers from eroding into the CMOS region from the release processes.
A cap 240 is disposed on the substrate, encapsulating the CMOS and sensor regions. The cap is disposed on the periphery of the device within the bond pads. For example, the bond pads are disposed outside of the encapsulated CMOS and sensor regions. This enables access to the bond pads. The cap includes an upper cap portion and a lower cap portion. The cap portions may be integrated. For example, the cap portions are formed by a single cap material. As shown, the upper and lower portions of the sides of the cap are aligned. Alternatively, the upper portion may protrude over the bond pad, resulting in non-aligned upper and lower portions on the side with the bond pads. Other configurations of the cap may also be useful.
A cap cavity 265 is provided in the lower portion of the cap and is over the CMOS region and sensor region with the upper cavity 264. The cap cavity and the upper sensor cavity may be collectively referred to as the cap cavity. In one embodiment, the cap cavity is a vacuum. The cap is formed of a material which is transparent to infrared radiation. For example, the cap is capable of transmitting infrared radiation to the sensor. The cap may be a silicon (Si) cap. Other types of materials, such as germanium (Ge), silicon-germanium (SiGe) or zinc sulfide (ZnS), may also be used to form the cap. Providing a cap formed from other types of materials which transmit infrared radiation may also be useful.
In one embodiment, the cap includes an anti-reflective region 244. The anti-reflective region facilitates the transmission of infrared radiation through the cap. In one embodiment, the anti-reflective region includes a bottom grating on the inner (bottom) surface of the cap and a top grating on the outer (top) surface of the cap. The gratings can have a moth-eye grating pattern or structure to facilitate the transmission of infrared radiation. The gratings may have other patterns which facilitate the transmission of infrared radiation. The gratings may be formed by etching the surfaces of the cap. Anti-reflective regions are described in, for example, co-pending U.S. patent application Ser. No. 17/612,200, filed on Nov. 17, 2021, which is already herein incorporated by reference for all purposes.
In another embodiment, the anti-reflective region includes an anti-reflection coating disposed on the front and back sides of the cap. Materials with a different reflective index may be deposited alternatively on the surfaces of the anti-reflective region. For example, materials for the anti-reflection coating may be zinc sulfide (ZnS) or germanium (Ge). Providing any other materials and deposition techniques for the anti-reflective coating may also be useful. The anti-reflective coating may be deposited on the surfaces of the cap and patterned to remain in the anti-reflective region.
A getter (not shown) may be disposed on the inner surface of the cap. The getter, for example, may be disposed on the inner surface of the cap in a recessed region adjacent to the anti-reflective region. The getter absorbs moisture and outgassing within the encapsulated device. The getter, for example, may be zirconium (Zr) alloys, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba) or magnesium (Mg). Other types of getter materials such as rare earth elements including cerium (Ce) or lanthanum (La) may also be useful. The getter facilitates maintaining the integrity of the vacuum in the cavity, improving reliability.
In one embodiment, a sealing ring 282 is employed to facilitate the bonding of the cap to the substrate. The sealing ring, for example, includes a cap sealing ring 282b and a substrate sealing ring 282a. The cap sealing ring, in one embodiment, surrounds the sensor and CMOS regions. The cap and substrate sealing rings are mated, bonding the cap to the substrate. In one embodiment, the sealing rings may be a metal or metal alloy. The sealing rings may be gold-based sealing rings, such as gold, gold-tin or a combination thereof. Providing other materials and structures for the sealing rings may also be useful. In one embodiment, the sealing rings are mated by thermal compression. Other techniques for bonding the cap to the substrate by forming thermal compression bonds or eutectic bonds may also be useful.
The cap may be part of a cap wafer which is processed to form a plurality of caps. The cap wafer may be bonded to a wafer with a plurality of devices. For example, wafer-level vacuum packaging bonds the caps to the devices. The cap wafer and device wafer are diced to separate the devices into individual vacuum-packaged devices.
As described, the sensor region includes 1 sensor. However, it is understood that the sensor region may include a plurality of sensors. The sensors, for example, may be configured in a matrix format with rows and columns of sensors forming a sensor array. Each sensor, for example, may correspond to a pixel of an image, such as a thermal image.
In one embodiment, as shown in
In one embodiment, the first and second body segments are configured to have about the same surface area. For example, the first body segment (first main and lead segments) has about the same surface area as the second body segment (second main and lead segments). For example, the first and second body segments are essentially symmetrical. Variations in processing may occur, causing variances in the surface areas of the first and second body segments. Preferably, the variance is less than about ±5%. Providing other variances between the surface areas of the body segments may also be useful. For example, the surface area differences may be less than about ±20%.
In other embodiments, the body segments may not be symmetrical. For example, it is not crucial or necessary for the body segments to be symmetrical. In some cases, it may be desirable to have body segments which are not symmetrical. For example, in the case that p-doped poly is more efficient in IR absorption, then the p-doped body may be configured to be larger than the n-doped body segment to increase IR absorption efficiency. Other configurations of the body segments may also be useful.
In one embodiment, the sensor body is rectangular-shaped. For example, the first and second body segments, when combined, form a rectangular-shaped sensor body. In one embodiment, the first and second main segments together form a rectangular shape main segment portion of the sensor body. The first and second lead segments extend from the first and second main segments. The first and second lead segments are configured to form the rectangular-shaped sensor body. In one embodiment, the first body segment and the second body segment have similar shapes except that they are flipped vertically and horizontally. Other configurations of the sensor body segments and/or shaped sensor body may also be useful. The lead or extended segments also advantageously serve as an absorber (e.g., doped poly absorber).
As shown, a main segment is essentially a right isosceles triangular-shaped member while a lead segment is an elongated-shaped member that extends from one end of the main segment between the base and one of the sides of the isosceles triangular-shaped member. Other shaped main segments may also be useful. For example, the shapes of the sensor body may depend on design requirements such as available space. The lead segment is connected to the main segment and extends outwardly and along the sides of the isosceles-shaped member. The main segment and the lead segment are separated by an L-shaped gap 389 (e.g., main-lead gap) therebetween. The first and second main segments are similarly shaped segments except that one is flipped vertically and horizontally from the other. In one embodiment, the first and second main segments are isolated segments. In some cases, the segments may be connected by undoped anchors. In other cases, the segments are completely isolated from each other. The gaps are provided to avoid dopant diffusion.
Anchors 352 may be provided within the base gap between the bases. The anchors, for example, are connected portions of the first and second main segments within the base gap, as illustrated by
In one embodiment, the sensor body is a polysilicon sensor body. Other types of materials which are stable under high temperatures having thermoelectric properties may also be used to serve as the sensor body. For example, such materials may include silicon germanium (SiGe), gallium nitride (GaN) or a 2D material, such as graphene, black phosphorus or molysulfide.
In one embodiment, the sensor body is doped with p-type and n-type dopants to form p and n regions. Doping, for example, may be achieved using ion implantation with a mask. For example, to form the p region of the sensor body, p-type dopants are implanted into the sensor body with the n region masked off, such as with a resist or implant mask. Similarly, to form the n region of the sensor body, n-type dopants are implanted into the sensor body with the p region masked off. The doping of the body segments, for example, may be integrated into the S/D doping processes of the p-type and n-type transistors. Other techniques for doping the body segments may also be useful. For example, separate doping processes may be employed to form the doped body segments.
In one embodiment, the sensor body is patterned prior to doping. For example, after the patterning process to form the sensor body (e.g., first and second body segments and anchors), it is doped to form n and p regions. The ends of the first and second lead segments serve as the first and second sensor terminals. The first and second terminals are, for example, the cold-ends of the sensor. The sensor body also includes spaces or gaps, such as the main-lead and base gaps. Other configurations of gaps may also be useful. The gaps facilitate a release process for forming the lower sensor cavity as well as creating thermal isolation between the main segments and the lead segments. The patterning process may include mask and etch processes, such as a patterned resist mask to serve as an etch mask for a reactive ion etch (RIE) process.
In the case of a polysilicon-based sensor body, it may be formed with the polysilicon layer used to form the gate electrodes. For example, the CMOS process may include a gate electrode layer for gate electrodes and may also be employed to also serve as the polysilicon sensor. In the case where the CMOS process includes more than one polysilicon gate electrode layer, the thinner polysilicon gate electrode layer may be preferably selected to serve as the polysilicon sensor. Alternatively, the gate electrode layer matching or closely matching the desired thickness of the sensor body thickness is preferably selected. In another embodiment, a separate layer may be employed to serve as the sensor body. Other configurations of forming the gate and sensor body may also be useful.
In one embodiment, a sensor body contact 355 couples the first and second body segments. As shown, the sensor body contact is disposed on the top surface of the sensor body. For example, the sensor body contact is disposed on the top surface which is opposite of the bottom surface facing the lower sensor cavity. In one embodiment, the sensor body contact is disposed at about an interface of the first and second main segments. For example, the sensor body contact is provided over the base gap between the main segments. As shown, the sensor body contact occupies a central portion of the interface of the first and second main segments between the anchors. It may be preferable to have the body contact as short as possible. However, there is a minimum length required to ensure mechanical strength and adhesion between the contact and the sensor body. The minimum length depends on, for example, the baseline design rules to accommodate the body contacts. Illustratively, the length of the sensor body is about ⅓ the total length of the base gap between the anchors. Other configurations, including the length of the sensor body contact, may also be useful.
As shown, the sensor body contact includes first and second sensor body via contacts 357P and 357N connected to the first and second body segments. Bottom surfaces of the first and second body via contacts are coupled to the first and second main segments. A sensor body interconnect 356 interconnects the top surfaces of the first and second via contacts. For example, the sensor body interconnect electrically connects the first and second body segments together. In one embodiment, the sensor body via contacts are closed loop via contacts. For example, a closed loop via contact includes a metal contact configured as a metallic ring which forms a closed loop. As shown, the via contacts are configured as rectangular-shaped metallic rings. Within the closed is a dielectric fill 386, as shown in
The sensor body contact, in one embodiment, includes a high-temperature contact. For example, the sensor body contact can sustain subsequent process temperatures. The components of the sensor body contact may be formed of titanium (Ti), aluminum (Al), copper (Cu) or a combination thereof. Other types of high-temperature metals may also be used to form the components of the sensor body contact. The type of material used for the contact may depend on the technology node. For example, matured technology nodes may employ Al while advanced technology nodes may employ Cu.
In some embodiments, silicide contacts 358 are provided on main segments, as shown in
As discussed, the first and second body segments are doped with first and second dopants, such as p-type and n-type dopants. In one embodiment, the sheet resistance of the body segments is adjusted to match the ambient (atmospheric) sheet resistance, which is about 377 Ω/square. Tuning the sheet resistance of the body segments to the atmospheric sheet resistance advantageously enables the body sensor to serve as an absorber, obviating the need to use a separate absorber layer. An additional absorber, such as TiN or SiN may be disposed on the body segments even though the body sensor already serves as an absorber. This further enhances IR absorption.
In other embodiments, a separate absorber (not shown) is provided on the main segments if the sensor body does not serve as an absorber. Examples of configurations of absorbers are shown and described in
The absorber may be provided when the sensor body sheet resistance is not tuned to the ambient sheet resistance. In other embodiments, the absorber is provided in addition to having the sensor body tuned to match the ambient sheet resistance. This may further enhance absorption.
The absorber, for example, is configured to absorb incident infrared radiation. The absorber may be a silicon nitride layer. Other types of absorbers, such as titanium nitride (TiN), nickel-chromium (NiCr) or other materials, may also be useful. In one embodiment, the absorber is configured to be part of an interferometric system which absorbs most of the incident infrared radiation. For example, the absorber interferometric system may be configured to absorb greater than 80% of incident infrared radiation having a wavelength of 8-14 μm. Providing any other configurations of the absorber may also be useful. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2-5 μm.
A sensor protection layer (not shown) may be provided over the absorber layer. Examples of different configurations of the sensor protection layer are shown and described in
The absorber may have various configurations. For example, the absorber may be separated from the sensor body by a dielectric liner, such as silicon oxide. Alternatively, the absorber may be embedded within a dielectric layer, such as silicon oxide, which is encased by a sensor protection layer, such as SiN. Other configurations of the absorber may also be useful.
As shown, the sensor includes a sensor body with first and second sensor segments 451P and 451N. The first body segment, for example, is doped with p-type dopants and the second body segment is doped with n-type dopants. The first body segment includes a first main segment 453PM and a first lead segment 453PL; the second body segment includes a second main segment 453NM and a second lead segment 453NL.
A sensor body contact 455 is provided to electrically connect the first and second body segments. The sensor body contact includes first and second sensor body via contacts 457P and 457N connected to the first and second body segments. A sensor body interconnect 456 interconnects the body via contacts. The sensor body via contacts, for example, are closed loop via contacts.
Unlike the embodiments of
As shown, the sensor includes a sensor body with first and second sensor segments 551P and 551N. The first body segment includes a first main segment 553PM and a first lead segment 553PL; the second body segment includes a second main segment 553NM and a second lead segment 553NL. The sensor body may include anchors 552 within the base gap between the main segments. In one embodiment, first and second anchors are provided proximate to opposing ends of the base gap 588. Other configurations of the anchors may also be useful. For example, a greater or lesser number of anchors may be provided.
A sensor body contact 555 electrically connects the first and second body segments. The sensor body contact includes first and second sensor body via contacts 557P and 557N connected to the first and second body segments. A sensor body interconnect 556 interconnects the body via contacts. The sensor body via contacts, for example, are closed loop via contacts. As shown, the sensor body contact occupies a central portion of the interface of the first and second main segments between the anchors. The sensor contact should have a minimum length to ensure sufficient mechanical stability of the free-standing sensor body. Anchors can be provided to provide additional support. In the case that the sensor body contact is sufficiently long, anchors may be eliminated. It is understood that the larger the sensor body contact, the lower the contact resistance. Also, the larger the sensor body contact, the smaller the absorber is. This reduces absorption efficiency. As shown, the length of the sensor body is about ⅓ the total length of the base gap between the anchors. Other configurations of the sensor body contact may also be useful. In some embodiments, silicide contacts 558 are provided on main segments, as shown in
Unlike the embodiments of
The gaps reduce or minimize the thermal capacity of the sensor body. The absorber can be provided to the sensor body. In one embodiment, in the case of metallic absorbers, the sheet resistance should be configured to have ambient sheet resistance to enhance or maximize IR absorption or to reduce or minimize reflection. Other configurations of absorbers may also be useful.
In one embodiment, the gap patterns include a plurality of slots or elongated openings along a first direction. As shown, the slots are along the x-direction. Alternatively, the slots may be along the second or y-direction. Providing other configurations of gap patterns may also be useful. The pattern, in particular, dimensions and spacing should be selected to improve absorption. For example, the spacing or gaps or openings should be less than ¼ wavelength to avoid impacting absorption. For example, openings may be a matrix of openings, such as square, rectangular, circle, oval, other geometric shapes or a combination thereof. For example, it may also include a combination of different-shaped openings as well as a combination of elongated and isolated openings in first or second directions. In a preferred embodiment, the gap pattern is configured to maximize the surface area of the openings or gaps within a body segment. The gap pattern should still provide the necessary mechanical stability.
As shown, the sensor includes a sensor body with first and second sensor segments 651P and 651N. The first body segment includes a first main segment 653PM and a first lead segment 653PL; the second body segment includes a second main segment 653NM and a second lead segment 653NL.
A sensor body contact 655 electrically connects the first and second body segments. The sensor body contact includes first and second sensor body via contacts 657P and 657N connected to the first and second body segments. A sensor body interconnect 656 interconnects the body via contacts. The sensor body via contacts, for example, are closed loop via contacts. As shown, similar to
Similar to
The gaps reduce or minimize the thermal capacity of the sensor body. The absorber can be provided to enhance IR absorption. In the case that the absorber is metallic, it should be configured to have an ambient sheet resistance to optimize absorption or minimize reflection.
In one embodiment, the gap patterns include a plurality of slots or elongated openings along a second direction. As shown, the slots are along the y-direction. Alternatively, the slots may be along the x-direction. Providing other configurations of gap patterns may also be useful. For example, openings may be a matrix of openings, such as square, rectangular, circle, oval, other geometric shapes or a combination thereof. For example, may include a combination of different-shaped openings as well as a combination of elongated and isolated openings in first or second directions. The pattern, such as dimensions and spacing, should be selected to improve absorption. For example, the spacing or gaps or openings should be less than ¼ wavelength to avoid impacting absorption. In a preferred embodiment, the gap pattern is configured to provide sufficient mechanical stability to maintain the free-standing sensor body physically intact without impacting absorption and maximize the surface area of the openings or gaps within a body segment.
A portion of the sensor body shown includes with first and second main segments 753PM and 753NM. The main segments include a base gap 788 separating them. A sensor body contact 755 electrically connects the first and second main segments. The sensor body contact includes first and second sensor body via contacts 757P and 757N connected to the first and second main segments. A sensor body interconnect 756 interconnects the body via contacts. The sensor body via contacts, for example, are closed loop via contacts. To reduce contact resistance, silicide contacts (not shown) may be provided on main segments.
In one embodiment, an absorber 790 is disposed over the sensor body. As shown, the absorber is disposed over the main segments of the sensor body. As previously discussed, the absorber may also be disposed over the lead segments of the sensor body. The absorber, for example, is configured to absorb incident infrared radiation. The absorber may be a SiN layer. Other types of absorbers may also be useful. The absorber layer should be resistant to the etchant of the second release process. The thickness of the absorber may be about 30-100 nm. Other thicknesses may also be useful.
In one embodiment, a dielectric liner 791 may be provided between the absorber and sensor body. The dielectric liner, for example, may be silicon oxide. Other types of dielectric liners may also be useful. The dielectric liner may be provided to reduce film stress and improve adhesive between the sensor body and the absorber layer. For example, the silicon oxide liner layer may reduce stress and improve adhesion between the polysilicon sensor body and the silicon nitride absorber layer. The dielectric liner and absorber may be referred to as an absorber stack. As shown, the absorber includes absorber studs to protect the sidewalls of the dielectric liner. For example, the dielectric liner is encased within the absorber. This prevents the dielectric liner from being eroded during the release processes to form the free-standing sensor and lower sensor cavity. The studs may be formed by patterning the dielectric liner to form a stud trench. The stud trench, for example, surrounds a main segment and a lead segment. For example, first and second stud trenches are formed for the first and second sensor body segments. The absorber is formed on the dielectric liner, filling the stud trenches and tops of the dielectric liner. The absorber stack is patterned to cover the patterned sensor body. For example, the absorber stack is patterned to cover the main segments of the sensor body. As shown, the dielectric liner below the absorber over the base gap 788 is removed during the release processes.
A portion of the sensor body shown includes with first and second main segments 753PM and 753NM electrically coupled by a sensor body contact 755. In one embodiment, an absorber 790 is disposed over the sensor body. As shown, the absorber is embedded within an absorber protection stack. In one embodiment, the absorber is embedded in an inner protection layer 792 which is encased by an outer protection layer 796. In one embodiment, the inner and outer protection layers are dielectrics. The inner dielectric layer may be silicon oxide while the outer protection layer may be SiN. Other configurations of the protection absorber stack may also be useful. As for the absorber layer, it may be TiN. Other types of absorbers, such as NiCr, may also be useful. In the case of a metallic absorber, its thickness may be tuned such that the absorber has a sheet resistance which matches the ambient sheet resistance. As for the protection absorber stack, the thickness of the inner dielectric layer may be about 100 nm while the thickness of the outer protection layer may be about 50-100 nm. Other thicknesses for the various layers may also be useful.
To form the protected absorber stack, a first dielectric layer may be formed on the sensor body, followed by forming the absorber thereover. After forming the absorber, it is patterned to define the absorber over the sensor segments. A second dielectric layer is formed over the absorber. This, for example, forms a dielectric absorber stack. The dielectric absorber stack may be patterned to form stud trenches followed by forming the sensor protection layer. The sensor protection layer covers the stud trenches and the surface of the dielectric absorber stack. The protected absorber stack is patterned to be over the sensor body. As shown, the dielectric layer below the absorber over the base gap 788 is removed during the release processes.
A portion of the sensor body shown includes with first and second main segments 853PM and 853NM electrically coupled by a sensor body contact 855. The main segments include segment gaps 858.
In one embodiment, an absorber 890 is disposed over the sensor body. As shown, the absorber is disposed over the main segments of the sensor body. In one embodiment, a dielectric liner 891 may be provided between the absorber and sensor body. The dielectric liner and absorber may be referred to as a lined absorber stack. In one embodiment, the lined absorber stack is a conformal stack. For example, the lined absorber stack conforms to the topography of the sensor body. The lined absorber stack may be formed after the sensor body is defined. The dielectric liner, for example, may be silicon oxide. For example, the dielectric liner is configured to reduce film stress and improve adhesion between the sensor body and absorber layer. Other types of dielectric liners may also be useful.
As shown, the absorber includes absorber studs to protect the sidewalls of the dielectric liner over the sensor body. For example, the dielectric liner on the top surface of the sensor body is encased within the absorber. This prevents the dielectric liner from being eroded during the release processes to form the free-standing sensor and lower sensor cavity. The studs may be formed by patterning the dielectric liner, which is conformal to the sensor body, to form first and second stud trenches for the first and second sensor body segments. The absorber is formed on the patterned dielectric liner, filling the stud trenches and the top surface of the dielectric liner. The lined absorber stack is patterned to be disposed over the sensor body. As shown, the dielectric liner outside of the absorber studs and below the absorber over the base gap 888 is removed during, for example, the second release process.
A portion of the sensor body shown includes with first and second main segments 853PM and 853NM electrically coupled by a sensor body contact 855. The main segments include segment gaps 858.
In one embodiment, a protected absorber stack is disposed over the sensor body. The protected absorber stack is conformal to the topography of the sensor body. As shown, the protected absorber stack is disposed over the sensor body. In one embodiment, the protected absorber stack includes an absorber 890 embedded in a dielectric layer 892 which is completely encased by sensor protection layer 896. For example, the dielectric layer is encased by upper and lower sensor protection layers and sensor protection studs. In one embodiment, a dielectric liner 891 is disposed between the sensor body and protected absorber stack.
To form the protected absorber stack, a dielectric liner is conformally formed over the sensor body. The dielectric liner is patterned to form first or liner stud trenches on the sensor body. A lower sensor protection layer is formed on the dielectric liner. The lower sensor protection layer fills the line stud trenches and the surface of the liner. After forming the lower sensor protection layer, a lower dielectric layer is formed thereover. The lower dielectric layer, for example, fills the gaps between the segment gaps and covers the top surface of the lower sensor protection layer. The absorber is formed on the lower dielectric layer. The absorber is patterned to be over the sensor body. An upper dielectric layer is formed over the lower dielectric layer and absorber. The dielectric absorber stack is patterned to form second or upper stud trenches of the upper and lower dielectric layer. An upper sensor protection layer is formed, filling the upper stud trenches and covering the upper dielectric layer. The protected absorber stack and dielectric liner are patterned to be over the sensor body. As shown, the dielectric liner outside of the lower studs and over the base gap 888 is removed during, for example, the second release process.
Referring to
As shown in
In one embodiment, a lower sensor cavity 960 is formed in the sensor region of the substrate. The lower sensor cavity may be formed by etching the substrate using a mask. The mask, in one embodiment, may be a patterned photoresist mask with an opening corresponding to the lower sensor cavity. Alternatively, the mask may be a hard mask, such as silicon oxide, silicon nitride or metal lines in the ILD layers which are patterned with a photoresist mask to include an opening corresponding to the lower sensor cavity. An anisotropic etch, such as a reactive ion etch (RIE), etches the substrate to form the lower sensor cavity.
A reflector 962 is formed at the bottom of the lower sensor cavity. In one embodiment, the reflector is a metal silicide layer formed at the bottom of the lower sensor cavity. The metal silicide reflector may be a TiSix, WSix or AlSix reflector. Other types of metal silicide reflectors may also be useful.
To form the reflector, a conductive metal layer is formed on the substrate. The conductive metal layer may line the surface of the substrate and the bottom of the lower sensor cavity. In one embodiment, the mask used to form the substrate remains. As such, the conductive metal layer covers the mask on the surface of the substrate. In the case of a photoresist mask, it is removed after depositing the conductive metal layer. This removes the conductive metal layer over the mask, leaving a portion of the conductive metal layer which covers the bottom of the lower sensor cavity. An anneal is performed, causing a reaction between the conductive metal and silicon substrate of the cavity bottom to form the metal silicide layer. In the case of a hard mask, the metal layer over the substrate is not removed. The hard mask prevents the reaction with the substrate. Unreacted metal and the hard mask are removed after the annealing process. Removing the unreacted metal and hard mask may be achieved using a first wet etch.
Alternative types of reflectors may also be formed at the bottom of the lower sensor cavity. In another embodiment, the reflector is a doped region at the bottom of the cavity. For example, an implant may be performed using the mask that forms the lower sensor cavity. The implant implants reflector dopants to form the reflector at the bottom of the lower sensor cavity. The reflector dopants may be n-type or p-type. The dopant concentration of the reflector is selected accordingly to reflect infrared radiation at a desired degree of reflection. For example, the dopant concentration of the doped reflector layer may be about 1021 dopants/cm3. The conductive properties of the surface of the doped region are attributed to the high concentration of dopants being applied, thereby enabling the reflection of the incoming infrared radiation. After implanting the dopants, the implant mask is removed.
In other embodiments, the reflector may be a non-conductive reflector, such as a photonic crystal reflector. For example, a photonic crystal layer is formed by etching the surface of the lower sensor cavity. The photonic crystal layer may include a grating pattern configured to reflect incident infrared radiation. For example, different grating patterns of varying depths may be etched from the surface of the photonic crystal layer to adjust the wavelengths and properties of the reflected infrared radiation. The photonic crystal layer may include a grating pattern configured to reflect incident radiation. Forming other types of reflectors may also be useful.
Referring to
A sacrificial layer 964 is formed on the substrate, as shown in
A dielectric layer 914 is formed on the substrate, as shown in 9f. The dielectric may be a silicon oxide layer. Other types of dielectric layers may also be formed. The dielectric layer is patterned, leaving it remaining over the lower sensor cavity with the sacrificial fill. The dielectric layer protects the sensor region while the CMOS region is processed. The dielectric layer defines a top of the lower sensor cavity and serves as a membrane for a sensor in the sensor region. The dielectric layer may be formed by CVD and patterned using mask and etch processes. In addition, the dielectric layer may serve as a sacrificial support on which a sensor is formed. The dielectric layer or sensor support, for example, is removed during the release processes. In one embodiment, the sensor support is removed during the second release process to form the free-standing sensor.
Referring to
As shown, isolation regions 980 are formed on the substrate to isolate the different regions of the substrate. The isolation regions, for example, may also be provided for well contact regions. The isolation regions, for example, are field oxide (FOX) isolation regions. The FOX regions may be formed by selective thermal oxidation of the substrate using a nitride mask. Other types of isolation regions may also be useful. For example, the isolation regions may be shallow trench isolation (STI) regions. The STI regions are trenches formed in the substrate and are filled with a dielectric material, such as silicon oxide. The STI regions may have a coplanar top surface with the substrate produced by CMP. In one embodiment, the STI regions are formed prior to dopant implantation so as not to be influenced by their growth by the doping of the silicon.
Gate layers are formed on the substrate. In one embodiment, the gate layer includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer may be a thermal oxide layer while the gate electrode layer may be a polysilicon layer. The gate electrode layer may be formed by CVD. The gate electrode layer, for example, covers the substrate in the CMOS and sensor regions. In one embodiment, the gate layers are patterned to form gates 923 in the transistor regions. For example, the gate layers are patterned to form the gates in the CMOS region and removed in the sensor region. Patterning the gate layers may be achieved using mask and etch techniques. For example, the gate layers are patterned by RIE using a patterned resist mask. A gate includes a gate electrode 923 over a gate dielectric 913. Other processes or configurations of processes may also be employed to form the gates.
In
In one embodiment, a sensor body 950 is formed on the dielectric layer over the filled lower sensor cavity in the MEMS region. For example, a sensor body layer, such as polysilicon is formed. The sensor body layer is patterned to form the sensor body, such as those previously described. Other types of sensor body layers may also be useful. For example, the sensor body layer may be silicon germanium (SiGe), gallium nitride (GaN) or a 2D material, such as graphene, black phosphorus or molysulfide. As shown, the sensor body includes gaps or spaces 954, as previously described, to facilitate release processes performed subsequently. Other techniques or processes for forming the sensor body may also be useful. After forming the sensor body, the mask protecting the CMOS region is removed.
As described, the gates and transistor gates are formed using separate processes. In other embodiments, the gates and sensor body may be formed in the same process. For example, gate layers are deposited on both the CMOS and sensor regions. The gate layers can be patterned using the same etch mask to form gates in the transistor regions and the sensor body in the sensor region. For example, the gate electrode and sensor body are formed from the same gate electrode layer and patterned using the same etch process.
Source/drain (S/D) regions 9241-2 are formed adjacent to the gates, as shown in
In one embodiment, lightly doped extension regions are formed adjacent to gates. P-type lightly doped extension regions are formed adjacent to the gate of the p-type transistor and n-type lightly doped extension regions are formed adjacent to the gate of the n-type transistor. Dielectric sidewall spacers may be formed on the sidewalls of the gates to facilitate the formation of the lightly doped extension regions. Spacers may also be formed on the dielectric layer or sensor support 914 when forming the gate sidewall spacers. After forming the spacers, the lightly doped extension regions are formed. Separate implants may be employed to form different types of lightly doped extension regions using implant masks, such as photoresist masks. After an implant, the implant mask is removed.
After forming the extension regions, a spacer dielectric layer is formed on the substrate. The spacer dielectric layer may be a silicon oxide layer. Other types of spacer dielectric layers may also be useful. An anisotropic etch is performed, removing horizontal portions of the spacer dielectric layer, and leaving spacers on the sidewalls of the gate. P-type S/D regions are formed adjacent to the gate of the p-type transistor and n-type S/D regions are formed adjacent to the gate of the n-type transistor. Separate implants may be employed to form different types of S/D regions using implant masks, such as photoresist masks.
After forming the S/D regions, a sensor implant process may be performed. For example, dopants are implanted to form the n-doped and p-doped sensor segments of the sensor body. The implants may dope the sensor segments to tune the sensor body having an ambient sheet resistance to also serve as an absorber. Separate implant processes may be employed for the n-doped and p-doped sensor segments.
As described, the implants to form the S/D regions are separate from those used to form the sensor. For example, the S/D implant mask protects the sensor during a S/D implant and the sensor implant mask protects the transistor during a sensor implant. In alternative embodiments, the implants used to form S/D regions of the transistors may be integrated into the process for forming the segments of the sensor body. For example, the p-type or n-type sensor segments are doped with the same implant process as the p-type or n-type S/D regions or body layer may be the same as the gate electrode layer. Other configurations of forming the sensor body and S/D regions may also be useful.
Metal silicide contacts may be formed on the substrate. For example, metal silicide contacts may be formed on the S/D regions, gates, well contacts as well as sensor via contact regions and sensor terminal contact regions on the sensor body. A metal layer, such as Ti, W, Co or Al, may be deposited on the substrate and annealed to cause a reaction between the metal and silicon to form metal silicide contacts. Unreacted metal is removed by, for example, a wet etch, leaving the metal silicide contacts. In other embodiments, the metal silicide contacts for the CMOS region and sensor region may be separate processes.
In some embodiments, after forming the sensor body, an absorber is formed on the sensor body. The absorber layer may include an absorber protection layer or stack, as described in, for example,
In
Referring to
The contacts, for example, are formed by a single damascene technique. The single damascene technique includes forming vias, filling the vias with a contact layer, and polishing, such as CMP, to remove excess contact material. Forming contacts using other techniques may also be useful.
In
A passivation layer is formed over the uppermost metal or pad level. For example, the passivation layer is formed over M3 which serves as a pad level. The passivation layer, for example, is part of the BEOL dielectric layer. In one embodiment, the passivation layer is a passivation stack PS with multiple passivation layers. In one embodiment, the passivation stack includes first, second and third passivation dielectric layers 976, 978 and 979. The passivation stack is configured to protect the BEOL from damage during the release processes. For example, the second passivation layer protects the BEOL dielectric during the second release process which removes the third passivation layer. In one embodiment, the passivation stack includes a silicon oxide/silicon nitride/silicon oxide stack. For example, the first passivation layer is a silicon oxide layer, the second passivation layer is a silicon nitride layer and the third passivation layer is a silicon oxide layer. Other configurations of the passivation stack may also be useful. The passivation layer may be formed by CVD.
In one embodiment, the BEOL dielectric layer includes a BEOL protection wall 981 surrounding the sensor region. The BEOL protection wall is formed with via contacts and metal lines of the metal and via levels, including the C0 level. In some embodiment, the BEOL protection wall may also include undoped polysilicon, such as that used to form the gates. The BEOL protection wall is configured to prevent the BEOL dielectric from damage within the active CMOS region during the release processes. The BEOL protection wall also serves to define the sensor region, enabling the release processes to be performed. For example, the BEOL protection wall prevents etchants, in particular, from the second release processes from penetrating the BEOL dielectric within the active CMOS region. The active CMOS region, for example, is the region outside of the BEOL protection wall and includes active or functional CMOS interconnect components. In one embodiment, the BEOL protection wall includes a double wall configuration with wall discontinuities to accommodate connections. The double wall configuration extends an etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Preferably, the double wall configuration maximizes the etchant path from the sensor region to the BEOL dielectric in the active CMOS region.
Referring to
As shown in
The process continues to perform a first release of the double release process. The first release process removes the sacrificial fill in the lower cavity. This forms the lower sensor cavity 960. In one embodiment, a dry etch is performed to remove the sacrificial fill. The etchant etches the sacrificial layer with a high etch rate compared to the metal as well as the dielectric material of the BEOL dielectric, the protective liner and sensor support. For example, the etchant is highly selective to metal and silicon oxide. In one embodiment, a xenon difluoride (XeF2) etchant is employed for the first release process. In another embodiment, isotropic sulfur hexafluoride (SF6) etchant is used as an alternative etchant to XeF2. Other types of etchants or etch processes may also be useful.
In
Referring to
In another embodiment, the substrate portion of the sealing ring can be formed by the uppermost metal level. For example, the metal pattern of the uppermost metal level may include the substrate portion of the sealing ring. The substrate portion of the sealing ring is exposed by patterning the passivation stack. For example, the passivation stack may be patterned to form a sealing ring opening to expose the substrate portion of the sealing ring and pad openings to expose bond pads.
The cap may be bonded using, for example, thermal compression. For example, the cap and substrate sealing rings are bonded together by thermal compression. Thermal compression may be performed at the wafer level. For example, wafer-level vacuum packaging may be employed to form the cap. The cap is bonded prior to dicing the wafer to separate the devices.
The cap, in one embodiment, is formed of a material transparent to infrared radiation. For example, the cap is capable of transmitting infrared radiation to the sensor. The cap, for example, may be a silicon cap. Other types of materials which transmit infrared radiation may also be useful.
In one embodiment, the cap includes an anti-reflective region 944. The anti-reflective region facilitates the transmission of infrared radiation through the cap. The anti-reflective region may include a bottom grating (not shown) on the inner (bottom) surface of the cap and a top grating (not shown) on the outer (top) surface of the cap. The gratings can have a moth-eye grating pattern or structure to facilitate the transmission of infrared radiation. Other grating patterns for the gratings may also be useful. Other types of anti-reflective regions may also be useful.
In some embodiments, the anti-reflective region includes anti-reflection coatings disposed on the front and back sides of the cap. Materials with a different reflective index may be deposited alternatively on the surfaces of the anti-reflective region. For example, materials for the anti-reflection coating may be zinc sulfide or germanium (Ge) and deposited in the same manner as the moth-eye grating pattern or structure. Providing any other materials and deposition techniques for the anti-reflective coating may also be useful.
A getter (not shown) may be disposed on the inner surface of the cap. For example, the bottom surface of the cap may include a recess 941 over the CMOS region. The getter may be disposed in the recess on the bottom surface of the cap. The getter absorbs moisture and outgassing within the encapsulated device. The getter, for example, may be zirconium alloys, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba) or magnesium (Mg). Other types of getter materials such as rare earth elements including cerium (Ce) or lanthanum (La) may also be useful. The getter facilitates maintenance of the vacuum, improving reliability. Other configurations of the cap may also be useful. After completion of wafer-level packaging, the wafer is diced to singulate the wafer into individual device packages.
As shown, the sensor region includes a sensor 1050. The sensor includes a sensor body first and second body segments. The first body segment includes a first main segment 1053PM and a first lead segment 1053PL and the second body segment includes a second main segment 1053NM and a second lead segment 1053NL. At an end of the first and second lead segments, first and second terminal via contacts 1032P and 1032N are provided. For example, the first terminal via contact is disposed at about an end of the first lead segment and the second terminal via contact is disposed at about an end of the second lead segment. First and second sensor via contacts 1057P and 1057N are disposed at about an interface of the first and second main segments.
In one embodiment, the via contacts are closed-loop via contacts. Providing closed-loop via contacts improves the mechanical stability of the free-standing sensor after the second release process. Other types of via contacts may also be useful. The terminal and sensor via contacts, for example, may be disposed within the pre-metal or C0 dielectric level. For example, the via contacts provide interconnections to interconnects on the first metal (M1) dielectric level.
In one embodiment, a BEOL protection wall 1081 surrounds the sensor region. As shown, the protection wall is a rectangular-shaped protection wall. Other shapes for the protection wall may also be useful. The BEOL protection wall includes via contacts and metal lines or interconnects of the metal and via levels of the BEOL dielectric (including the C0 level). The BEOL protection wall may also include polysilicon patterned on the surface of the substrate (e.g., gate layers). The BEOL protection wall is configured to prevent the BEOL dielectric from damage within the active CMOS region during the release processes. For example, the BEOL protection wall prevents etchants from the release processes from penetrating the BEOL dielectric within the active CMOS region.
As shown, sensor terminal interconnects 1030 are coupled to the sensor via contacts and a sensor contact interconnect 1056 couples the sensor via contacts together. In one embodiment, a first sensor terminal interconnect 1030P is connected to the first sensor via contact; a second sensor terminal interconnect 1030N is connected to the second sensor via contact. The sensor terminal and sensor contact interconnects, for example, are M1 interconnects.
In one embodiment, the BEOL protection wall includes a double wall configuration. As shown, the BEOL protection wall includes inner and outer protection walls 1081I and 1081O. The double wall configuration extends an etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Preferably, the double wall configuration maximizes the etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Other configurations of the BEOL protection wall may also be useful.
Discontinuities are provided in the BEOL protection wall. In one embodiment, the discontinuities are provided to accommodate metal interconnects to the sensor. Preferably, the discontinuities are provided to accommodate metal interconnects to the sensor and to extend the etchant path of the release processes as long as possible to the CMOS active region.
In one embodiment, the C0, M1 and V1 levels of the outer protection wall include terminal interconnect discontinuities 1083O to accommodate the sensor terminal interconnects 1030. The C0, M1 and V1 levels of the protection wall include a first outer wall terminal interconnect discontinuity 1083OP to accommodate the first sensor terminal interconnect and a second outer wall terminal interconnect discontinuity 1083ON to accommodate the second sensor terminal interconnect. For example, the C0 contact 1033C0, the M1 interconnect 1034M1 and V1 of the outer protection wall includes first and second outer wall terminal interconnect discontinuities. The outer wall terminal interconnect discontinuities avoid shorting of the sensor terminals. As for layers above V1, the outer protection wall does not have any discontinuities.
In one embodiment, the sensor terminal interconnects are part of the M1 metal layer. For example, the first sensor terminal interconnect of the first lead segment of the first body segment is part of the M1 metal layer and the second sensor terminal interconnect of the second lead segment of the second body segment is part of the M1 metal layer. Other configurations of the sensor terminal interconnects may also be useful.
In one embodiment, the inner protection wall 1081i does not include first and second terminal interconnect discontinuities as the outer protection wall. For example, the inner protection wall does not have inner wall discontinuities where the outer wall terminal interconnect discontinuities are located. Instead, the inner protection wall includes first and second inner wall discontinuities 1083i located at other parts of the inner protection wall to avoid shorting the first and second terminal interconnects. For example, the various layers of the inner protection wall include first and second inner wall discontinuities. The first and second inner wall discontinuities avoid shorting of the first and second terminal interconnects. In one embodiment, the inner wall discontinuities are configured to provide a long travel path for the etchants of the double-release process to the active CMOS region of the BEOL dielectric. Preferably, the inner wall discontinuities provide the longest possible travel path for the etchants of the double-release process to the active CMOS region of the BEOL dielectric.
As shown, the inner protection wall includes first and second inner protection wall discontinuities. The first and second inner protection wall discontinuities are disposed at opposing diagonal portions of the inner protection wall. For example, the first and second inner protection wall discontinuities are disposed at opposing diagonal portions at all levels. The opposing diagonal portions are distal from the outer protection wall terminal interconnect discontinuities. For example, the first and second inner protection wall discontinuities are located far away from the first and second outer protection wall terminal interconnect discontinuities. Preferably, the first and second inner protection wall discontinuities are located as far away as possible from the first and second outer protection wall terminal interconnect discontinuities.
In one embodiment, the M1 terminal interconnects are coupled to the C0 via contacts. The first and second inner wall discontinuities enable a long etchant path of the second release process to prevent damage to the active CMOS BEOL dielectric, as illustrated by the arrows. This prevents the etchant from damaging the BEOL dielectric in the active CMOS region from the second release process.
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The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. The scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
This application claims the benefit of U.S. Provisional Application Ser. No. 63/279,682, filed on Nov. 16, 2021. This application is also a continuation-in-part of U.S. patent application Ser. No. 17/612,200, filed on Nov. 17, 2021; a continuation-in-part of U.S. patent application Ser. No. 17/440,784, filed on Sep. 19, 2021; a continuation-in-part of U.S. patent application Ser. No. 17/440,175, filed on Sep. 16, 2021; a continuation-in-part of U.S. patent application Ser. No. 17/439,797, filed on Sep. 15, 2021 which are all a continuation-in-part of U.S. patent application Ser. No. 17/156,639, filed on Jan. 25, 2021. The disclosures of above said applications are herein incorporated by reference in their entireties for all purposes.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/SG2022/050830 | 11/16/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63279682 | Nov 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17612200 | Nov 2021 | US |
| Child | 18710198 | US | |
| Parent | 17440784 | Sep 2021 | US |
| Child | 18710198 | US | |
| Parent | 17440175 | Sep 2021 | US |
| Child | 18710198 | US | |
| Parent | 17439797 | Sep 2021 | US |
| Child | 18710198 | US | |
| Parent | 17156639 | Jan 2021 | US |
| Child | 18710198 | US |
