Patent Application
20140179106
The invention relates to a method of forming semiconductor devices on a semiconductor wafer. More specifically, the invention relates to selectively etching a dielectric layer with respect to an organic mask and a metal containing mask or etch stop.
In forming semiconductor devices, some devices may be formed by selectively etching an etch layer with respect to an organic mask and a metal containing mask or etch stop.
To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming devices in an oxide layer over a substrate, wherein a metal containing layer forms at least either an etch stop layer below the oxide layer or a patterned mask above the oxide layer, wherein a patterned organic mask is above the oxide layer is provided. The substrate is placed in a plasma processing chamber. The oxide layer is etched through the patterned organic mask, wherein metal residue from the metal containing layer forms metal residue on sidewalls of the oxide layer. The patterned organic mask is stripped. The metal residue is cleaned by the steps comprising providing a cleaning gas comprising BCl3 and forming a plasma from the cleaning gas. The substrate is removed from the plasma processing chamber.
In another manifestation of the invention, a method for forming devices in an oxide layer over a substrate, wherein a metal containing layer forms at least either an etch stop layer below the oxide layer or a patterned mask above the oxide layer, wherein a patterned organic mask is above the oxide layer is provided. The substrate is placed in a plasma processing chamber. The oxide layer is etched through the patterned organic mask, wherein metal residue from the metal containing layer forms metal residue on sidewalls of the oxide layer. The patterned organic mask is stripped. The metal residue is cleaned by the steps comprising providing a cleaning gas comprising BCl3 and Cl2, wherein the cleaning gas has a flow ratio of BCl3 to Cl2 that is greater than 2:1 and forming a plasma from the cleaning gas, The substrate is removed from the plasma processing chamber.
These and other features of the present invention will be described in more details below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
In the formation of some semiconductor devices, it is desirable to etch a dielectric layer, such as silicon oxide, with respect to an organic mask, such as a spin on material or amorphous carbon, and a metal containing hardmask, such as titanium nitride (TiN) or titanium (Ti). In other semiconductor processes, it is desirable to etch an etch layer disposed below a patterned organic mask with features, where a metal containing hardmask is formed on the bottoms of some of the organic mask features. A photoresist mask may be used to open a pattern in an organic layer to form an organic mask.
Etch Layer with Organic Mask, Metal Containing Hardmask, and Metal Containing Etch Stop
In an embodiment, a substrate with an oxide etch layer disposed under a patterned organic mask with features and a metal containing hardmask at the bottom of features of the patterned organic and a metal containing etch stop is placed in an etch chamber (step 104).
The plasma power supply 306 and the wafer bias voltage power supply 316 may be configured to operate at specific radio frequencies such as, for example, 13.56 MHz, 27 MHz, 2 MHz, 400 kHz, or combinations thereof. Plasma power supply 306 and wafer bias power supply 316 may be appropriately sized to supply a range of powers in order to achieve desired process performance. For example, in one embodiment of the present invention, the plasma power supply 306 may supply the power in a range of 300 to 10000 Watts, and the wafer bias voltage power supply 316 may supply a bias voltage in a range of 10 to 2000 V. In addition, the TCP coil 310 and/or the electrode 320 may be comprised of two or more sub-coils or sub-electrodes, which may be powered by a single power supply or powered by multiple power supplies.
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Information transferred via communications interface 414 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 414, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communication channels. With such a communications interface, it is contemplated that the one or more processors 402 might receive information from a network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that shares a portion of the processing.
The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
The oxide etch layer is selectively etched with respect to the patterned organic mask and the metal containing hardmask or etch stop (step 108). In an embodiment, the oxide etch comprises a plurality of cycles where each cycle comprises a selective mask deposition phase and a selective etch layer etch phase.
An example of a recipe for providing a selective mask deposition phase provides a chamber pressure of 3 mTorr. A deposition gas of 100 sccm Ar, 50 sccm H2, and 15 sccm C4F8 is flowed into the plasma processing chamber 304. 400 watts of RF at 13.56 MHz is provided by the TCP coil 310 to form the deposition gas into a plasma 314. No deposition bias is provided by the wafer bias power supply 316, since the duty cycle is off during the selective mask deposition phase to provide a net deposition. In this example, since the deposition gas is the same recipe as the etch gas, the flow of the deposition gas does not need to be stopped.
An example of a recipe for providing an etch provides a chamber pressure of 3 mTorr. An etch gas of 100 sccm Ar, 50 sccm H2, and 15 sccm C4F8 is flowed into the plasma processing chamber 304. 400 watts of RF at 13.56 MHz is provided by the TCP coil 310 to form the etch gas into a plasma 314. An etch bias of 500 volts, generated by providing an RF at 13.56 MHz, is provided by turning on the bias power from the wafer bias power supply 316 during a pulsed bias, where the etching phase is during the on part of the duty cycle. In this example, since the etch gas is the same recipe as the deposition gas, the flow of the etch gas does not need to be stopped. There may be some deposition during this phase, but during this phase there is no net deposition. More preferably, there is a net removal of the deposition.
If the etch phase does not remove all of the deposition, so that the deposition prevents any of the organic mask and hardmask from being etched, then the resulting etch may have an infinite selectivity for etching the etch layer with respect to both the organic mask and hardmask.
The organic mask is stripped (step 112). An example of a recipe for stripping the organic mask provides a pressure of 5 mTorr. A strip gas of 100 sccm Cl2 and 100 sccm O2 is flowed into the plasma processing chamber 304. A bias of 50 volts is provided. TCP power of 1,000 watts is provided. The process is maintained for 60 seconds.
The metal residue 504 is cleaned (step 116).
An example of a recipe for cleaning, provides a chamber pressure of 10 mTorr. A residue clean gas of 200 sccm BCl3 and 30 sccm Cl2 is flowed from the clean gas source 336 into the plasma processing chamber 304 (step 604). The residue clean gas is formed into a plasma 314 by providing 500 watts RF at 13.56 MHz (step 608). The process is maintained for 5 seconds before the flow of the residue clean gas is stopped (step 612).
Additional processing steps may be performed while the substrate remains in the plasma processing chamber 304. The substrate is then removed from the plasma processing chamber 304 (step 120) after the metal residue is cleaned and after any additional processing steps.
In another embodiment, a residue clean recipe may provide a pressure of 5 mTorr. The clean gas comprises 100 sccm BCl3 and 50 sccm Cl2. 200 watts RF is provided at 13.56 MHz. The process is maintained for 5 seconds.
If the metal residue is not removed from the stack, the metal residue can block pattern transfer and lead to defectivity issues in subsequent processing. In addition, the metal residues can also result in corrosion or condensation defects when exposed to atmosphere. If the metal residue is not removed from the chamber walls 350, the plasma processing chamber 304 is subject to process drift and defectivity. Therefore, cleaning the metal residue from the stack 200 and the chamber walls 350 reduce device defects and plasma processing chamber drift. These embodiments preferably allow cleaning with minimal or no etching of the metal containing hardmask 224 or etch stop layer 208. In addition, these embodiments allow for the simultaneous cleaning of metal deposits on the stack 200 and on the chamber wall 350 with minimal or no etching of the metal containing hardmask 224 or etch stop layer 208.
Although in the previous embodiment, both the hardmask and etch stop are metal containing, in other embodiments only the hardmask is metal containing and the etch stop is not metal containing, or the etch stop is metal containing and the hardmask is not metal containing. In various embodiments, the metal containing hardmask or etch stop may be TiN, Ta, Ti, Ta2O3, Ti2O3, Al2O3, or Al. If the hardmask or etch stop is not metal containing, it may be SiN or another nitride. Preferably, the etch layer is a silicon oxide based layer.
Preferably, the residue clean gas comprises BCl3. More preferably, the residue clean gas comprises BCl3 and Cl2. Preferably, the flow of BCl3 is greater than the flow of Cl2. More preferably, the flow rate of BCl3 is at least twice the flow rate of Cl2. Most preferably, the flow rate of BCl3 is at least five times the flow rate of Cl2. The higher concentration of BCl3 with respect to Cl2 has been found to increase residue removal, while reducing etching of the metal containing hardmask or etch stop. The residue clean gas is fluorocarbon free.
Preferably, the residue cleaning has a self bias of less than 20 volts. More preferably, the residue cleaning has a self bias of 0 volts, so that the RF bias is zero. The low bias allows for removing the metal residue, while minimizing etching.
In one embodiment the metal containing hardmask 224 is removed before removing the stack 200 from the plasma processing chamber 304. In another embodiment, the metal containing hardmask 224 is removed after removing the substrate 204 from the plasma processing chamber 304. In other embodiments, additional steps may be provided. For example, the stack 200 is removed from the plasma processing chamber 304 before the metal hardmask 224 is removed. A second mask may then be formed over the hardmask 224 for a double patterning process. The stack 200 may then be placed in the plasma processing chamber 304 for additional etching. In another embodiment, additional etch steps may be performed before the stack 200 is removed from the plasma processing chamber 304. For example, a subsequent etch may use the etch layer as a mask for etching the metal containing etch stop layer.
While this invention has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.
