Patent Application
20160276091
Embodiments generally relate to circuit boards. More particularly, embodiments relate to inductors for plated through holes on circuit boards.
Circuit boards such as printed circuit boards (PCBs) typically include plated through holes as interconnect structures to electrically couple components. A conventional through hole may traverse an entire cross-section of a circuit board, wherein electrical traces extending from a via portion of the through hole may act as an electrical path to electrically couple components on the PCB. In some cases, the intended signaling portion of a via may cover less than the entire length of the through hole, wherein the remaining unintended signaling portion of the through hole may be considered a stub portion. Electrical traces may interconnect a transition between a surface layer and an internal layer or between two internal layers; the closer the internal routing layer is to the surface layer, the longer the stub portion will be.
The impedance of the stub portion may be approximated by that of a transmission line with an open termination:
Z
OC
=−jZ
0 cot(βl)
where j is an imaginary number, Z0 is a characteristic impedance of the system, β is a propagation constant, and l is the stub length.
For a frequency in the GHz range and a stub length in the millimeter range, the impedance will maintain a negative imaginary value, which is equivalent to a capacitance in shunt with a primary electrical interconnect. This condition may be represented as an equivalent circuit that includes a channel and a capacitance representing a stub portion. The stub portion significantly changes the impedance profile of the through hole, causing severe reflections, resonance, and additional loss. Consequently, the structure is not useful for high speed links. To reduce these effects, the stub may be removed through drilling. However, stub removal may add cost and decrease the mechanical integrity of the circuit board. Micro-via and/or buried via technologies may be used to remove the stub as well. However, these technologies may add significant cost to manufacturing the circuit board.
The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:
In order to compensate for stub capacitance of a plated through hole, a self-coupled inductor may be used. More particularly,
The inductor-compensated plated through hole 110 may conform to typical design rules used in fabricating PCBs or other types of circuit boards. This fabrication may include a plated through hold drill diameter of 10 mils, a conductor cap/pad of 20 mils, a trace width of inductor coils and electrical lead lines of 4 mils with a spacing of 3.5 mils, and adjacent plated through hole spacing (pitch) of 39 mils. These parameters make the plated through hole 110 along with an adjacent plated through hole (shown in
Although the plated through hole 110 of
In addition to transitions between layers, the self-coupled inductor configuration may be used with plated through holes in a same-layer transition. Such a compensated plated through hole 210 is depicted in
The self-coupled inductor compensated plated through holes of the above embodiments may find application in a variety of situations such as, for example, high speed signaling (e.g., 16 GHz for PCIe (Peripheral Components Interconnect Express) signals having data rates of 25 Gbps or above for SerDes (Serializer-Deserializer) between a variety of devices on the same or other circuit boards. The plated through holes may also couple to devices not located on circuit boards. Such devices include, but are not limited to, processors, controllers, memory, switches, complex programmable logic devices, programmable logic arrays, integrated circuits, or other passive components such as capacitors, resistors, inductors, etc. A variety of applications may use the plated through holes of the present embodiments. These applications may include, for example, PCIe-4 (Peripheral Components Interconnect Express), USB (Universal Serial Bus, e.g., USB Specification 3.1, Rev. 1.0 Jul. 26, 2013), SOC (System On a Chip), Unified I/O (Input/Output), On-processor Interconnects, MIPI (Mobile and Mobile Influenced), I/O PHYs (Input Output PHYsical layer connections), MPCIe (Mini Peripheral Components Interconnect Express), and non-PSP.
Depending upon the application, the performance of the self-coupled inductor compensated plated through holes described above may be enhanced through the application of magnetic materials between the two inductors (e.g., a nickel coating in the plated through hole or addition of a high permeability material). Resistor termination of the stub portion may be added to increase high frequency performance although low frequency performance is diminished.
Example 1 may include a circuit board system including a first circuit board including a first device selected from a processor, a controller, a memory, a switch, a complex programmable logic device, a programmable logic array, or an integrated circuit; a first plated through hole having a first via portion and a first stub portion; a first self-coupled inductor electrically coupled to the first via portion, the first self-coupled inductor including a first inductor in series with a second inductor, the first and second inductors being mutually coupled to reduce a capacitive effect of the first stub portion; and a second device selected from a processor, a controller, a memory, a switch, a complex programmable logic device, a programmable logic array, or an integrated circuit, the second device electrically coupled to the first circuit board.
Example 2 may include the circuit board system of example 1, wherein the first printed device is a processor and the second device is a memory.
Example 3 may include the circuit board system of example 1, wherein the first and second inductors are first and second approximately 180 degree paths connected to the first plated through hole.
Example 4 may include the circuit board system of example 3, wherein the first approximately 180 degree path is positioned at a first layer on the first circuit board and the second approximately 180 degree path is positioned at a second layer on the first circuit board.
Example 5 may include the circuit board system of example 3, wherein the first approximately 180 degree path and the second approximately 180 degree path are positioned on a same layer on the first circuit board.
Example 6 may include the circuit board system of example 1, wherein the first inductor is positioned at a first layer on the first circuit board and the second inductor is positioned at a second layer on the circuit board.
Example 7 may include the circuit board system of example 1, wherein the first and second inductors are positioned on a same layer on the first circuit board.
Example 8 may include the circuit board system of example 1, wherein the first plated through hole is capped with a conductor.
Example 9 may include the circuit board system of any one of examples 1 to 8, wherein the second device is positioned on a second circuit board.
Example 10 may include the circuit board system of example 9, wherein the second circuit board includes a second plated through hole having a second via portion and a second stub portion, the second plated through hole having a second self-coupled inductor electrically coupled to the second via portion, the second self-coupled inductor including a third inductor in series with a fourth inductor, the third and fourth inductors being mutually coupled to reduce a capacitive effect of the second stub portion.
Example 11 may include a circuit board including a plated through hole having a via portion and a stub portion; a self-coupled inductor electrically coupled to the via portion of the plated through hole, the self-coupled inductor structure including a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion.
Example 12 may include the circuit board of example 11, wherein the first and second inductors are first and second approximately 180 degree paths connected to the plated through hole.
Example 13 may include the circuit board of example 12, wherein the first approximately 180 degree path is positioned at a first layer on the circuit board and the second approximately 180 degree path is positioned at a second layer on the first circuit board.
Example 14 may include the circuit board of example 12, wherein the first approximately 180 degree path and the second approximately 180 degree path are positioned on a same layer on the circuit board.
Example 15 may include the circuit board of example 11, wherein the first approximately 180 degree path and the second approximately 180 degree path are positioned such that electricity is to flow in the same direction in the first approximately 180 degree path and the second approximately 180 degree path.
Example 16 may include the circuit board of any one of examples 11 to 15, further comprising a device selected from a processor, a controller, a memory, a switch, a complex programmable logic device, a programmable logic array, or an integrated circuit.
Example 17 may include a method of high-speed signaling between a circuit board and a device including providing a first circuit board including a first device selected from a processor, a controller, a memory, a switch, a complex programmable logic device, a programmable logic array, or an integrated circuit; providing a first plated through hole having a first via portion and a first stub portion; providing a first self-coupled inductor electrically coupled to the first via portion, the first self-coupled inductor including a first inductor in series with a second inductor, the first and second inductors being mutually coupled to reduce a capacitive effect of the first stub portion; providing a second device selected from a processor, a controller, a memory, a switch, a complex programmable logic device, a programmable logic array, or an integrated circuit, the second device electrically coupled to the first circuit board; and sending a high speed signal between the first device and the second device.
Example 18 may include the method of example 17, wherein the first device is a processor and the second device is a memory.
Example 19 may include the method of example 17, wherein the first device is a processor and the second device is a switch.
Example 20 may include the method of example 17, wherein the high speed signal has a data rate up to 30 Gbps.
Example 21 may include the method of example 17, wherein the first and second inductors are first and second approximately 180 degree paths connected to the first plated through hole.
Example 22 may include the method of example 21, wherein the first approximately 180 degree path is positioned at a first layer on the first circuit board and the second approximately 180 degree path is positioned at a second layer on the first circuit board.
Example 23 may include the method of example 21, wherein the first approximately 180 degree path and the second approximately 180 degree path are positioned on a same layer on the first circuit board.
Example 24 may include the method of example 17, wherein the first inductor is positioned at a first layer on the first circuit board and the second inductor is positioned at a second layer on the circuit board.
Example 25 may include the method of example 17, wherein the first and second inductors are positioned on a same layer on the first circuit board.
Example 26 may include the method of example 17, further providing a conductor cap on the first plated through hole.
Example 27 may include the method of any one of examples 17 to 26, further providing a second circuit board to mount the second device.
Example 28 may include the method of example 27, further providing a second plated through hole having a second via portion and a second stub portion on the second circuit board, and further providing a second self-coupled inductor electrically coupled to the second via portion of the second plated through hole, the second self-coupled inductor including a third inductor in series with a fourth inductor, the third and fourth inductors being mutually coupled to reduce a capacitive effect of the second stub portion.
Example 29 may include a system for high speed signaling including first means for providing a high speed signal from a first circuit board; interconnect means having a via portion and a stub portion; inductor means couple to the via portion for reducing a capacitive effect of the stub portion; second means for receiving a high speed signal from the first circuit board.
Example 30 may include the system for high speed signaling according to example 29, wherein the inductor means comprises a self-coupled inductor having first inductor means and second inductor means.
Example 31 may include the system for high speed signaling according to example 30, wherein the first and second inductor means each include an approximately 180 degree path coupled to the interconnect means.
Example 32 may include the system for high speed signaling according to example 31, wherein the first inductor means is on a first level of the circuit board and the second inductor means is on a second level of the circuit board.
Example 33 may include the system for high speed signaling according to example 31, wherein the first inductor means is on a same level of the circuit board as the second inductor means.
Advantageously, the self-coupled inductor compensated plated through holes described in the embodiments can be used in high-speed signaling environments, including data rates of 30 Gbps. Such an approach may facilitate many types of interconnections, such as those between a processor and memory or a processor and a network switch. The self-coupled inductor compensated plated through holes can save the cost of circuit board fabrication as it can avoid drilling plated through holes or buried via technologies. The self-coupled inductor compensated plated holes can have flexibility on designing inductor path configurations and mutual coupling coefficients, and, thus, it can be optimized to compensate the stub capacitance. Compared to a resistor terminated approach, it is more applicable for broadband digital interconnects without compromising low frequency performance.
Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.
Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.
As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A, B, C; A and B; A and C; B and C; or A, B and C.
Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.
