Patent Application
20240234206
The presented disclosure is related to nanofabrication techniques for nanoelectronic devices and structures. More in particular, the disclosed teachings include methods of using irradiation to selectively convert insulating self-developing resists such as metal fluorides into conducting metals as a way to enable electrical elements and structures with dimensions below 5 nm.
With the continual miniaturization of microelectronic devices into the nanometer scale, conventional microfabrication techniques are approaching fundamental limits. As an example, processes such as photolithography, which pattern device structures by depositing metals through lithographic masks, encounter significant challenges when critical dimensions reach the less than 7 nm, and more in particular, 1-2 nm. In what follows, the challenges to fabricate nanodevices at such tiny scales are further described using exemplary structures and devices.
A quantum point contact (QPC) is a narrow constriction between two electrically conducting regions, of a width comparable to the electronic wavelength. The importance of QPCs lies in the fact that they take advantage of quantization of ballistic conductance in mesoscopic systems.
The electron wave can only pass through the constriction if it interferes constructively, which for a given width of constriction, only happens for a certain number of modes N. The current carried by such a quantum state is the product of the velocity times the electron density. These two quantities by themselves differ from one mode to the other, but their product is mode independent.
As a consequence, each state contributes the same amount of e2/h per spin direction to the total conductance G=2Ne2/h. Metal QPCs are structures in which a ‘neck’ of atoms just a few atomic diameters wide (that is, comparable to the conduction electrons' Fermi wavelength) bridges two electrical contacts and have been very difficult to fabricate.
Quantum point contacts were first reported in GaAs/AlGaAs two-dimensional electron gas (2 DEG) channels by taking advantage of the large electron Fermi wavelength in this system at low temperatures. Point contacts were formed by applying a voltage to suitably shaped gate electrodes on the 2 DEG, so that the electron gas could be locally depleted. Conducting regions were thereby created in the plane of the 2 DEG, forming quantum dots and QPCs. Over the past several years, other ways of fabricating QPCs in metals have emerged. For example, QPCs have been realized in break-junctions by pulling apart a piece of conductor until it breaks. The breaking point forms the point contact but is very difficult to keep stable. Another means of creating QPCs is by positioning the tip of a scanning tunneling microscope close to the surface of a conductor. So far, QPCs have remained laboratory curiosities, as they can only be formed at low temperatures in high-mobility heterostructures or in mechanically unstable systems. Stable QPCs for circuits have so far been elusive as the dimensions required have been beyond our reach.
As silicon semiconductor devices are scaled down to nanometer dimensions, the underlying physics governing their behavior undergoes fundamental changes. Phenomena that previously allowed precise control of conductivity through doping are rendered inapplicable. At tiny scales of less than 7 nm, atomic dopants act as mere scattering centers rather than enhancing conductivity. Therefore, alternative approaches must be considered at the nanoscale.
One option may be vacuum tube devices comprised of electrodes surrounded by air or vacuum rather than semiconductors. However, these devices are presently limited by the high voltages required to induce current flow due to the work function of the electron emitter material. For example, tungsten has a work function around 4 eV. Even with modifications, the voltage remains on the order of volts, leading to extremely high impedance. This restricts applications, especially at high frequencies.
This limitation can be overcome by reducing the electrode gap such that direct electron tunneling between electrodes can effectively take place. As an example, by shrinking the gap below approximately 2 nm, the required voltage can be dramatically reduced along with device impedance. This is analogous to scanning tunneling microscopy, where atomic resolution imaging relies on maintaining sub-nanometer gaps during scanning. The challenge lies in fabricating such tiny gaps to create functional in-plane vacuum devices serving as transistor replacements in integrated circuits. Realizing this goal would allow improved scaling of electronic systems.
In view of the above, new nanofabrication methods capable of producing functional structures and devices at tiny length scales of less than 7 nm range are needed.
The disclosed methods and devices address the problems and technical issues as described in the previous section.
According to a first aspect of the present disclosure, a method of fabricating a miniature quantum point contact is disclosed, the method comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist, and exposing the second layer to an electron beam to generate a miniature quantum point contact, the miniature quantum point contact having a constriction width of less than 7 nm.
According to a second aspect of the present disclosure, a method of fabricating a miniature wire is disclosed, the method comprising: providing a first layer comprising an insulated layer with two metal contacts on top; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist; exposing the second layer to an electron beam going from one metal contact to another metal contact of the two metal contacts, across an exposure line, thereby forming the miniature wire that connects the two metal contacts, the miniature wire having a width of less than 7 nm.
According to a third aspect of the present disclosure, a method of via-hole fabrication is disclosed, the method comprising: providing a first layer serving as a substrate; depositing a second layer on top of the first layer, the second layer comprising an electron beam resist; exposing the second resist layer with an electron beam to generate a miniature hole inside the second layer;
the miniature hole having a constriction width of less than 7 nm; and by using the second layer as an etch mask, etching through the first layer, to generate a via through the miniature hole and inside the first layer, the via having with a width of less than 7 nm.
According to a fourth aspect of the present disclosure, a method of generating interconnects is disclosed, the method comprising: providing a first layer serving as a substrate; depositing a second layer on top of the first layer, the second layer comprising an electron beam resist; exposing the second layer with an electron beam to generate miniature trenches inside the second layer, based on an interconnection scheme, the miniature trenches having widths of less than 7 nm, and electroplating metal into the second layer along the miniature trenches.
According to a fifth aspect of the present disclosure, a method of fabricating an array of miniature quantum points contacts is disclosed, the method comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an electron beam resist, and exposing the second layer to an array of electron beams to generate the array of miniature quantum point contacts, the miniature quantum point contacts having each a constriction width of less than 7 nm.
According to a sixth aspect of the present disclosure, A method of fabricating a miniature conducting point contact comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist, and exposing the second layer to an electron beam to generate a miniature conducting point contact, the miniature conducting point contact having a constriction width of less than 7 nm.
Further aspects of the disclosure are provided in the description, drawings and claims of the present application.
Throughout this document, the term “miniature”, when used to describe a device or structure, is defined as having a width less than 7 nanometers (nm). As an example, a “miniature (QPC)” would indicate a QPC with a constriction width on the order of less than 7 nm, e.g., 2 nm. Other examples include a “miniature wire”, referring to a conductive wire with a width below 7 nm, or a “miniature gap”, signifying a separation between two surfaces, structures, or features that is less than 5 nm wide.
Throughout this document the term “electron beam resist” refers to materials, such as metal fluorides (e.g., AlF3, LiF, YbF2, or CuF2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3 etc.). Such materials can be changed by irradiation with an electron beam. Upon exposure, fluorine can evaporate from the exposed area, leaving the metal behind. According to the teachings of the present disclosure, this kind of process can occur at the nanoscale level and, as a result, features with dimensions of less than 7 nm, e.g. 1 nm, can be made when a well-focused electron beam is used to expose the electron beam resist, e.g., fluoride.
On the other hand, the second layer (202) could be an electron beam resist, composed of various materials, such as fluoride-based materials including, for example, AlF3, LiF, YbF2, or CuF2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3. Serving as the top contact, the third layer (203), may also be a metal. In an exemplary embodiment where second layer (202) comprises metal fluoride, during electron irradiation, the fluoride loses its fluorine and converts into metal. The self-developing fluoride layer, with resistivities above 10 ohm·cm, offers excellent electronic isolation. A point contact (204) is formed at the irradiated spot. In an exemplary fabrication process where the electron beam may be focused to, for example, 0.12 nm or less, the resulting point contacts can be between 0.5 and 2 nm in diameter. The embodiments of
Various miniature features have been fabricated to show the feasibility of the disclosed teachings. As an example,
QPCs can be used as extremely sensitive charge detectors. Since the conductance through the contact strongly depends on the size of the constriction, any potential fluctuation (for instance, created by light, magnetic fields, or other electrons) in the vicinity will influence the current through the QPC. It is possible to detect single electrons with such a scheme. In solid-state systems, QPCs can be used as readout devices for the state of quantum bits, as switches, or as transistors. Unlike previous QPC systems, the disclosed devices can be directly integrated into silicon CMOS electronic circuits. This will enable the harnessing of ballistic electron transport through essentially one-dimensional nanometer-scale channels and develop a compelling alternative to 2 DEG heterostructures, quantum wires or nanotubes made from materials systems that are difficult to integrate into silicon circuits.
Using the disclosed teachings, direct writing of miniature wire connecting to metal contacts is made possible.
With continued reference to
In the past, vacuum diodes and triodes with emitter-anode dimensions down to 7 nm have been developed. Same devices with emitter-anode dimensions of less than 7 nm, e.g. 2 nm, can be fabricated based on the described methods. The existing field emission triodes have been limited by the high impedance of the devices, a direct result of the work function of the emitters that limit the minimum operating voltage to above 5V. Several approaches have been adopted to overcome this limitation, including using multi-tip emitters and coating the emitters with low work function materials, but the emission voltage can still not be reduced to below 3V using the existing solutions.
The enhanced lithographic fabrication techniques disclosed herein allow for the construction of structures with, for example, 2 nm electrode spacing, enabling access to the metal-vacuum-metal (MVM) tunneling mechanism. As a result, the construction of MVM triodes and multi-terminal tunnel devices having low impedances becomes feasible. Such devices can exhibit superior performance compared to conventional semiconductor transistors. Furthermore, their robustness is ensured, as MVM tunneling relies on well-established physics-that is used in scanning tunneling microscopes (STM), a common surface characterization technique. The essential dimensions required to implement these devices are readily accessible through the utilization of state-of-the-art silicon fabrication lines.
The present application claims priority to U.S. Provisional Patent Application No. 63/399,510 filed on Aug. 19, 2022, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63399510 | Aug 2022 | US |
