Patent Application
20160005674
This non-provisional application claims priority claim under 35 U.S.C. ยง119(a) on Patent Application No. 103123104 filed in Taiwan, R.O.C. on Jul. 4, 2014, the entire contents of which are hereby incorporated by reference herein.
1. Technical Field
This disclosure relates to an integrated circuit assembly and an integrated circuit packaging structure, and in particular, to an integrated circuit assembly applicable to a heat-dissipation flip-chip packaging structure and an integrated circuit packaging structure.
2. Related Art
Current electronic products need to have high-speed operation and processing capabilities for powerful functions. Moreover, electronic products gradually decrease in size for the purpose of portability. Therefore, the density of arranging electronic components in an apparatus becomes high, causing a challenge of heat dissipation design. During fabrication of an integrated circuit, chip-scale packaging (CSP) is an integrated circuit packaging technology developed to adapt to reduced sizes of electronic products, where flip-chip packaging is a packaging technology that is very popular nowadays.
Refer to ROC Invention Patent 1254433 (referred to as Prior Art I below). Prior Art I discloses a heat dissipation flip-chip apparatus, which has a chip, where a bump is formed on an active surface of the chip, and the chip is then connected to an external solder ball through a lead on a substrate. Moreover, a rear surface of the chip is connected to a heat sink to provide a main heat dissipation path. Because a heat sink of the heat dissipation flip-chip apparatus disclosed in Prior Art I is stacked above the chip, it becomes difficult to achieve an objective of a thin integrated circuit, and an objective of reducing the height of the apparatus is limited.
Refer to ROC Invention Patent 1283447 (referred to as Prior Art II below). Prior Art II discloses a flip-chip thin film packaging structure, which has a flip-chip chip disposed on an upper surface of a flexible substrate, and has a heat sink disposed on a lower surface of the flexible substrate, where the flip-chip chip is connected to the heat sink through a heat conducting through hole passing through the upper surface and the lower surface of the flexible substrate. According to the disclosure in Prior Art II, the heat sink can be disposed on the flexible substrate in a sputtering manner. Because a metal layer formed in a sputtering manner may be very thin and can reach an order of magnitude of micro-meter (um), compared with Prior Art I, further improvement can be made in terms of the height of the flip-chip packaging in Prior Art II. However, through analysis from the structure of the flip-chip chip, the flip-chip chip can only reach an exposed heat sink after at least passing through heterogeneous materials such as a lead layer and a heat conducting through hole; moreover, the size of the heat conducting through hole is limited to some extent; these factors affect the heat dissipation efficiency of the flip chip packaging structure disclosed in Prior Art II.
To solve the foregoing problem, this disclosure provides an integrated circuit assembly and an integrated circuit packaging structure, and in particular, to an integrated circuit assembly applicable to a heat-dissipation flip-chip packaging structure and an integrated circuit packaging structure.
This disclosure provides an integrated circuit assembly, including a chip, an electrical bump, and a heat dissipation bump. The chip has an active surface and an electronic component that is formed by using a semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface.
Moreover, this disclosure further provides an integrated circuit packaging structure, including a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an electronic component formed by using a semiconductor process and an active surface. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame includes a lead, and the lead is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, and the heat dissipation bump and a part of the lead frame are exposed without being covered. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface.
In the integrated circuit assembly and the integrated circuit packaging structure disclosed in this disclosure, a connection relationship between a heat dissipation bump and a chip forms a direct heat dissipation path to the exterior, and therefore, desirable heat dissipation efficiency is achieved in combination with design of an external heat dissipation mechanism. Moreover, the structure of the integrated circuit packaging structure disclosed in this disclosure is simplified, so that the height of the integrated circuit packaging structure can be further lowered, which helps to make an application apparatus of the integrated circuit packaging structure thin; therefore, the integrated circuit packaging structure is very applicable to a portable electronic apparatus.
Features, implementation, and efficacy of the optimal embodiments of the present creation are described below in detail with reference to the accompanying drawings.
The disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the disclosure, and wherein:
The integrated circuit assembly 100 disclosed by this disclosure is applicable to a flip-chip packaging structure introduced subsequently, so that a formed integrated circuit package has advantages of a low height and desirable heat dissipation. The chip 110 is an integrated circuit chip formed by using any semiconductor process, and can include any active component such as a field-effect transistor (FET) and a bipolar junction transistor (BJT), or include any passive component such as a resistor, a capacitor, an inductor, and a diode. The electrical bump 120 is used for transferring an electrical signal, so that a circuit on the chip 110 can electrically communicate with an external circuit. The heat dissipation bump 130 is used as a heat dissipation path for the chip 110, so that a working heat source generated by the chip 110 can be effectively dissipated outside by using the heat dissipation bump 130.
In addition, to make heat dissipation of the integrated circuit assembly 100 more efficient, the height of the heat dissipation bump 130 relative to the active surface 111 is unequal to that of the electrical bump 120 relative to the active surface 111. For example, in the embodiment disclosed in
To make the height (or distance) of the heat dissipation bump 130 relative to the active surface 111 different from that of the electrical bump 120 relative to the active surface 111, the heat dissipation bump 130 can be connected to the active surface 111 of the chip 110 through a heat conductor 131, and the electrical bump 120 can be connected to the active surface 111 through an electrical conductor 121. The heat conductor 131 is formed by a material, such as metal, having desirable heat conductivity. The electrical conductor 121 is formed by a material, such as metal, having desirable heat conductivity. A height difference formed by the heat conductor 131 and the electrical conductor 121 can make the height (or distance) of the heat dissipation bump 130 relative to the active surface 111 different from that of the electrical bump 120 relative to the active surface 111. Because the heat conductor 131 and the heat dissipation bump 130 directly form a heat dissipation path to the exterior for the chip 110, desirable heat dissipation efficiency is provided. The heat conductor 131 and the electrical conductor 121 can be formed by using methods such as etching, sputtering, exposure and development known in a general semiconductor process, which can be implemented and accomplished by persons of ordinary skill in the art according to requirements of applications by using the known technologies in the art after fully understanding the spirit disclosed in this disclosure and is therefore no longer elaborated herein.
In addition, in yet another embodiment of this disclosure, the heat dissipation bump 130 and the electrical bump 120 can also be directly connected to the active surface 111 of the chip 110; the heat dissipation bump 130 and the electrical bump 120 are different in volume, so that the height of the heat dissipation bump 130 may be formed different from that of the electrical bump 120. For example, the volume of the heat dissipation bump 130 is greater than that of the electrical bump 120, so that the height of the heat dissipation bump 130 relative to the active surface 111 is made different from that of the electrical bump 120 relative to the active surface 111.
A structure formed by the chip 110, the electrical bump 120, and the heat dissipation bump 130 is the integrated circuit assembly 100 disclosed in
In addition, in yet another embodiment of this disclosure, the integrated circuit packaging structure 200 may further include an external bump 260 connected to the part, exposed from the sealant 250, of the lead frame 240. The external bump 260 can be used to be electrically connected to an external circuit conveniently in a manner of, for example, welding, so that a circuit on the chip 110 can electrically communicate with the external circuit.
In yet another embodiment of this disclosure, the lead frame 240 of the integrated circuit packaging structure 200 includes a lead layer 245 (shown in
In the integrated circuit packaging structure 200 disclosed in this disclosure, a connection relationship between a heat dissipation bump 130 and a chip 110 forms a direct heat dissipation path to the exterior, and therefore, desirable heat dissipation efficiency is achieved in combination with design of an external heat dissipation mechanism. Moreover, the structure of the integrated circuit packaging structure 200 is simplified, and a substrate component in a conventional flip-chip package is omitted, so that the height of the integrated circuit packaging structure 200 can be further lowered, which helps to make an application apparatus of the integrated circuit packaging structure 200 thin; therefore, the integrated circuit packaging structure 200 is very applicable to a portable electronic apparatus.
Though the embodiments of the present creation are disclosed above, the embodiments are not used for limiting the present creation; several variations can be made according to the shapes, structures, features, and quantity described in the application scope of the present creation by persons skilled in the art without departing from the spirit and scope of the present creation, and therefore, the patent protection scope of the present creation shall be as defined in the appended claims of the specification.
| Number | Date | Country | Kind |
|---|---|---|---|
| 103123104 | Jul 2014 | TW | national |
