The instant application claims priority to Malaysia Patent Application Ser. No. PI 2018702390 filed Jul. 9, 2018, the entire specification of which is expressly incorporated herein by reference.
This invention relates to an integrated circuit device. In more particular, the invention is about a laterally diffused metal oxide semiconductor device.
The application of laterally diffused metal oxide semiconductor, LDMOS devices in microwave/RF power amplifiers offers several advantages, including high linearity and efficiency, high gain, excellent reliability and competitive cost. In a RF-LDMOS device, a Faraday shield is applied in between a gate and drain for mitigating high electric field at the gate and drain edge, as well as reducing reverse transfer capacitance, which is the gate to drain capacitance, thereby enhancing RF performance.
An example of a LDMOS device is described in U.S. Pat. No. 9,064,868. This integrated circuit device comprises a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, and a Faraday shield positioned laterally between the gate electrode and the drain region, and above the isolation structure. The Faraday shield is formed of a plurality of vertically stacked conductive features, wherein each of the plurality of vertically stacked conductive features is positioned in a separate layer of insulating material.
U.S. Patent Application Publication No. US20140042538 also disclosed a radio frequency LDMOS device having a substrate, a p-type epitaxial layer on the substrate, a p-type well in a first portion of the p-type epitaxial layer, a lightly doped n-type drain region in a second portion of the p-type epitaxial layer, a moderately doped n-type region in a first portion of the lightly doped n-type drain region, a heavily doped n-type drain region in a second portion of the lightly doped n-type drain region, and a heavily doped n-type source region in an upper portion of the p-type well. This RF LDMOS device also includes a gate oxide layer covering a portion of the p-type epitaxial layer between the heavily doped n-type source region and the lightly doped n-type drain region, a polysilicon gate covering the gate oxide layer, an oxide layer covering the polysilicon gate and a portion of the moderately doped n-type region, and a Faraday shield covering a portion of the oxide layer.
Generally, the Faraday shield is connected to a metal by multiple conventional electrical contacts. Since the electrical contacts are separate components, there is no continuous current flow from the Faraday shield to the metal, and the conductive surface is small. This drawback leads to low current capacity transmission.
The present invention relates to an integrated circuit device comprising a plurality of metals disposed on surface of the integrated circuit device, and a Faraday shield connected to one of the metals through at least one conductive interconnect, wherein the interconnect is produced by a damascene process and forms a continuous connection to the metal from the Faraday shield.
In a preferred embodiment of the present invention, the integrated circuit device further comprises a substrate as a base of the integrated circuit device, a semiconductor layer disposed on top of the substrate, an isolation layer positioned on top of the semiconductor layer, wherein the metals are disposed above the isolation layer, and a transistor including a source and drain region, and a gate electrode.
In one embodiment of the present invention, the interconnect further comprises a conductive material layer extended from the metal to the Faraday shield in which the interconnect is connected thereto.
The present invention further comprises at least one mask layer for joining more than one interconnects together to form the continuous connection to the metal layer from the Faraday shield.
It is preferred that the Faraday shield is positioned laterally between the gate electrode and the drain region in the isolation layer.
In a preferred embodiment, the Faraday shield consists of a plurality of insulative layers and at least one conductive layer.
It is preferred that the insulative layer is any one or a combination of silicon nitride and silicon rich oxide.
Preferably, the conductive layer is any one or combination of titanium nitride, tungsten and silicide.
The semiconductor layer is preferred to be an epitaxial layer.
Preferably, the source, drain and gate electrode are respectively connected to the metals by an electrical contact.
A main purpose of this invention is to introduce a solution to existing integrated circuit devices, especially laterally diffused metal oxide semiconductor devices that utilizes a plurality of electrical contacts for connecting the Faraday shield to a metal. Such conventional method does not provide continuous and large surface area for current flow. The present invention suggested the use of an interconnect that allows continuous and bulk current flow. In addition, it also provides large surface area for current flow. It is preferred that a single interconnect is utilized in the present invention such that it eliminates the need for installation or formation of multiple electric contacts. However, the present invention also supports the use of more than one interconnect by connecting the interconnects together via at least one mask layer. The damascene process for forming the interconnect allows the interconnect that connects the Faraday shield to a metal to be manufactured at the same time as the installation or formation of other electrical contacts that connect other components, including the electrical contacts which connects the drain and source region, and the gate electrode to the metals respectively. The continuous interconnect formed through the damascene process is simple and less complicated as the conventional method that requires installation or formation of several electric contacts which can only support low current density. Moreover, more than one interconnect can be formed through the present invention to enhance the continuation of connection from the Faraday shield to the metal with different conductive materials. Further, the continuous interconnect allows the fabrication of a smaller cell for the integrated circuit device.
For a better understanding of the invention, preferred embodiments of the invention that are illustrated in the accompanying drawings will be described in detail.
The present invention discloses an integrated circuit device. In more particular, the integrated circuit device is a laterally diffused metal oxide semiconductor, LDMOS device. The LDMOS device is suitable for use in radio frequency, RF devices and therefore, the integrated circuit device can be a RF-LDMOS device.
In a preferred embodiment, the present invention comprises a substrate (101) as a base of the integrated circuit device. On top of the substrate (101) is a semiconductor layer (102) sandwiched between the substrate (101) and an isolation layer (103). It is preferred that the semiconductor layer (102) is an epitaxial layer. A plurality of metals (110a, 110b, 110c, 110d) are disposed above the isolation layer (103). A transistor including a source (107) and drain (108) region, and a gate electrode (109) employed in the present invention. The source (107) and drain (108) region, and gate electrode (109) are respectively connected to the metals (110a, 110b, 110c, 110d) by electrical contacts (113a, 113b, 113c).
Referring to
A primary feature of the present invention is the incorporation of a continuous conductive interconnect (112) that connects the Faraday shield (111) to one of the metals (110c) above the Faraday shield (111). The interconnect (112) as illustrated in
In another embodiment of the present invention as illustrated in
According to the preferred embodiment of the present invention as depicted in
The process flow of producing the present invention starts from forming the transistor after the substrate (101), semiconductor layer (102) and isolation layer (103) are formed. The conductive feature on the source (107) and drain (108) region, as well as the gate electrode (109) are formed via salicidation process that involves the reaction of a thin metal film with silicon in the active regions of the device, whereby metal silicide contacts are formed through a series of annealing, etching processes, or a combination thereof.
Following the salicidation process, the Faraday shield (111) is formed by multiple dielectric films and a conductive film. The interconnect (112) is then formed through the damascene processes that starts from etching the dielectric layer to form a recess according to predetermined dimensions for the interconnect (112) on top of the Faraday shield (111). A barrier layer is deposited into the base of the recess to separate the recess from the Faraday shield (111) for preventing diffusion of the material to be deposited into the recess.
The conductive material that forms the interconnect (112) is then deposited into the recess. Applicable conductive materials include copper. The deposition of the conductive material can be carried out by the electroplating process. In a final step of the damascene process, the surface of the interconnect (112) is planarized using chemical mechanical planarization, CMP.
Such process of forming the interconnect (112) allows simultaneously formation of other electric contacts (113a, 113b, 113c) for connecting to other components including the source (107) and drain (108) region, as well as the gate electrode (109). In another preferred embodiment of the present invention as illustrated in
Number | Date | Country | Kind |
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PI 2018702390 | Jul 2018 | MY | national |