Patent Application
20140021469
The disclosure relates generally to integrated circuit (IC) wafers and fabrication, and more particularly, to an IC including a set of sensor structures disposed within a layer of the IC and configured to sense cracks in the IC, a related method of forming, and a design structure.
In integrated circuit (IC) design, a plurality of materials, orientations, and components may be employed by designers to customize and create various ICs. These designs may include the use of copper wire, aluminum wire, silicon layers and many other kinds of components and materials. Standard IC chip fabrication includes the use of Back End Of Line (BEOL) wires to form components such as inductors in and upon ICs. However, as a result of component proximity and/or variances in material properties (e.g., thermal expansion rates) between components such as BEOL wires and silicon, stresses may form in the IC during fabrication. As the IC is subjected to several thermal cycles during fabrication, these stresses may lead to deformation, cracking, and/or IC failure. In some ICs, designers may call for larger wires in designs, thereby enabling larger currents and the creation of discrete structures. However, as components and/or wire sizes increase, the stresses which may be imparted through the differing coefficients of thermal expansion may also increase, resulting in an increase in IC failures (e.g., cracks). Detection of these failures (e.g., cracks) may be difficult, imprecise, and unreliable, requiring complex analysis of each IC manufactured. The complexity of crack detection in current IC chip fabrication technology limits IC inspection and chip design options, and increases the likelihood that malfunctioning and defective ICs go undetected by fabricators and quality analysts.
A first aspect of the disclosure provides an integrated circuit including: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
A second aspect of the disclosure provides a method including: forming a first wiring layer on a substrate, the first wiring layer including a sensor structure; forming a second wiring layer on the substrate above the first wiring layer, the second wiring layer including a wire component located proximate the sensor structure; transmitting an electrical current through the sensor structure, the electrical current passing from a first end of the sensor structure to a second end of the sensor structure; obtaining the electrical current at the second end of the sensor structure; and analyzing the electrical current at the second end of the sensor structure to determine a condition of the second wiring layer.
A third aspect of the disclosure provides a design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing an integrated circuit on a wafer, the design structure including: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
The above and other aspects, features and advantages of the disclosure will be better understood by reading the following more particular description of the disclosure in conjunction with the accompanying drawings.
It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. It is understood that elements similarly numbered between the FIGURES may be substantially similar as described with reference to one another. Further, in embodiments shown and described with reference to
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Sensor structure 50 may be configured to pass an electrical current through a portion of IC 40. The electrical current passing from a first end 730 (shown in
In an embodiment, sensor structure 50 may have a serpentine or woven shape beneath wire component 30. Sensor structure 50 may include a bending, curled, and/or spiral pattern, proximate wire component 30 with increased exposure to wire component 30, thereby increasing potential exposure to crack propagation and formation. Sensor structure 50 may be located proximate and physically distinct and/or isolated from wire component 30. In one embodiment, a portion 52 (shown in phantom) of sensor structure 50 may extend to contact wire component 30 and/or dielectric layer 36.
In an embodiment, sensor structure 180 may be communicatively connected to a via 120 located proximate BEOL elements 130, 132, 134, 140, and 150. Sensor structure 180 may be configured to fracture and/or deform in order to indicate a crack in IC 100, substrate 105, and/or processing/secondary dielectric layers 110, 112, 114, 116, and 170. This indication may be based on a variation in a characteristic (e.g., change in current carrying capacity, resistance, electrical conductance, etc.) of sensor structure 180. In one embodiment, a crack in processing/secondary dielectric layer 116 may propagate and proceed to contact sensor structure 180, fracturing sensor structure 180 and thereby indicating the presence of the crack/changing a characteristic of sensor structure 180.
In an embodiment, sensor structure 180 may have a serpentine shape beneath wire component 130. In this embodiment, sensor structure 180 is formed in a bending, curled, and/or spiral pattern, forming a sensor structure 180 proximate wire component 130, thereby increasing potential exposure to cracks.
Any of substrate 105, and processing/secondary dielectric layers 110, 112, 114, 116, and 170, may be comprised of but not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more Group III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Substrate 105 and layers 110, 112, 114, 116, and 170, may also be comprised of Group II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). The processes to provide substrate 105, as illustrated and described, are well known in the art and thus, no further description is necessary.
First set of dielectric layers 102, 104, 106, 108, and 160, and processing/secondary dielectric layers 110, 112, 114, 116, may include silicon dioxide (SiO2), silicon nitride (SiN), or any other suitable material. Any number of dielectric layers may be located over the IC/chip body, as many other layers included in semiconductor chips now known or later developed. In one embodiment, first dielectric layers 102, 104, 106, 108, and 160, and processing/secondary dielectric layers 110, 112, 114, 116, may include silicon dioxide (SiO2) for its insulating, mechanical and optical qualities. First dielectric layers 102, 104, 106, 108, and 160, and processing/secondary dielectric layers 110, 112, 114, 116 may include, but are not limited to: silicon nitride (Si3N4), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phosho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK™ (a polyarylene ether available from Dow Chemical Corporation), a spin-on silicon-carbon containing polymer material available from JSR Corporation, other low dielectric constant (<3.9) material, or layers thereof. First dielectric layers 102, 104, 106, 108, and 160, and processing/secondary dielectric layers 110, 112, 114, 116, may be deposited using conventional techniques described herein and/or those known in the art.
As used herein, the term “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
Sensor structure 180 may be formed in first dielectric layer 110 through etching or any other known means. In one embodiment, etching may be performed using a reactive ion etch (RIE). As is known in the art of semiconductor fabrication, RIE uses chemically reactive plasma to remove material deposited on wafers/substrates. Differences in width between these openings may allow for utilizing a phenomenon known as inverse RIE lag. Inverse RIE lag, as is known in the art of semiconductor fabrication, causes a faster etch rate in narrower openings (higher aspect ratios) than in openings having larger widths (lower aspect ratios). Inverse RIE lag may be induced under any conditions characterized by high polymerization and high wafer self-bias voltages. In one embodiment, conditions characterized by high polymerization, may include general chemistries such as CxHyFz (Carbon-Hydrogen-Flourine) with high oxide-to-nitride selectivity (where the blanket etch rate ratio is greater than approximately 20:1). In another embodiment, conditions characterized by high polymerization may include O2 (oxygen), a dilutant, and one or more of: C4F6, C5F8, or C4F8. In this case, the dilutant may be, for example, Argon (Ar). High wafer self-bias voltages may, for example, be voltages greater than approximately 500 volts. While specific conditions for facilitating inverse RIE lag are described herein, those conditions are merely illustrative. Inverse RIE lag may be induced under other conditions not specifically described herein. It is understood that IC 100 may be subjected to a single or multiple metallization processes at any time during formation.
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Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both subsurface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
