INTEGRATED CIRCUIT TEST RESULT COMMUNICATION

Abstract

A chip has formed thereon integrated circuit elements, which include a main circuit and an associated non volatile memory structure. A test result associated with prior testing of a function of the main circuit is stored in the non volatile memory structure. Additional apparatus and methods are disclosed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of components of an RFID system, according to various embodiments of the invention.

FIG. 2 is a diagram showing components of a passive RFID tag, including a tag that can be used in the system of FIG. 1, according to various embodiments of the invention.

FIG. 3 is a conceptual diagram illustrating a half-duplex mode of communication between the components of the RFID system of FIG. 1, according to various embodiments of the invention.

FIG. 4 is a flowchart illustrating testing methods according to various embodiments of the invention.

FIG. 5 is a diagram of a wafer having integrated circuit elements formed and tested according to the methods of the flowchart of FIG. 4.

FIG. 6 is a block diagram of integrated circuit elements that can be formed as one or more integrated circuits on the wafer of FIG. 5, according to various embodiments of the invention.

FIG. 7 is a block diagram of an electrical circuit according to some embodiments of FIG. 5, including an RFID tag, and a non volatile memory structure.

FIG. 8 is a diagram illustrating a scheme for storing test results according to various embodiments of the invention.

FIG. 9 is a conceptual diagram illustrating separation of the wafer of FIG. 5 into multiple integrated circuit (IC) chips.

FIG. 10 is a block diagram of an integrated circuit chip shown in FIG. 9, and further showing various embodiments.

FIG. 11 is a flowchart illustrating methods of processing chips, such as those of FIG. 9, according to various embodiments of the invention.

FIG. 12 is a conceptual diagram illustrating a sample processing activity according to embodiments of the methods of FIG. 11.

FIG. 13 is a conceptual diagram illustrating IC chip sorting according to embodiments of the methods of FIG. 11.

FIG. 14 is a conceptual diagram to illustrate sorting RFID IC chips that can be at least partly assembled into RFID tags such as those of FIG. 12 according to embodiments of the method of FIG. 11.

Claims

1. A method, including: forming, on a wafer, integrated circuit elements including a main circuit and a non volatile memory structure associated with the main circuit;testing a function of the main circuit;storing a test result associated with the testing in the non volatile memory structure; andseparating from a remainder of the wafer a chip that includes the integrated circuit elements.

2. The method of claim 1, wherein content of the non volatile memory structure cannot be read by the main circuit.

3. The method of claim 1, wherein the non volatile memory structure includes a fuse.

4. The method of claim 3, wherein the fuse is one of a one-time programmable fuse and a many-times programmable fuse.

5. The method of claim 1, wherein content of the non volatile memory structure can be read by the main circuit.

6. The method of claim 1, wherein the main circuit is a radio frequency identification (RFID) circuit.

7. The method of claim 6, wherein the non volatile memory structure is to store a product code associated with the RFID circuit.

8. The method of claim 1, wherein the storing is performed before the separating.

9. The method of claim 1, wherein the storing is performed after the separating.

10. The method of claim 1, further including: physically probing the wafer to accomplish at least one of the testing and the storing.

11. The method of claim 1, further including: directing radio frequency energy at the wafer to accomplish at least one of the testing and the storing.

12. The method of claim 1, wherein the main circuit is associated with an on-chip antenna after the separating, and wherein storing the test result includes transmitting a signal that is received by the on-chip antenna.

13. The method of claim 12, wherein the main circuit is a radio frequency identification (RFID) circuit, and the test result is a product code associated with the RFID circuit.

14. The method of claim 1, wherein the test result includes one of a passed result, a failed result, and a grade.

15. The method of claim 1, wherein the storing is performed only if the function has passed the test.

16. The method of claim 1, wherein the storing is performed only if the function has failed the test.

17. The method of claim 1, wherein the storing further includes: storing at least a part of the test result as a plurality of individual results corresponding to a plurality of individual tests.

18. The method of claim 1, wherein the storing further includes: storing at least a part of the test result as at least one aggregate result of multiple tests.

19. A wafer having formed thereon integrated circuit elements comprising: a first main circuit; anda first non volatile memory structure associated with the first main circuit, the first non volatile memory structure having stored therein a test result associated with prior testing of a function of the first main circuit.

20. The wafer of claim 19, wherein content of the first non volatile memory structure cannot be read by the first main circuit.

21. The wafer of claim 19, wherein the first non volatile memory structure includes a fuse.

22. The wafer of claim 21, wherein the fuse is one of a one-time programmable fuse and a many-times programmable fuse.

23. The wafer of claim 19, wherein content of the first non volatile memory structure can be read by the first main circuit.

24. The wafer of claim 19, wherein the first main circuit is a radio frequency identification (RFID) circuit.

25. The wafer of claim 24, wherein the first memory structure is to store a product code associated with the RFID circuit.

26. The wafer of claim 19, wherein the integrated circuit elements further include: a second main circuit that is a substantial duplicate of the first main circuit; anda second non volatile memory structure associated with the second main circuit, the second memory structure having stored therein a test result associated with prior testing of a function of the second main circuit.

27. The wafer of claim 26, wherein the first and the second main circuits are radio frequency identification (RFID) circuits.

28. The wafer of claim 26, wherein the integrated circuit elements further include: a first on-chip antenna associated with the first main circuit, anda second on-chip antenna associated with the second main circuit.

29. The wafer of claim 19, wherein the test result comprises one of a passed result, a failed result, and a grade.

30. The wafer of claim 19, wherein the test result comprises a passed result, and excludes a failed result.

31. The wafer of claim 30, wherein the main circuit is a radio frequency identification (RFID) circuit, and the test result comprises a product code associated with the RFID circuit.

32. The wafer of claim 19, wherein the test result comprises a failed result, and excludes a passed result.

33. The wafer of claim 19, wherein the test result comprises individual results of multiple tests.

34. The wafer of claim 19, wherein the test result comprises at least one aggregate result of multiple tests.

35. A device, including: a chip having formed thereon integrated circuit elements including a main circuit and an associated non volatile memory structure having stored therein a test result associated with prior testing of a function of the main circuit.

36. The device of claim 35, wherein content of the non volatile memory structure cannot be read by the main circuit.

37. The device of claim 35, wherein the non volatile memory structure includes a fuse.

38. The device of claim 37, wherein the fuse is one of a one-time programmable fuse and a many-times programmable fuse.

39. The device of claim 35, wherein content of the non volatile memory structure can be read by the main circuit.

40. The device of claim 35, wherein the main circuit is a radio frequency identification (RFID) circuit.

41. The device of claim 40, wherein the non volatile memory structure is to store a product code associated with the RFID circuit.

42. The device of claim 35, wherein the integrated circuit elements further include: an on-chip antenna associated with the main circuit, the on-chip antenna to receive the test result in a signal prior to the test result being stored in the non volatile memory structure.

43. The device of claim 35, further including: an antenna to couple to the chip.

44. The device of claim 35, further including: a base for attaching the chip thereon.

45. The device of claim 44, wherein the base comprises one of a carrier, a strap, and an inlay.

46. The device of claim 35, wherein the test result comprises one of a passed result, a failed result, and a grade.

47. The device of claim 35, wherein the test result comprises a passed result, and excludes a failed result.

48. The device of claim 47, wherein the main circuit is a radio frequency identification (RFID) circuit, and the test result is a product code associated with the RFID circuit.

49. The device of claim 35, wherein the test result comprises a failed result, and excludes a passed result.

50. The device of claim 35, wherein the test result comprises individual results of multiple tests.

51. The device of claim 35, wherein the test result comprises at least one aggregate result of multiple tests.

52. A method, including: preparing a chip having formed thereon integrated circuit elements including a main circuit and a non volatile memory structure for interrogation;interrogating the chip;reading, as a result of the interrogation, from the non volatile memory structure a stored test result associated with prior testing of a function of the main circuit; andprocessing the chip according to the obtained test result.

53. The method of claim 52, wherein the main circuit is a radio frequency identification (RFID) circuit.

54. The method of claim 53, wherein the test result is a product code associated with the RFID circuit.

55. The method of claim 52, wherein the preparing includes separating the chip from a remainder of a wafer.

56. The method of claim 52, wherein the processing includes: discarding the chip if reading the stored test result fails.

57. The method of claim 52, wherein the processing includes: discarding the chip if the stored test result comprises a failed result.

58. The method of claim 52, wherein the processing includes: retaining the chip only if the stored test result comprises a passed result.

59. The method of claim 52, wherein the processing includes: segregating, from a plurality of chips, those chips, including the chip, whose stored test result comprises a passed result.

60. The method of claim 52, wherein the processing includes: segregating, from a plurality of chips, those chips, including the chip, whose stored test result comprises a failed result.

61. The method of claim 52, wherein the processing includes: rendering the stored test result unreadable.

62. The method of claim 52, wherein the stored test result includes a grade, and wherein the processing includes: retaining the chip together with other chips that are associated with the same grade.

63. The method of claim 52, wherein the interrogating includes: probing the chip.

64. The method of claim 52, wherein the interrogating includes: coupling interrogation circuitry to the chip; andsending, from the interrogation circuitry to the chip, a request to retrieve the stored test result.

65. The method of claim 52, wherein the interrogating includes: directing radio frequency energy at the chip; andreceiving backscattered energy from the chip that encodes the stored test result.

66. The method of claim 65, further including: attaching to the chip an antenna to receive the radio frequency energy.

67. The method of claim 65, wherein the integrated circuit elements include an on-chip antenna associated with the main circuit, and wherein the radio frequency energy is backscattered from the on-chip antenna.

68. The method of claim 52, further including: prior to the reading, placing the chip on a base.

69. The method of claim 68, wherein the base comprises one of a carrier, a strap, and an inlay.

70. The method of claim 52, wherein the processing includes: attaching an antenna to the chip.

71. The method of claim 52, wherein the processing includes: creating a radio frequency identification (RFID) tag using the chip.

72. The method of claim 52, further including: prior to the reading, assembling the chip into a radio frequency identification (RFID) tag.

73. The method of claim 52, further including: assembling the chip into a radio frequency identification (RFID) tag using a mass fluidic orientation and assembly technique.

74. The method of claim 52, wherein the reading further includes: reading the stored test result as a plurality of individual results corresponding to a plurality of individual tests.

75. The method of claim 52, wherein the reading further includes: reading the stored test result as at least one aggregate result of multiple tests.