Claims
- 1. An integrated circuit (IC) comprising a plurality of circuit elements interconnected by a secondary conductor through a plurality of vias disposed at a plurality of locations for coupling the plurality of circuit elements as an alternative to a primary conductor.
- 2. The IC of claim 1, wherein the primary conductor is more conductive than the secondary conductor.
- 3. The IC of claim 1, wherein the primary conductor is formed of a low loss metal.
- 4. The IC of claim 3, wherein the low loss metal is copper or copper alloy.
- 5. The IC of claim 3, wherein the low loss metal is aluminum or aluminum alloy.
- 6. The IC of claim 3, wherein the secondary conductor is formed of a lossy metal relative to the low loss metal used for the primary conductor.
- 7. The IC of claim 6, wherein the lossy metal is aluminum or aluminum alloy.
- 8. The IC of claim 1, wherein the plurality of vias are disposed only at both ends of the secondary conductor.
- 9. The IC of claim 1, wherein the plurality of vias are disposed along the entire length of the secondary conductor.
- 10. The IC of claim 1, wherein the secondary conductor is located substantially underneath the primary conductor.
- 11. The IC of claim 1, wherein the secondary conductor has a width that is smaller than the width of the primary conductor.
- 12. The IC of claim 1, wherein the secondary conductor has a height that is thinner than the height of the primary conductor.
- 13. The IC of claim 1, wherein the primary conductor is formed by a low loss metal deposition in a passivation layer that resides on top of an oxide layer where the secondary conductor is formed.
- 14. The IC of claim 1, wherein the secondary conductor is formed in a top-most metal layer among a plurality of metal layers.
- 15. The IC of claim 1, wherein the primary conductor implements an inductor.
- 16. The IC of claim 1, wherein the primary conductor implements a transmission line.
- 17. The IC of claim 1, wherein the secondary conductor has a spiral pattern.
- 18. The IC of claim 1, wherein the secondary conductor is strapped to the primary conductor through the plurality of vias, and wherein the vias are located to reduce changes to RF performance of the primary conductor
- 19. The IC of claim 1, wherein the secondary conductor is formed such that changes to RF performance of the primary conductor are reduced.
- 20. A device comprising an integrated circuit (IC) having included thereon a plurality of circuit elements interconnected by a secondary conductor through a plurality of vias disposed at a plurality of locations for coupling the plurality of circuit elements as an alternative to a primary conductor.
- 21. A method of fabricating an integrated circuit (IC) to facilitate testing of interconnection of circuit elements thereon prior to deposition of a low loss metal, the method comprising:
forming a secondary conductor over a substrate to interconnect a plurality of circuit elements as an alternative to a primary conductor to be formed thereon; and forming a plurality of vias at a plurality of locations for coupling the second conductor to the primary conductor and the plurality of circuit elements.
- 22. The method of claim 21, further comprising:
testing interconnection of the plurality of circuit elements coupled by the secondary conductor.
- 23. The method of claim 22, further comprising:
after the testing, depositing the low loss metal.
- 24. The method of claim 21, wherein the primary conductor is formed with the low loss metal and the secondary conductor is formed with a lossy metal relative to the low loss metal.
- 25. The method of claim 21, wherein the secondary conductor has a height that is thinner than the height of the primary conductor.
- 26. The method of claim 21, wherein the substrate has a thickness that is substantially greater than the thickness of the primary conductor.
- 27. The method of claim 21, wherein the secondary conductor is formed such that changes to RF performance of the primary conductor are reduced.
- 28. The method of claim 21, wherein the vias are formed at locations such that changes to RF performance of the primary conductor are reduced.
RELATED APPLICATION
[0001] This application claims the benefit of provisional U.S. application Ser. No. 60/375,510, filed Apr. 24, 2002, which is incorporated herein by reference in its entirety for all purposes.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60375510 |
Apr 2002 |
US |